Searched refs:pVCpu (Results 1 - 25 of 149) sorted by relevance

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/vbox/src/VBox/VMM/VMMRZ/
H A DVMMRZ.cpp42 * @param pVCpu Pointer to the VMCPU of the calling EMT.
46 VMMRZDECL(int) VMMRZCallRing3(PVM pVM, PVMCPU pVCpu, VMMCALLRING3 enmOperation, uint64_t uArg) argument
48 VMCPU_ASSERT_EMT(pVCpu);
53 if (RT_UNLIKELY( pVCpu->vmm.s.cCallRing3Disabled != 0
72 "VMMRZCallRing3: enmOperation=%d uArg=%#llx idCpu=%#x\n", enmOperation, uArg, pVCpu->idCpu);
75 "VMMRZCallRing3: enmOperation=%d uArg=%#llx idCpu=%#x\n", enmOperation, uArg, pVCpu->idCpu);
83 pVCpu->vmm.s.enmCallRing3Operation = enmOperation;
84 pVCpu->vmm.s.u64CallRing3Arg = uArg;
85 pVCpu->vmm.s.rcCallRing3 = VERR_VMM_RING3_CALL_NO_RC;
90 if (pVCpu
128 VMMRZCallRing3Disable(PVMCPU pVCpu) argument
162 VMMRZCallRing3Enable(PVMCPU pVCpu) argument
194 VMMRZCallRing3IsEnabled(PVMCPU pVCpu) argument
211 VMMRZCallRing3SetNotification(PVMCPU pVCpu, R0PTRTYPE(PFNVMMR0CALLRING3NOTIFICATION) pfnCallback, RTR0PTR pvUser) argument
230 VMMRZCallRing3RemoveNotification(PVMCPU pVCpu) argument
242 VMMRZCallRing3IsNotificationSet(PVMCPU pVCpu) argument
[all...]
/vbox/src/VBox/VMM/VMMAll/
H A DPDMAllCritSectBoth.cpp38 * @param pVCpu Pointer to the VMCPU.
40 VMM_INT_DECL(void) PDMCritSectBothFF(PVMCPU pVCpu) argument
43 Assert( pVCpu->pdm.s.cQueuedCritSectLeaves > 0
44 || pVCpu->pdm.s.cQueuedCritSectRwShrdLeaves > 0
45 || pVCpu->pdm.s.cQueuedCritSectRwExclLeaves > 0);
48 i = pVCpu->pdm.s.cQueuedCritSectRwShrdLeaves;
49 pVCpu->pdm.s.cQueuedCritSectRwShrdLeaves = 0;
53 PPDMCRITSECTRW pCritSectRw = pVCpu->pdm.s.apQueuedCritSectRwShrdLeaves[i];
55 PPDMCRITSECTRW pCritSectRw = (PPDMCRITSECTRW)MMHyperR3ToCC(pVCpu->CTX_SUFF(pVM),
56 pVCpu
[all...]
H A DHMAll.cpp60 * @param pVCpu Pointer to the VMCPU.
63 static void hmQueueInvlPage(PVMCPU pVCpu, RTGCPTR GCVirt) argument
66 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
69 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
73 if (iPage == RT_ELEMENTS(pVCpu->hm.s.TlbShootdown.aPages))
74 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
76 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
85 * @param pVCpu Pointer to the VMCPU.
88 VMM_INT_DECL(int) HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt) argument
90 STAM_COUNTER_INC(&pVCpu
112 HMFlushTLB(PVMCPU pVCpu) argument
136 hmR0PokeCpu(PVMCPU pVCpu, RTCPUID idHostCpu) argument
187 hmPokeCpuForTlbFlush(PVMCPU pVCpu, bool fAccountFlushStat) argument
222 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local
259 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local
381 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local
417 PVMCPU pVCpu = VMMGetCpu(pVM); local
428 HMGetPaePdpes(PVMCPU pVCpu) argument
500 HMSetSingleInstruction(PVMCPU pVCpu, bool fEnable) argument
514 HMHypercallsEnable(PVMCPU pVCpu) argument
525 HMHypercallsDisable(PVMCPU pVCpu) argument
536 HMTrapXcptUDForGIMEnable(PVMCPU pVCpu) argument
548 HMTrapXcptUDForGIMDisable(PVMCPU pVCpu) argument
[all...]
H A DCPUMAllRegs.cpp89 * @param pVCpu The current Virtual CPU.
92 static void cpumGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg) argument
94 Assert(!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
95 Assert(!HMIsEnabled(pVCpu->CTX_SUFF(pVM)));
96 Assert((uintptr_t)(pSReg - &pVCpu->cpum.s.Guest.es) < X86_SREG_COUNT);
98 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
102 pSReg->Attr.n.u4Type = pSReg == &pVCpu->cpum.s.Guest.cs ? X86_SEL_TYPE_ER_ACC : X86_SEL_TYPE_RW_ACC;
112 else if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
124 Assert(!CPUMIsGuestInLongMode(pVCpu));
134 SELMLoadHiddenSelectorReg(pVCpu,
145 CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu) argument
157 CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg) argument
173 CPUMGetHyperCtxCore(PVMCPU pVCpu) argument
184 CPUMGetHyperCtxPtr(PVMCPU pVCpu) argument
190 CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit) argument
197 CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit) argument
204 CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3) argument
214 CPUMGetHyperCR3(PVMCPU pVCpu) argument
220 CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS) argument
226 CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS) argument
232 CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES) argument
238 CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS) argument
244 CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS) argument
250 CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS) argument
256 CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP) argument
262 CPUMSetHyperEDX(PVMCPU pVCpu, uint32_t u32ESP) argument
268 CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl) argument
275 CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP) argument
295 CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX) argument
310 CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR) argument
316 CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR) argument
360 CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0) argument
367 CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1) argument
374 CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2) argument
381 CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3) argument
388 CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6) argument
394 CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7) argument
403 CPUMGetHyperCS(PVMCPU pVCpu) argument
409 CPUMGetHyperDS(PVMCPU pVCpu) argument
415 CPUMGetHyperES(PVMCPU pVCpu) argument
421 CPUMGetHyperFS(PVMCPU pVCpu) argument
427 CPUMGetHyperGS(PVMCPU pVCpu) argument
433 CPUMGetHyperSS(PVMCPU pVCpu) argument
439 CPUMGetHyperEAX(PVMCPU pVCpu) argument
445 CPUMGetHyperEBX(PVMCPU pVCpu) argument
451 CPUMGetHyperECX(PVMCPU pVCpu) argument
457 CPUMGetHyperEDX(PVMCPU pVCpu) argument
463 CPUMGetHyperESI(PVMCPU pVCpu) argument
469 CPUMGetHyperEDI(PVMCPU pVCpu) argument
475 CPUMGetHyperEBP(PVMCPU pVCpu) argument
481 CPUMGetHyperESP(PVMCPU pVCpu) argument
487 CPUMGetHyperEFlags(PVMCPU pVCpu) argument
493 CPUMGetHyperEIP(PVMCPU pVCpu) argument
499 CPUMGetHyperRIP(PVMCPU pVCpu) argument
505 CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit) argument
513 CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit) argument
521 CPUMGetHyperLDTR(PVMCPU pVCpu) argument
527 CPUMGetHyperDR0(PVMCPU pVCpu) argument
533 CPUMGetHyperDR1(PVMCPU pVCpu) argument
539 CPUMGetHyperDR2(PVMCPU pVCpu) argument
545 CPUMGetHyperDR3(PVMCPU pVCpu) argument
551 CPUMGetHyperDR6(PVMCPU pVCpu) argument
557 CPUMGetHyperDR7(PVMCPU pVCpu) argument
569 CPUMGetGuestCtxCore(PVMCPU pVCpu) argument
581 CPUMQueryGuestCtxPtr(PVMCPU pVCpu) argument
586 CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit) argument
600 CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit) argument
614 CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr) argument
627 CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr) argument
657 CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0) argument
730 CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2) argument
737 CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3) argument
745 CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4) argument
770 CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags) argument
777 CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip) argument
784 CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax) argument
791 CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx) argument
798 CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx) argument
805 CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx) argument
812 CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp) argument
819 CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp) argument
826 CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi) argument
833 CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi) argument
840 CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss) argument
847 CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs) argument
854 CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds) argument
861 CPUMSetGuestES(PVMCPU pVCpu, uint16_t es) argument
868 CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs) argument
875 CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs) argument
882 CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val) argument
888 CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit) argument
896 CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden) argument
904 CPUMGetGuestCS(PVMCPU pVCpu) argument
910 CPUMGetGuestDS(PVMCPU pVCpu) argument
916 CPUMGetGuestES(PVMCPU pVCpu) argument
922 CPUMGetGuestFS(PVMCPU pVCpu) argument
928 CPUMGetGuestGS(PVMCPU pVCpu) argument
934 CPUMGetGuestSS(PVMCPU pVCpu) argument
940 CPUMGetGuestLDTR(PVMCPU pVCpu) argument
946 CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit) argument
954 CPUMGetGuestCR0(PVMCPU pVCpu) argument
960 CPUMGetGuestCR2(PVMCPU pVCpu) argument
966 CPUMGetGuestCR3(PVMCPU pVCpu) argument
972 CPUMGetGuestCR4(PVMCPU pVCpu) argument
978 CPUMGetGuestCR8(PVMCPU pVCpu) argument
988 CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR) argument
994 CPUMGetGuestEIP(PVMCPU pVCpu) argument
1000 CPUMGetGuestRIP(PVMCPU pVCpu) argument
1006 CPUMGetGuestEAX(PVMCPU pVCpu) argument
1012 CPUMGetGuestEBX(PVMCPU pVCpu) argument
1018 CPUMGetGuestECX(PVMCPU pVCpu) argument
1024 CPUMGetGuestEDX(PVMCPU pVCpu) argument
1030 CPUMGetGuestESI(PVMCPU pVCpu) argument
1036 CPUMGetGuestEDI(PVMCPU pVCpu) argument
1042 CPUMGetGuestESP(PVMCPU pVCpu) argument
1048 CPUMGetGuestEBP(PVMCPU pVCpu) argument
1054 CPUMGetGuestEFlags(PVMCPU pVCpu) argument
1060 CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue) argument
1101 CPUMGetGuestDR0(PVMCPU pVCpu) argument
1107 CPUMGetGuestDR1(PVMCPU pVCpu) argument
1113 CPUMGetGuestDR2(PVMCPU pVCpu) argument
1119 CPUMGetGuestDR3(PVMCPU pVCpu) argument
1125 CPUMGetGuestDR6(PVMCPU pVCpu) argument
1131 CPUMGetGuestDR7(PVMCPU pVCpu) argument
1137 CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue) argument
1148 CPUMGetGuestEFER(PVMCPU pVCpu) argument
1284 CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t uLeaf, uint32_t uSubLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx) argument
1636 PVMCPU pVCpu = &pVM->aCpus[i]; local
1797 PVMCPU pVCpu = &pVM->aCpus[i]; local
1827 CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0) argument
1834 CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1) argument
1841 CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2) argument
1848 CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3) argument
1855 CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6) argument
1862 CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7) argument
1869 CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value) argument
1910 CPUMRecalcHyperDRx(PVMCPU pVCpu, uint8_t iGstReg, bool fForceHyper) argument
2155 CPUMSetGuestXcr0(PVMCPU pVCpu, uint64_t uNewValue) argument
2205 CPUMIsGuestNXEnabled(PVMCPU pVCpu) argument
2217 CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu) argument
2230 CPUMIsGuestPagingEnabled(PVMCPU pVCpu) argument
2242 CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu) argument
2254 CPUMIsGuestInRealMode(PVMCPU pVCpu) argument
2266 CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu) argument
2279 CPUMIsGuestInProtectedMode(PVMCPU pVCpu) argument
2291 CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu) argument
2303 CPUMIsGuestInLongMode(PVMCPU pVCpu) argument
2315 CPUMIsGuestInPAEMode(PVMCPU pVCpu) argument
2331 CPUMIsGuestIn64BitCode(PVMCPU pVCpu) argument
2360 CPUMIsGuestInRawMode(PVMCPU pVCpu) argument
2374 CPUMRawEnter(PVMCPU pVCpu) argument
2449 CPUMRawLeave(PVMCPU pVCpu, int rc) argument
2553 CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl) argument
2570 CPUMRawGetEFlags(PVMCPU pVCpu) argument
2585 CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags) argument
2635 CPUMHandleLazyFPU(PVMCPU pVCpu) argument
2648 CPUMIsGuestFPUStateActive(PVMCPU pVCpu) argument
2660 CPUMIsGuestDebugStateActive(PVMCPU pVCpu) argument
2673 CPUMIsGuestDebugStateActivePending(PVMCPU pVCpu) argument
2685 CPUMIsHyperDebugStateActive(PVMCPU pVCpu) argument
2698 CPUMIsHyperDebugStateActivePending(PVMCPU pVCpu) argument
2711 CPUMDeactivateGuestDebugState(PVMCPU pVCpu) argument
2723 CPUMGetGuestCPL(PVMCPU pVCpu) argument
2799 CPUMGetGuestMode(PVMCPU pVCpu) argument
2819 CPUMGetGuestCodeBits(PVMCPU pVCpu) argument
2842 CPUMGetGuestDisMode(PVMCPU pVCpu) argument
[all...]
H A DCPUMStack.cpp33 VMMDECL(void) CPUMPushHyper(PVMCPU pVCpu, uint32_t u32) argument
36 pVCpu->cpum.s.Hyper.esp -= sizeof(u32);
37 *(uint32_t *)MMHyperRCToR3(pVCpu->CTXALLSUFF(pVM), (RTRCPTR)pVCpu->cpum.s.Hyper.esp) = u32;
H A DTMAllCpu.cpp69 * @param pVCpu Pointer to the VMCPU.
72 int tmCpuTickResume(PVM pVM, PVMCPU pVCpu) argument
74 if (!pVCpu->tm.s.fTSCTicking)
76 pVCpu->tm.s.fTSCTicking = true;
81 pVCpu->tm.s.offTSCRawSrc = SUPReadTsc() - pVCpu->tm.s.u64TSC;
83 pVCpu->tm.s.offTSCRawSrc = tmCpuTickGetRawVirtual(pVM, false /* don't check for pending timers */)
84 - pVCpu->tm.s.u64TSC;
97 * @param pVCpu Pointer to the VCPU.
99 int tmCpuTickResumeLocked(PVM pVM, PVMCPU pVCpu) argument
141 tmCpuTickPause(PVMCPU pVCpu) argument
162 tmCpuTickPauseLocked(PVM pVM, PVMCPU pVCpu) argument
192 tmCpuTickRecordOffsettedTscRefusal(PVM pVM, PVMCPU pVCpu) argument
233 TMCpuTickCanUseRealTSC(PVM pVM, PVMCPU pVCpu, uint64_t *poffRealTsc, bool *pfParavirtTsc) argument
310 tmCpuCalcTicksToDeadline(PVMCPU pVCpu, uint64_t cNsToDeadline) argument
344 TMCpuTickGetDeadlineAndTscOffset(PVM pVM, PVMCPU pVCpu, uint64_t *poffRealTsc, bool *pfOffsettedTsc, bool *pfParavirtTsc) argument
402 tmCpuTickGetInternal(PVMCPU pVCpu, bool fCheckTimers) argument
437 TMCpuTickGet(PVMCPU pVCpu) argument
449 TMCpuTickGetNoCheck(PVMCPU pVCpu) argument
465 TMCpuTickSet(PVM pVM, PVMCPU pVCpu, uint64_t u64Tick) argument
495 TMCpuTickSetLastSeen(PVMCPU pVCpu, uint64_t u64LastSeenTick) argument
513 TMCpuTickGetLastSeen(PVMCPU pVCpu) argument
552 TMCpuTickIsTicking(PVMCPU pVCpu) argument
[all...]
H A DGIMAll.cpp62 * @param pVCpu Pointer to the VMCPU.
64 VMM_INT_DECL(bool) GIMAreHypercallsEnabled(PVMCPU pVCpu) argument
66 PVM pVM = pVCpu->CTX_SUFF(pVM);
73 return gimHvAreHypercallsEnabled(pVCpu);
76 return gimKvmAreHypercallsEnabled(pVCpu);
88 * @param pVCpu Pointer to the VMCPU.
91 VMM_INT_DECL(int) GIMHypercall(PVMCPU pVCpu, PCPUMCTX pCtx) argument
93 PVM pVM = pVCpu->CTX_SUFF(pVM);
94 VMCPU_ASSERT_EMT(pVCpu);
102 return gimHvHypercall(pVCpu, pCt
153 GIMShouldTrapXcptUD(PVMCPU pVCpu) argument
178 GIMXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis) argument
206 GIMReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) argument
241 GIMWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) argument
[all...]
H A DTRPMAll.cpp50 * @param pVCpu Pointer to the VMCPU.
54 VMMDECL(int) TRPMQueryTrap(PVMCPU pVCpu, uint8_t *pu8TrapNo, TRPMEVENT *penmType) argument
59 if (pVCpu->trpm.s.uActiveVector != ~0U)
62 *pu8TrapNo = (uint8_t)pVCpu->trpm.s.uActiveVector;
64 *penmType = pVCpu->trpm.s.enmActiveType;
79 * @param pVCpu Pointer to the VMCPU.
81 VMMDECL(uint8_t) TRPMGetTrapNo(PVMCPU pVCpu) argument
83 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
84 return (uint8_t)pVCpu->trpm.s.uActiveVector;
95 * @param pVCpu Pointe
97 TRPMGetErrorCode(PVMCPU pVCpu) argument
129 TRPMGetFaultAddress(PVMCPU pVCpu) argument
147 TRPMGetInstrLength(PVMCPU pVCpu) argument
163 TRPMResetTrap(PVMCPU pVCpu) argument
193 TRPMAssertTrap(PVMCPU pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType) argument
226 TRPMAssertXcptPF(PVMCPU pVCpu, RTGCUINTPTR uCR2, RTGCUINT uErrorCode) argument
258 TRPMSetErrorCode(PVMCPU pVCpu, RTGCUINT uErrorCode) argument
290 TRPMSetFaultAddress(PVMCPU pVCpu, RTGCUINTPTR uCR2) argument
309 TRPMSetInstrLength(PVMCPU pVCpu, uint8_t cbInstr) argument
333 TRPMIsSoftwareInterrupt(PVMCPU pVCpu) argument
346 TRPMHasTrap(PVMCPU pVCpu) argument
366 TRPMQueryTrapAll(PVMCPU pVCpu, uint8_t *pu8TrapNo, TRPMEVENT *pEnmType, PRTGCUINT puErrorCode, PRTGCUINTPTR puCR2, uint8_t *pcbInstr) argument
398 TRPMSaveTrap(PVMCPU pVCpu) argument
415 TRPMRestoreTrap(PVMCPU pVCpu) argument
442 TRPMForwardTrap(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t iGate, uint32_t cbInstr, TRPMERRORCODE enmError, TRPMEVENT enmType, int32_t iOrgTrap) argument
864 TRPMRaiseXcpt(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt) argument
893 TRPMRaiseXcptErr(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt, uint32_t uErr) argument
923 TRPMRaiseXcptErrCR2(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt, uint32_t uErr, RTGCUINTPTR uCR2) argument
[all...]
H A DPGMAll.cpp61 PVMCPU pVCpu; member in struct:PGMHVUSTATE
72 DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
73 DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
75 static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
76 static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
400 * @param pVCpu Pointer to the VMCPU.
405 VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault) argument
407 PVM pVM = pVCpu->CTX_SUFF(pVM);
409 Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
410 STAM_PROFILE_START(&pVCpu
509 PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage) argument
555 PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess) argument
607 PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess) argument
720 PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage) argument
809 PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault) argument
832 PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys) argument
855 pdmShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags) argument
879 PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags) argument
899 PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags) argument
914 PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags) argument
935 pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags) argument
979 pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD) argument
1072 pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde) argument
1113 pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD) argument
1215 pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD) argument
1260 pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD) argument
1350 pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode) argument
1410 PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys) argument
1434 pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk) argument
1482 PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr) argument
1499 PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags) argument
1519 PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask) argument
1559 pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd) argument
1602 pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt) argument
1646 pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd) argument
1712 pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4) argument
1753 PGMGstGetPaePdpes(PVMCPU pVCpu, PX86PDPE paPdpes) argument
1776 PGMGstUpdatePaePdpes(PVMCPU pVCpu, PCX86PDPE paPdpes) argument
1805 PGMGetHyperCR3(PVMCPU pVCpu) argument
1818 PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode) argument
1864 PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu) argument
1935 PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal) argument
2044 PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3) argument
2101 PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal) argument
2243 PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer) argument
2303 PGMCr0WpEnabled(PVMCPU pVCpu) argument
2333 PGMGetGuestMode(PVMCPU pVCpu) argument
2345 PGMGetShadowMode(PVMCPU pVCpu) argument
2419 PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe) argument
2563 pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL) argument
2764 PVMCPU pVCpu = &pVM->aCpus[0]; local
2805 PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4) argument
[all...]
/vbox/src/VBox/VMM/include/
H A DPGMGstDefs.h78 # define GST_IS_NX_ACTIVE(pVCpu) (true && This_should_perhaps_not_be_used_in_this_context)
102 # define GST_IS_NX_ACTIVE(pVCpu) (pgmGstIsNoExecuteActive(pVCpu))
109 # define GST_GET_PTE_GCPHYS(Pte) PGM_A20_APPLY(pVCpu, ((Pte).u & GST_PTE_PG_MASK))
112 # define GST_GET_PTE_SHW_FLAGS(pVCpu, Pte) ((Pte).u & (X86_PTE_P | X86_PTE_RW | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G)) /**< @todo Could return P|RW|US|A|D here without consulting the PTE. */
113 # define GST_GET_PDE_SHW_FLAGS(pVCpu, Pde) (true && This_should_perhaps_not_be_used_in_this_context) //??
114 # define GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, Pde) (true && This_should_perhaps_not_be_used_in_this_context) //??
115 # define GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, Pde) (true && This_should_perhaps_not_be_used_in_this_context) //??
116 # define GST_IS_PTE_VALID(pVCpu, Pte) (true)
117 # define GST_IS_PDE_VALID(pVCpu, Pd
[all...]
H A DEMHandleRCTmpl.h36 * @param pVCpu Pointer to the VMCPU.
41 int emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc) argument
43 int emR3HmHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
68 rc = emR3RawPrivileged(pVM, pVCpu);
77 AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVCpu)));
81 rc = emR3RawGuestTrap(pVM, pVCpu);
89 rc = emR3RawPatchTrap(pVM, pVCpu, pCtx, rc);
120 | (CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0));
122 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
127 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMI
[all...]
/vbox/src/VBox/VMM/VMMR0/
H A DHMSVMR0.cpp49 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
51 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
53 STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
107 int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
123 #define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
128 #define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
129 || pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
131 pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
257 * @param pVCpu Pointer to the VMCPU.
261 typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCT
472 PVMCPU pVCpu = &pVM->aCpus[i]; local
529 PVMCPU pVCpu = &pVM->aCpus[i]; local
537 PVMCPU pVCpu = &pVM->aCpus[i]; local
607 hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite) argument
[all...]
H A DPGMR0Bth.h23 PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
H A DHMVMXR0.cpp178 # define HMVMX_START_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitDispatch, ed)
179 # define HMVMX_STOP_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitDispatch, ed)
186 #define HMVMX_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
191 #define HMVMX_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
192 || pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
194 pVCpu->hm.s.idEnteredCpu, RTMpCpuId())); \
199 pVCpu->hm.s.u32HMError = pVmxTransient->uExitReason; \
330 * @param pVCpu Pointer to the VMCPU.
337 typedef int FNVMXEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
339 typedef DECLCALLBACK(int) FNVMXEXITHANDLER(PVMCPU pVCpu, PCPUMCT
552 hmR0VmxUpdateErrorRecord(PVM pVM, PVMCPU pVCpu, int rc) argument
702 hmR0VmxReadExitQualificationVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient) argument
888 PVMCPU pVCpu = &pVM->aCpus[i]; local
937 PVMCPU pVCpu = &pVM->aCpus[i]; local
978 PVMCPU pVCpu = &pVM->aCpus[i]; local
1137 hmR0VmxSetMsrPermission(PVMCPU pVCpu, uint32_t uMsr, VMXMSREXITREAD enmRead, VMXMSREXITWRITE enmWrite) argument
1187 hmR0VmxGetMsrPermission(PVMCPU pVCpu, uint32_t uMsr, PVMXMSREXITREAD penmRead, PVMXMSREXITWRITE penmWrite) argument
1229 hmR0VmxSetAutoLoadStoreMsrCount(PVMCPU pVCpu, uint32_t cMsrs) argument
1267 hmR0VmxAddAutoLoadStoreMsr(PVMCPU pVCpu, uint32_t uMsr, uint64_t uGuestMsrValue, bool fUpdateHostMsr) argument
1329 hmR0VmxRemoveAutoLoadStoreMsr(PVMCPU pVCpu, uint32_t uMsr) argument
1388 hmR0VmxIsAutoLoadStoreGuestMsr(PVMCPU pVCpu, uint32_t uMsr) argument
1409 hmR0VmxUpdateAutoLoadStoreHostMsrs(PVMCPU pVCpu) argument
1443 hmR0VmxLazySaveHostMsrs(PVMCPU pVCpu) argument
1469 hmR0VmxIsLazyGuestMsr(PVMCPU pVCpu, uint32_t uMsr) argument
1494 hmR0VmxLazySaveGuestMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
1525 hmR0VmxLazyLoadGuestMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
1569 hmR0VmxLazyRestoreHostMsrs(PVMCPU pVCpu) argument
1594 hmR0VmxCheckVmcsCtls(PVMCPU pVCpu) argument
1636 hmR0VmxCheckHostEferMsr(PVMCPU pVCpu) argument
1658 hmR0VmxCheckAutoLoadStoreMsrs(PVMCPU pVCpu) argument
1723 hmR0VmxFlushEpt(PVMCPU pVCpu, VMXFLUSHEPT enmFlush) argument
1759 hmR0VmxFlushVpid(PVM pVM, PVMCPU pVCpu, VMXFLUSHVPID enmFlush, RTGCPTR GCPtr) argument
1800 VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt) argument
1843 VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys) argument
1869 hmR0VmxFlushTaggedTlbNone(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu) argument
1903 hmR0VmxFlushTaggedTlbBoth(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu) argument
2029 hmR0VmxFlushTaggedTlbEpt(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu) argument
2096 hmR0VmxFlushTaggedTlbVpid(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu) argument
2208 hmR0VmxFlushTaggedTlb(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu) argument
2330 hmR0VmxSetupPinCtls(PVM pVM, PVMCPU pVCpu) argument
2374 hmR0VmxSetupProcCtls(PVM pVM, PVMCPU pVCpu) argument
2565 hmR0VmxSetupMiscCtls(PVM pVM, PVMCPU pVCpu) argument
2635 hmR0VmxInitXcptBitmap(PVM pVM, PVMCPU pVCpu) argument
2662 hmR0VmxInitUpdatedGuestStateMask(PVMCPU pVCpu) argument
2775 PVMCPU pVCpu = &pVM->aCpus[i]; local
2847 hmR0VmxSaveHostControlRegs(PVM pVM, PVMCPU pVCpu) argument
2909 hmR0VmxSaveHostSegmentRegs(PVM pVM, PVMCPU pVCpu) argument
3153 hmR0VmxSaveHostMsrs(PVM pVM, PVMCPU pVCpu) argument
3231 hmR0VmxShouldSwapEferMsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
3291 hmR0VmxLoadGuestEntryCtls(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
3359 hmR0VmxLoadGuestExitCtls(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
3444 hmR0VmxLoadGuestApicState(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
3503 hmR0VmxGetGuestIntrState(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
3549 hmR0VmxLoadGuestIntrState(PVMCPU pVCpu, uint32_t uIntrState) argument
3569 hmR0VmxLoadGuestXcptIntercepts(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
3607 hmR0VmxLoadGuestRip(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
3634 hmR0VmxLoadGuestRsp(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
3660 hmR0VmxLoadGuestRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
3713 hmR0VmxLoadGuestRipRspRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
3738 hmR0VmxLoadSharedCR0(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
3929 hmR0VmxLoadGuestCR3AndCR4(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
4137 hmR0VmxLoadSharedDebugState(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
4300 hmR0VmxValidateSegmentRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) argument
4483 hmR0VmxWriteSegmentReg(PVMCPU pVCpu, uint32_t idxSel, uint32_t idxLimit, uint32_t idxBase, uint32_t idxAccess, PCPUMSELREG pSelReg) argument
4537 hmR0VmxLoadGuestSegmentRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
4758 hmR0VmxLoadGuestMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
4856 hmR0VmxLoadGuestActivityState(PVMCPU pVCpu, PCPUMCTX pCtx) argument
4883 hmR0VmxSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
4943 hmR0VmxRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) argument
4970 hmR0VmxReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx, PVMXTRANSIENT pVmxTransient) argument
5226 VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cParams, uint32_t *paParam) argument
5309 VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu) argument
5388 hmR0VmxInitVmcsReadCache(PVM pVM, PVMCPU pVCpu) argument
5482 VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val) argument
5579 VMXWriteCachedVmcsEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val) argument
5658 hmR0VmxUpdateTscOffsettingAndPreemptTimer(PVM pVM, PVMCPU pVCpu) argument
5751 hmR0VmxSetPendingEvent(PVMCPU pVCpu, uint32_t u32IntInfo, uint32_t cbInstr, uint32_t u32ErrCode, RTGCUINTPTR GCPtrFaultAddress) argument
5773 hmR0VmxSetPendingXcptDF(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
5801 hmR0VmxCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
5979 hmR0VmxSaveGuestCR0(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6022 hmR0VmxSaveGuestCR4(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6055 hmR0VmxSaveGuestRip(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6082 hmR0VmxSaveGuestRsp(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6109 hmR0VmxSaveGuestRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6137 hmR0VmxSaveGuestRipRspRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6157 hmR0VmxSaveGuestIntrState(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6214 hmR0VmxSaveGuestActivityState(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6235 hmR0VmxSaveGuestSysenterMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6275 hmR0VmxSaveGuestLazyMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6317 hmR0VmxSaveGuestAutoLoadStoreMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6363 hmR0VmxSaveGuestControlRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6471 hmR0VmxReadSegmentReg(PVMCPU pVCpu, uint32_t idxSel, uint32_t idxLimit, uint32_t idxBase, uint32_t idxAccess, PCPUMSELREG pSelReg) argument
6556 hmR0VmxSaveGuestSegmentRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6598 hmR0VmxSaveGuestTableRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6664 hmR0VmxSaveGuestDR7(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6693 hmR0VmxSaveGuestApicState(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6715 hmR0VmxSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6782 hmR0VmxSaveGuestRegsForIemExec(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fMemory, bool fNeedRsp) argument
6826 HMR0EnsureCompleteBasicContext(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6858 hmR0VmxCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
6943 hmR0VmxTrpmTrapToPendingEvent(PVMCPU pVCpu) argument
7009 hmR0VmxPendingEventToTrpmTrap(PVMCPU pVCpu) argument
7085 hmR0VmxLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fSaveGuestState) argument
7205 hmR0VmxLeaveSession(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
7252 hmR0VmxLongJmpToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
7275 hmR0VmxExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, int rcExit) argument
7354 hmR0VmxCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser) argument
7426 hmR0VmxSetIntWindowExitVmcs(PVMCPU pVCpu) argument
7446 hmR0VmxClearIntWindowExitVmcs(PVMCPU pVCpu) argument
7462 hmR0VmxSetNmiWindowExitVmcs(PVMCPU pVCpu) argument
7482 hmR0VmxClearNmiWindowExitVmcs(PVMCPU pVCpu) argument
7501 hmR0VmxEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
7584 hmR0VmxSetPendingDebugXcpt(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
7608 hmR0VmxInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fStepping) argument
7722 hmR0VmxSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
7746 hmR0VmxInjectXcptDF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fStepping, uint32_t *puIntrState) argument
7764 hmR0VmxSetPendingXcptDB(PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
7783 hmR0VmxSetPendingXcptOF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint32_t cbInstr) argument
7812 hmR0VmxInjectXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fErrorCodeValid, uint32_t u32ErrorCode, bool fStepping, uint32_t *puIntrState) argument
7834 hmR0VmxSetPendingXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint32_t u32ErrorCode) argument
7855 hmR0VmxSetPendingIntN(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint16_t uVector, uint32_t cbInstr) argument
7924 hmR0VmxInjectEventVmcs(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint64_t u64IntInfo, uint32_t cbInstr, uint32_t u32ErrCode, RTGCUINTREG GCPtrFaultAddress, bool fStepping, uint32_t *puIntrState) argument
8112 hmR0VmxClearEventVmcs(PVMCPU pVCpu) argument
8158 VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu) argument
8203 VMXR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit) argument
8292 hmR0VmxSaveHostState(PVM pVM, PVMCPU pVCpu) argument
8322 VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu) argument
8356 hmR0VmxLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
8441 hmR0VmxLoadSharedState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) argument
8498 hmR0VmxLoadGuestStateOptimal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx) argument
8560 hmR0VmxPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, bool fStepping) argument
8682 hmR0VmxPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
8829 hmR0VmxPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, int rcVMRun) argument
8931 hmR0VmxRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) argument
9013 hmR0VmxRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) argument
9120 VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) argument
9151 hmR0VmxHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, uint32_t rcReason) argument
9248 hmR0VmxHandleExitStep(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, uint32_t uExitReason, uint16_t uCsStart, uint64_t uRipStart) argument
9383 hmR0VmxAdvanceGuestRip(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
9420 hmR0VmxCheckGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) argument
10039 hmR0VmxExitExtInt(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10053 hmR0VmxExitXcptOrNmi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10173 hmR0VmxExitIntWindow(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10189 hmR0VmxExitNmiWindow(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10226 hmR0VmxExitWbinvd(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10237 hmR0VmxExitInvd(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10248 hmR0VmxExitCpuid(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10271 hmR0VmxExitGetsec(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10288 hmR0VmxExitRdtsc(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10314 hmR0VmxExitRdtscp(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10344 hmR0VmxExitRdpmc(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10371 hmR0VmxExitVmcall(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10406 hmR0VmxExitInvlpg(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10433 hmR0VmxExitMonitor(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10458 hmR0VmxExitMwait(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10496 hmR0VmxExitRsm(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10513 hmR0VmxExitSmi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10530 hmR0VmxExitIoSmi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10542 hmR0VmxExitSipi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10559 hmR0VmxExitInitSignal(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10577 hmR0VmxExitTripleFault(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10587 hmR0VmxExitHlt(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10613 hmR0VmxExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10624 hmR0VmxExitPreemptTimer(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10642 hmR0VmxExitXsetbv(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10663 hmR0VmxExitInvpcid(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10677 hmR0VmxExitErrInvalidGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10731 hmR0VmxExitErrMsrLoad(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10743 hmR0VmxExitErrMachineCheck(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10755 hmR0VmxExitErrUndefined(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10768 hmR0VmxExitXdtrAccess(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10784 hmR0VmxExitRdrand(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10800 hmR0VmxExitRdmsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10853 hmR0VmxExitWrmsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10973 hmR0VmxExitPause(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
10990 hmR0VmxExitTprBelowThreshold(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
11016 hmR0VmxExitMovCRx(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
11134 hmR0VmxExitIoInstr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
11361 hmR0VmxExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
11411 hmR0VmxExitMtf(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
11426 hmR0VmxExitApicAccess(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
11505 hmR0VmxExitMovDRx(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
11599 hmR0VmxExitEptMisconfig(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
11656 hmR0VmxExitEptViolation(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
11734 hmR0VmxExitXcptMF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
11764 hmR0VmxExitXcptBP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
11795 hmR0VmxExitXcptDB(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
11879 hmR0VmxExitXcptNM(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
11936 hmR0VmxExitXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
12216 hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
12243 hmR0VmxExitXcptPF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient) argument
[all...]
H A DHMVMXR0.h31 VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu);
32 VMMR0DECL(void) VMXR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit);
41 VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu);
42 VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
43 DECLASM(int) VMXR0StartVM32(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
44 DECLASM(int) VMXR0StartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
48 DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
49 VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
55 VMMR0DECL(int) VMXWriteCachedVmcsEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
57 DECLINLINE(int) VMXReadCachedVmcsEx(PVMCPU pVCpu, uint32_ argument
[all...]
/vbox/src/VBox/VMM/VMMR3/
H A DEM.cpp89 static VBOXSTRICTRC emR3Debug(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc);
90 static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
91 static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
92 int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
170 PVMCPU pVCpu = &pVM->aCpus[i]; local
172 pVCpu->em.s.enmState = (i == 0) ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
173 pVCpu->em.s.enmPrevState = EMSTATE_NONE;
174 pVCpu->em.s.fForceRAW = false;
176 pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
465 PVMCPU pVCpu = &pVM->aCpus[i]; local
479 EMR3ResetCpu(PVMCPU pVCpu) argument
538 PVMCPU pVCpu = &pVM->aCpus[i]; local
593 PVMCPU pVCpu = &pVM->aCpus[i]; local
645 emR3SetExecutionPolicy(PVM pVM, PVMCPU pVCpu, void *pvUser) argument
754 EMR3FatalError(PVMCPU pVCpu, int rc) argument
803 emR3Debug(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc) argument
998 emR3RemStep(PVM pVM, PVMCPU pVCpu) argument
1033 emR3RemExecuteSyncBack(PVM pVM, PVMCPU pVCpu) argument
1061 emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone) argument
1236 emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations) argument
1271 emR3ExecuteIemThenRem(PVM pVM, PVMCPU pVCpu, bool *pfFFDone) argument
1330 emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) argument
1555 emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc) argument
1621 emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc) argument
2070 emR3IsExecutionAllowed(PVM pVM, PVMCPU pVCpu) argument
2112 EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu) argument
2693 PVMCPU pVCpu = VMMGetCpu(pVM); local
2708 PVMCPU pVCpu = VMMGetCpu(pVM); local
[all...]
H A DEMHM.cpp63 DECLINLINE(int) emR3HmExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
64 static int emR3HmExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
65 static int emR3HmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
84 * @param pVCpu Pointer to the cross context CPU structure for
89 VMMR3_INT_DECL(VBOXSTRICTRC) EMR3HmSingleInstruction(PVM pVM, PVMCPU pVCpu, uint32_t fFlags) argument
91 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
104 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
106 VBOXSTRICTRC rcStrict = emR3HmForcedActions(pVM, pVCpu, pCtx);
117 bool fOld = HMSetSingleInstruction(pVCpu, true);
118 VBOXSTRICTRC rcStrict = VMMR3HmRunGC(pVM, pVCpu);
168 emR3HmExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC, const char *pszPrefix) argument
244 emR3HmExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC) argument
260 emR3HmExecuteIOInstruction(PVM pVM, PVMCPU pVCpu) argument
390 emR3HmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) argument
466 emR3HmExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone) argument
[all...]
H A DEMRaw.cpp61 static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
62 DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
63 static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
64 static int emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
65 static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
66 static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
67 static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
83 static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr) argument
87 pRec = (PCLISTAT)RTAvlGCPtrGet(&pVCpu->em.s.pCliStatTree, GCPtrInstr);
101 bool fRc = RTAvlGCPtrInsert(&pVCpu
121 emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu) argument
155 emR3RawStep(PVM pVM, PVMCPU pVCpu) argument
231 emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations) argument
268 emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix) argument
423 emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC) argument
439 emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu) argument
545 emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu) argument
706 emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu) argument
767 emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret) argument
949 emR3RawPrivileged(PVM pVM, PVMCPU pVCpu) argument
1203 emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc) argument
1232 EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu) argument
1251 emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) argument
1372 emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone) argument
[all...]
H A DIEMR3.cpp46 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local
47 pVCpu->iem.s.offVM = -RT_OFFSETOF(VM, aCpus[idCpu].iem.s);
48 pVCpu->iem.s.offVMCpu = -RT_OFFSETOF(VMCPU, iem.s);
49 pVCpu->iem.s.pCtxR3 = CPUMQueryGuestCtxPtr(pVCpu);
50 pVCpu->iem.s.pCtxR0 = VM_R0_ADDR(pVM, pVCpu->iem.s.pCtxR3);
51 pVCpu->iem.s.pCtxRC = VM_RC_ADDR(pVM, pVCpu->iem.s.pCtxR3);
53 STAMR3RegisterF(pVM, &pVCpu
[all...]
H A DVMMTests.cpp45 static void vmmR3TestClearStack(PVMCPU pVCpu) argument
49 memset(pVCpu->vmm.s.pbEMTStackR3 + 64, 0xaa, VMM_STACK_SIZE - 64);
196 PVMCPU pVCpu = &pVM->aCpus[0]; local
204 CPUMSetHyperState(pVCpu, pVM->vmm.s.pfnCallTrampolineRC, pVCpu->vmm.s.pbEMTStackBottomRC, 0, 0);
205 vmmR3TestClearStack(pVCpu);
206 CPUMPushHyper(pVCpu, uVariation);
207 CPUMPushHyper(pVCpu, enmTestcase);
208 CPUMPushHyper(pVCpu, pVM->pVMRC);
209 CPUMPushHyper(pVCpu,
250 PVMCPU pVCpu = &pVM->aCpus[0]; local
339 PVMCPU pVCpu = &pVM->aCpus[0]; local
640 PVMCPU pVCpu = &pVM->aCpus[0]; local
[all...]
H A DPGMShw.h114 PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode);
115 PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta);
116 PGM_SHW_DECL(int, Exit)(PVMCPU pVCpu);
119 PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
120 PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags);
171 * @param pVCpu Pointer to the VMCPU.
174 PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode)
186 PVM pVM = pVCpu->pVMR3;
190 Assert(!pVCpu->pgm.s.pShwPageCR3R3);
194 int rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_ROOT_NESTED, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
[all...]
/vbox/include/VBox/vmm/
H A Dtrpm.h71 VMMDECL(int) TRPMQueryTrap(PVMCPU pVCpu, uint8_t *pu8TrapNo, PTRPMEVENT penmType);
72 VMMDECL(uint8_t) TRPMGetTrapNo(PVMCPU pVCpu); variable
73 VMMDECL(RTGCUINT) TRPMGetErrorCode(PVMCPU pVCpu); variable
74 VMMDECL(RTGCUINTPTR) TRPMGetFaultAddress(PVMCPU pVCpu); variable
75 VMMDECL(uint8_t) TRPMGetInstrLength(PVMCPU pVCpu); variable
76 VMMDECL(int) TRPMResetTrap(PVMCPU pVCpu); variable
77 VMMDECL(int) TRPMAssertTrap(PVMCPU pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType);
78 VMMDECL(int) TRPMAssertXcptPF(PVMCPU pVCpu, RTGCUINTPTR uCR2, RTGCUINT uErrorCode);
79 VMMDECL(void) TRPMSetErrorCode(PVMCPU pVCpu, RTGCUINT uErrorCode);
80 VMMDECL(void) TRPMSetFaultAddress(PVMCPU pVCpu, RTGCUINTPT
82 VMMDECL(bool) TRPMIsSoftwareInterrupt(PVMCPU pVCpu); variable
83 VMMDECL(bool) TRPMHasTrap(PVMCPU pVCpu); variable
85 VMMDECL(void) TRPMSaveTrap(PVMCPU pVCpu); variable
86 VMMDECL(void) TRPMRestoreTrap(PVMCPU pVCpu); variable
99 VMMR3DECL(void) TRPMR3ResetCpu(PVMCPU pVCpu); variable
[all...]
H A Dcpum.h1015 VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR);
1016 VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1017 VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden);
1018 VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu); variable
1019 VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit);
1020 VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu); variable
1021 VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu); variable
1022 VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu); variable
1023 VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu); variable
1024 VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu); variable
1026 VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu); variable
1027 VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu); variable
1028 VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu); variable
1029 VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu); variable
1030 VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu); variable
1031 VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu); variable
1032 VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu); variable
1033 VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu); variable
1034 VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu); variable
1035 VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu); variable
1036 VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu); variable
1037 VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu); variable
1038 VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu); variable
1039 VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu); variable
1040 VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu); variable
1041 VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu); variable
1042 VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu); variable
1043 VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu); variable
1044 VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu); variable
1045 VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu); variable
1046 VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu); variable
1047 VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu); variable
1048 VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu); variable
1052 VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu); variable
1098 VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu); variable
1101 VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu); variable
1108 VMMDECL(bool) CPUMIsGuestIn16BitCode(PVMCPU pVCpu); variable
1109 VMMDECL(bool) CPUMIsGuestIn32BitCode(PVMCPU pVCpu); variable
1110 VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu); variable
1111 VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu); variable
1112 VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu); variable
1113 VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu); variable
1114 VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu); variable
1115 VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu); variable
1116 VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu); variable
1117 VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu); variable
1118 VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu); variable
1119 VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu); variable
1120 VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu); variable
1121 VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu); variable
1232 VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu); variable
1233 VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu); variable
1234 VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu); variable
1235 VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu); variable
1236 VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu); variable
1237 VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu); variable
1245 VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu); variable
1246 VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu); variable
1248 VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu); variable
1250 VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu); variable
1251 VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu); variable
1252 VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu); variable
1253 VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu); variable
1254 VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu); variable
1255 VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu); variable
1256 VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu); variable
1257 VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu); variable
1260 VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu); variable
1261 VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu); variable
1262 VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu); variable
1263 VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu); variable
1264 VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu); variable
1265 VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu); variable
1266 VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu); variable
1268 VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu); variable
1300 VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu); variable
1301 VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu); variable
1302 VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu); variable
1303 VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu); variable
1304 VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu); variable
1306 VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu); variable
1347 VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu); variable
1348 VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu); variable
1349 VMMDECL(bool) CPUMIsGuestDebugStateActivePending(PVMCPU pVCpu); variable
1350 VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu); variable
1351 VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu); variable
1352 VMMDECL(bool) CPUMIsHyperDebugStateActivePending(PVMCPU pVCpu); variable
1353 VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu); variable
1354 VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu); variable
1355 VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu); variable
1356 VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu); variable
1449 VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu); variable
[all...]
H A Dvm.h259 #define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
261 #define VMCPU_SET_STATE(pVCpu, enmNewState) \
262 ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
264 #define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
265 ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
268 # define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
270 VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
273 enmState, enmExpectedState, (pVCpu)->idCpu)); \
276 # define VMCPU_ASSERT_STATE(pVCpu, enmExpectedStat
[all...]
/vbox/src/VBox/VMM/VMMRC/
H A DTRPMRCHandlers.cpp68 uint32_t const fDbgEFlags1 = CPUMRawGetEFlags(pVCpu); \
73 uint32_t const fDbgEFlags2 = CPUMRawGetEFlags(pVCpu); \
153 * @param pVCpu Pointer to the VMCPU.
159 static int trpmGCExitTrap(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTXCORE pRegFrame) argument
161 uint32_t uOldActiveVector = pVCpu->trpm.s.uActiveVector;
167 pVCpu->trpm.s.uActiveVector = UINT32_MAX;
182 TMTimerPollVoid(pVM, pVCpu);
184 VM_FF_IS_PENDING(pVM, VM_FF_TM_VIRTUAL_SYNC), VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TIMER)));
192 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
194 Log2(("VM_FF_INHIBIT_INTERRUPTS at %08RX32 successor %RGv\n", pRegFrame->eip, EMGetInhibitInterruptsPC(pVCpu)));
306 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu); local
360 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu); local
451 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu); local
503 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu); local
533 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu); local
659 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu); local
686 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu); local
792 trpmGCTrap0dHandlerRing0(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC) argument
900 trpmGCTrap0dHandlerRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC) argument
1005 trpmGCTrap0dHandlerRdTsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame) argument
1038 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu); local
1193 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu); local
1256 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu); local
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