/** @file
* CPUM - CPU Monitor(/ Manager).
*/
/*
* Copyright (C) 2006-2015 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* The contents of this file may alternatively be used under the terms
* of the Common Development and Distribution License Version 1.0
* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
* VirtualBox OSE distribution, in which case the provisions of the
* CDDL are applicable instead of those of the GPL.
*
* You may elect to license modified versions of this file under the
* terms and conditions of either the GPL or the CDDL or both.
*/
#ifndef ___VBox_vmm_cpum_h
#define ___VBox_vmm_cpum_h
/** @defgroup grp_cpum The CPU Monitor / Manager API
* @{
*/
/**
* CPUID feature to set or clear.
*/
typedef enum CPUMCPUIDFEATURE
{
/** The APIC feature bit. (Std+Ext) */
/** The PAE feature bit. (Std+Ext) */
/** The NX feature bit. (Ext) */
/** The LONG MODE feature bit. (Ext) */
/** The PAT feature bit. (Std+Ext) */
/** The x2APIC feature bit. (Std) */
/** The RDTSCP feature bit. (Ext) */
/** The Hypervisor Present bit. (Std) */
/** The MWait Extensions bits (Std) */
/** The CR4.OSXSAVE bit CPUID mirroring, only use from CPUMSetGuestCR4. */
/** 32bit hackishness. */
/**
* CPU Vendor.
*/
typedef enum CPUMCPUVENDOR
{
/** 32bit hackishness. */
/**
* X86 and AMD64 CPU microarchitectures and in processor generations.
*
* @remarks The separation here is sometimes a little bit too finely grained,
* and the differences is more like processor generation than micro
* arch. This can be useful, so we'll provide functions for getting at
* more coarse grained info.
*/
typedef enum CPUMMICROARCH
{
kCpumMicroarch_Intel_NB_Gallatin, /**< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). */
kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /**< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin */
/** Predicate macro for catching netburst CPUs. */
((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
/** Predicate macro for catching Core7 CPUs. */
((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
/** Predicate macro for catching AMD Family OFh CPUs (aka K8). */
/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
* decendants). */
((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
/** Predicate macro for catching AMD Family 16H CPUs. */
((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
/**
* CPUID leaf.
*
* @remarks This structure is used by the patch manager and is therefore
* more or less set in stone.
*/
typedef struct CPUMCPUIDLEAF
{
/** The leaf number. */
/** The sub-leaf number. */
/** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
/** The EAX value. */
/** The EBX value. */
/** The ECX value. */
/** The EDX value. */
/** Flags. */
/** Pointer to a CPUID leaf. */
/** Pointer to a const CPUID leaf. */
/** @name CPUMCPUIDLEAF::fFlags
* @{ */
/** Indicates working intel leaf 0xb where the lower 8 ECX bits are not modified
* and EDX containing the extended APIC ID. */
/** The leaf contains an APIC ID that needs changing to that of the current CPU. */
/** The leaf contains an OSXSAVE which needs individual handling on each CPU. */
/** Mask of the valid flags. */
/** @} */
/**
* Method used to deal with unknown CPUID leaves.
* @remarks Used in patch code.
*/
typedef enum CPUMUNKNOWNCPUID
{
/** Invalid zero value. */
/** Use given default values (DefCpuId). */
/** Return the last standard leaf.
* Intel Sandy Bridge has been observed doing this. */
/** Return the last standard leaf, with ecx observed.
* Intel Sandy Bridge has been observed doing this. */
/** The register values are passed thru unmodified. */
/** End of valid value. */
/** Ensure 32-bit type. */
/** Pointer to unknown CPUID leaf method. */
/**
* MSR read functions.
*/
typedef enum CPUMMSRRDFN
{
/** Invalid zero value. */
kCpumMsrRdFn_Invalid = 0,
/** Return the CPUMMSRRANGE::uValue. */
/** Alias to the MSR range starting at the MSR given by
* CPUMMSRRANGE::uValue. Must be used in pair with
* kCpumMsrWrFn_MsrAlias. */
/** Write only register, GP all read attempts. */
/** End of valid MSR read function indexes. */
} CPUMMSRRDFN;
/**
* MSR write functions.
*/
typedef enum CPUMMSRWRFN
{
/** Invalid zero value. */
kCpumMsrWrFn_Invalid = 0,
/** Writes are ignored, the fWrGpMask is observed though. */
/** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
/** Alias to the MSR range starting at the MSR given by
* CPUMMSRRANGE::uValue. Must be used in pair with
* kCpumMsrRdFn_MsrAlias. */
/** End of valid MSR write function indexes. */
} CPUMMSRWRFN;
/**
* MSR range.
*/
typedef struct CPUMMSRRANGE
{
/** The first MSR. [0] */
/** The last MSR. [4] */
/** The read function (CPUMMSRRDFN). [8] */
/** The write function (CPUMMSRWRFN). [10] */
/** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
* UINT16_MAX if not used by the read and write functions. [12] */
/** Reserved for future hacks. [14] */
* When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
* offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
* offset into CPUM. */
/** The bits to ignore when writing. [24] */
/** The bits that will cause a GP(0) when writing. [32]
* This is always checked prior to calling the write function. Using
* UINT64_MAX effectively marks the MSR as read-only. */
/** The register name, if applicable. [40] */
#ifdef VBOX_WITH_STATISTICS
/** The number of reads. */
/** The number of writes. */
/** The number of times ignored bits were written. */
/** The number of GPs generated. */
#endif
} CPUMMSRRANGE;
#ifdef VBOX_WITH_STATISTICS
#else
#endif
/** Pointer to an MSR range. */
/** Pointer to a const MSR range. */
/**
* CPU features and quirks.
* This is mostly exploded CPUID info.
*/
typedef struct CPUMFEATURES
{
/** The CPU vendor (CPUMCPUVENDOR). */
/** The CPU family. */
/** The CPU model. */
/** The CPU stepping. */
/** The microarchitecture. */
#ifndef VBOX_FOR_DTRACE_LIB
#else
#endif
/** The maximum physical address with of the CPU. */
/** Alignment padding. */
/** Max size of the extended state (or FPU state if no XSAVE). */
/** Supports MSRs. */
/** Supports the page size extension (4/2 MB pages). */
/** Supports 36-bit page size extension (4 MB pages can map memory above
* 4GB). */
/** Supports physical address extension (PAE). */
/** Page attribute table (PAT) support (page level cache control). */
/** Supports the FXSAVE and FXRSTOR instructions. */
/** Supports the XSAVE and XRSTOR instructions. */
/** Supports MMX. */
/** Supports AMD extensions to MMX instructions. */
/** Supports SSE. */
/** Supports SSE2. */
/** Supports SSE3. */
/** Supports SSSE3. */
/** Supports SSE4.1. */
/** Supports SSE4.2. */
/** Supports AVX. */
/** Supports AVX2. */
/** Supports AVX512 foundation. */
/** Supports RDTSC. */
/** First generation APIC. */
/** Second generation APIC. */
/** Hypervisor present. */
/** MWAIT & MONITOR instructions supported. */
/** MWAIT Extensions present. */
/** Supports AMD 3DNow instructions. */
/** AMD64: Supports long mode. */
/** AMD64: No-execute page table bit. */
/** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
/** AMD64: Supports RDTSCP. */
/** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */
/** Indicates that FPU instruction and data pointers may leak.
* This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
* is only saved and restored if an exception is pending. */
/** Alignment padding / reserved for future use. */
} CPUMFEATURES;
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** Pointer to a CPU feature structure. */
/** Pointer to a const CPU feature structure. */
/** @name Guest Register Getters.
* @{ */
/** @} */
/** @name Guest Register Setters.
* @{ */
/** @} */
/** @name Misc Guest Predicate Functions.
* @{ */
#ifndef VBOX_WITHOUT_UNNAMED_UNIONS
/**
* Tests if the guest is running in real mode or not.
*
* @returns true if in real mode, otherwise false.
* @param pCtx Current CPU context
*/
{
}
/**
* Tests if the guest is running in real or virtual 8086 mode.
*
* @returns @c true if it is, @c false if not.
* @param pCtx Current CPU context
*/
{
|| pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
}
/**
* Tests if the guest is running in virtual 8086 mode.
*
* @returns @c true if it is, @c false if not.
* @param pCtx Current CPU context
*/
{
}
/**
* Tests if the guest is running in paged protected or not.
*
* @returns true if in paged protected mode, otherwise false.
* @param pVM The VM handle.
*/
{
}
/**
* Tests if the guest is running in long mode or not.
*
* @returns true if in long mode, otherwise false.
* @param pCtx Current CPU context
*/
{
}
/**
* Tests if the guest is running in 64 bits mode or not.
*
* @returns true if in 64 bits protected mode, otherwise false.
* @param pVCpu The current virtual CPU.
* @param pCtx Current CPU context
*/
{
return false;
return CPUMIsGuestIn64BitCodeSlow(pCtx);
}
/**
* Tests if the guest has paging enabled or not.
*
* @returns true if paging is enabled, otherwise false.
* @param pCtx Current CPU context
*/
{
}
/**
* Tests if the guest is running in PAE mode or not.
*
* @returns true if in PAE mode, otherwise false.
* @param pCtx Current CPU context
*/
{
/* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
}
#endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
/** @} */
/** @name Hypervisor Register Getters.
* @{ */
#if 0 /* these are not correct. */
#endif
/** This register is only saved on fatal traps. */
/** This register is only saved on fatal traps. */
/** This register is only saved on fatal traps. */
/** @} */
/** @name Hypervisor Register Setters.
* @{ */
VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX);
/** @} */
/** @name Changed flags.
* These flags are used to keep track of which important register that
* have been changed since last they were reset. The only one allowed
* to clear them is REM!
* @{
*/
| CPUM_CHANGED_CR0 \
| CPUM_CHANGED_CR4 \
| CPUM_CHANGED_CR3 \
| CPUM_CHANGED_TR \
/** @} */
/** @name Typical scalable bus frequency values.
* @{ */
/** Special internal value indicating that we don't know the frequency.
* @internal */
/** @} */
#ifdef IN_RING3
/** @defgroup grp_cpum_r3 The CPUM ring-3 API
* @{
*/
VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf);
VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
# if defined(VBOX_WITH_RAW_MODE) || defined(DOXYGEN_RUNNING)
/** @name APIs for the CPUID raw-mode patch (legacy).
* @{ */
/** @} */
# endif
/** @} */
#endif /* IN_RING3 */
#ifdef IN_RC
/** @defgroup grp_cpum_rc The CPUM Raw-mode Context API
* @{
*/
/**
*
* Assumes a trap stack frame has already been setup on the guest's stack!
* This function does not return!
*
* @param selCS Code selector of handler
* @param pHandler GC virtual address of handler
* @param eflags Callee's EFLAGS
* @param selSS Stack selector for handler
* @param pEsp Stack address for handler
*/
/**
* Call guest V86 code directly.
*
* This function does not return!
*
*/
#ifdef VBOX_WITH_RAW_RING1
#endif
/** @} */
#endif /* IN_RC */
#ifdef IN_RING0
/** @defgroup grp_cpum_r0 The CPUM ring-0 API
* @{
*/
VMMR0_INT_DECL(int) CPUMR0ModuleInit(void);
VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void);
#endif
/** @} */
#endif /* IN_RING0 */
/** @} */
#endif