cpum.h: CPUMDeactivateGuestFPUState was removed earlier today.

IEM,CPUM: Implemented XSETBV and XGETBV.

CPUM,IEM: Expose GuestFeatures and HostFeatures (exploded CPUID), making IEM use it. Early XSAVE/AVX guest support preps.

Remove CPUFeatures and CPUFeaturesExt from CPUM, use HostFeatures instead. Extended HostFeatures.

CPUMCTXCORE elimination.

PATM,CPUM: Redid the CPUID stuff by calling a patch helper function implemented by CPUM. This eliminates needing to expose CPUM guts to in patches that gets saved. Also reimplemented the lookup as a binary search (for the leaf, not sub-leaf).

VMM,REM: CPUID revamp - almost there now.

PATM,CPUM: CPUID patch update.

CPUM: Working on refactoring the guest CPUID handling.

SUPDrv,VMM: Added SUPR0TscDeltaMeasureBySetIndex to SUPDrv (bumping version req) so that VMMR0.cpp can, if necessary, trigger a delta measurement prior to doing RC and HM stuff. Also, made the context hook set the return-to-ring3 force flag if we're rescheduled on a CPU with an TSC delta needing measuring. This is probably code that will almost never get called...

doxygen fixes.

VMM/MSRs: Added status codes for returning to ring-3 to service the MSR access.

VMM/GIM/Minimal: OS X bits.

Recently missed header updates.

VMM: Add MWait Extensions as a CPUM feature to allow configuring it from other VMM components.

VMM/GIM: Hyper-V provider, work-in-progress.

VMM: Expose the MSR read/write function index enums.

VMM: Expose CPUMR3MsrRangesInsert().

VMM/VMMR3: Enable CPUMR3CpuIdInsert().

CPUM,VMM: More work related to bus, cpu and tsc frequency info. Should cover older core and p6 as well as p4 now.

CPUM,DevEFI: Bus vs cpu clock ratio fixes for more recent CPUs. Older CPUs (<=Core2) still need some more work.

CPUM: Added AMD Athlon64 3200+ (130nm) and Pentium4 (mod 4, w/ 64-bit).

build fix

MSR rewrite: initial hacking - half disabled.

VMM: Use EFER.LMA in PAE-paging mode check rather than EFER.LME.

VMM: Get rid of residual VBOX_WITH_OLD_VTX_CODE defines.

VMM: FPU cleanup.

VMM/CPUM: Guest and Hyper-debug state pending 32->64 switcher case helpers.

VMM: CPUMR0Init -> CPUMR0InitVM renamed.

VMM: X2APIC + NMI. Only tested on AMD64.

CPUMRecalcHyperDRx: Host single stepping in HM-mode fix.

VMM: I/O breakpoints.

VMM: Debug register handling redo. (only partly tested on AMD-V so far.)

Made dSYM-bundle loading work as well as line numbers in the stack traces (when possible).

- *: Where possible, drop the #ifdef VBOX_WITH_RAW_RING1 when EMIsRawRing1Enabled is used. - SELM: Don't shadow TSS.esp1/ss1 unless ring-1 compression is enabled (also fixed a log statement there). - SELM: selmGuestToShadowDesc should not push ring-1 selectors into ring-2 unless EMIsRawRing1Enabled() holds true. - REM: Don't set CPU_INTERRUPT_EXTERNAL_EXIT in helper_ltr() for now.

VMM: HM bits.

Ring-1 compression patches, courtesy of trivirt AG: - main: diff to remove the hwvirt requirement for QNX - rem: diff for dealing with raw ring 0/1 selectors and general changes to allowed guest execution states - vmm: changes for using the guest's TSS selector index as our hypervisor TSS selector (makes str safe) (VBOX_WITH_SAFE_STR ) - vmm: changes for dealing with guest ring 1 code (VBOX_WITH_RAW_RING1) - vmm: change to emulate smsw in RC/R0 (QNX uses this old style instruction a lot so going to qemu for emulation is very expensive) - vmm: change (hack) to kick out patm virtual handlers in case they conflict with guest GDT/TSS write monitors; we should allow multiple handlers per page, but that change would be rather invasive

VMM/VMMR0: HM bits.

VMM/VMMR0: HM bits.

CPUM: helper function.

VMMR0/CPUMR0: atomic update of aGuestCpuId*(); fix return type of CPUMR3LogCpuIds()

VMM: don't pass certain CPUID features to the guest if the feature is not supported on some host cores

VMM/VMMR0: bits.

VMM: APIC refactor, cache APIC base MSR during init phase.

VMM: Fixed some selector arithmetic, introducing a new constand and renaming and old one to make things clearer. Also added CPUMGetGuestLdtrEx and make some (but not all) of SELM use this instead of shadow GDT.

Eliminating CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID and CPUMAreHiddenSelRegsValid. Addressing some LDTR and TR things (saved stated, transition to REM).

VMM: Futher work on dealing with hidden segment register, esp. when going stale.

SELM,DIS,CPUM,EM: Hidden selector register cleanups.

CPUMIsGuestIn64BitCode/CPUMIsGuestIn64BitCodeEx changes together with some early lazily loading of hidden selectors (raw-mode).

A few missed copyright year updates.

VMM: RDTSCP support on Intel. Segregated some common CPU features from the AMD superset into Extended features as they're now available on Intel too.

VMM: Switcher and TRPM fixes wrt hypervisor traps and tstVMM.

VMM: Avoid stale selector issues in RC so there will be no need to try fix them by recursive trapping (this was broken for GS since forever anyways).

CPUMRaw[SG]etEFlags: Drop pCtxCore.

CPUMGetGuestCPL: Drop the context core pointer and use the Guest state in CPUMCPU via pVCpu.

TRPM: Save state directly to the CPUMCPU context member instead of putting on the stack. this avoid copying the state around before returning to host context to service an IRQ, or before using IEM.

CPUM: Combined the visible and hidden selector register data into one structure. Preparing for lazily resolving+caching of hidden registers in raw-mode.

CPUM: Fixed saved state bustage. Got two padding equally wrong and shifted the registers inbetween...

Moved VBox/x86.h/mac to iprt/x86.h/mac.

CPUM: Option to set Hypervisor Present bit.

CPUM: CPUMSetGuestGDTR and CPUMSetGuestIDTR should take 64-bit base value.

build fix

CPUMIsGuestInRealOrV86Mode and CPUMIsGuestInRealOrV86ModeEx.

Two cases where CPUM_CHANGED_GLOBAL_TLB_FLUSH was missing, causing stale TLB entries and mayhem.

fix OSE