Lines Matching refs:pVCpu
60 * @param pVCpu Pointer to the VMCPU.
63 static void hmQueueInvlPage(PVMCPU pVCpu, RTGCPTR GCVirt)
66 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
69 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
73 if (iPage == RT_ELEMENTS(pVCpu->hm.s.TlbShootdown.aPages))
74 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
76 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
85 * @param pVCpu Pointer to the VMCPU.
88 VMM_INT_DECL(int) HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
90 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushPageManual);
92 PVM pVM = pVCpu->CTX_SUFF(pVM);
94 return VMXR0InvalidatePage(pVM, pVCpu, GCVirt);
97 return SVMR0InvalidatePage(pVM, pVCpu, GCVirt);
100 hmQueueInvlPage(pVCpu, GCVirt);
110 * @param pVCpu Pointer to the VMCPU.
112 VMM_INT_DECL(int) HMFlushTLB(PVMCPU pVCpu)
116 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
117 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbManual);
136 static void hmR0PokeCpu(PVMCPU pVCpu, RTCPUID idHostCpu)
138 uint32_t cWorldSwitchExits = ASMAtomicUoReadU32(&pVCpu->hm.s.cWorldSwitchExits);
140 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatPoke, x);
142 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPoke, x);
148 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPoke, z);
151 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPoke, z);
156 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPoke, z);
158 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPokeFailed, z);
163 * that's something not suitable for stack... So, pVCpu->hm.s.something
166 while ( ASMAtomicUoReadBool(&pVCpu->hm.s.fCheckedTLBFlush)
167 && cWorldSwitchExits == ASMAtomicUoReadU32(&pVCpu->hm.s.cWorldSwitchExits))
171 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPoke, z);
173 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPokeFailed, z);
183 * @param pVCpu The handle of the virtual CPU to poke.
187 static void hmPokeCpuForTlbFlush(PVMCPU pVCpu, bool fAccountFlushStat)
189 if (ASMAtomicUoReadBool(&pVCpu->hm.s.fCheckedTLBFlush))
192 STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdownFlush);
194 STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
196 RTCPUID idHostCpu = pVCpu->hm.s.idEnteredCpu;
198 hmR0PokeCpu(pVCpu, idHostCpu);
200 VMR3NotifyCpuFFU(pVCpu->pUVCpu, VMNOTIFYFF_FLAGS_POKE);
204 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushPageManual);
222 PVMCPU pVCpu = &pVM->aCpus[idCpu];
226 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
229 if (pVCpu->idCpu == idCurCpu)
230 HMInvalidatePage(pVCpu, GCPtr);
233 hmQueueInvlPage(pVCpu, GCPtr);
234 hmPokeCpuForTlbFlush(pVCpu, false /* fAccountFlushStat */);
259 PVMCPU pVCpu = &pVM->aCpus[idCpu];
263 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
265 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
267 hmPokeCpuForTlbFlush(pVCpu, true /* fAccountFlushStat */);
381 PVMCPU pVCpu = &pVM->aCpus[idCpu];
387 VMXR0InvalidatePhysPage(pVM, pVCpu, GCPhys);
391 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
392 hmPokeCpuForTlbFlush(pVCpu, true /*fAccountFlushStat*/);
417 PVMCPU pVCpu = VMMGetCpu(pVM);
418 return !!pVCpu->hm.s.Event.fPending;
426 * @param pVCpu Pointer to the VMCPU.
428 VMM_INT_DECL(PX86PDPE) HMGetPaePdpes(PVMCPU pVCpu)
430 return &pVCpu->hm.s.aPdpes[0];
496 * @param pVCpu Pointer to the cross context CPU structure of
500 VMM_INT_DECL(bool) HMSetSingleInstruction(PVMCPU pVCpu, bool fEnable)
502 VMCPU_ASSERT_EMT(pVCpu);
503 bool fOld = pVCpu->hm.s.fSingleInstruction;
504 pVCpu->hm.s.fSingleInstruction = fEnable;
512 * @param pVCpu Pointer to the VMCPU.
514 VMM_INT_DECL(void) HMHypercallsEnable(PVMCPU pVCpu)
516 pVCpu->hm.s.fHypercallsEnabled = true;
523 * @param pVCpu Pointer to the VMCPU.
525 VMM_INT_DECL(void) HMHypercallsDisable(PVMCPU pVCpu)
527 pVCpu->hm.s.fHypercallsEnabled = false;
534 * @param pVCpu Pointer to the VMCPU.
536 VMM_INT_DECL(void) HMTrapXcptUDForGIMEnable(PVMCPU pVCpu)
538 pVCpu->hm.s.fGIMTrapXcptUD = true;
539 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
546 * @param pVCpu Pointer to the VMCPU.
548 VMM_INT_DECL(void) HMTrapXcptUDForGIMDisable(PVMCPU pVCpu)
550 pVCpu->hm.s.fGIMTrapXcptUD = false;
551 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);