Lines Matching refs:pVCpu

36  * @param   pVCpu   Pointer to the VMCPU.
41 int emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
43 int emR3HmHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
68 rc = emR3RawPrivileged(pVM, pVCpu);
77 AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVCpu)));
81 rc = emR3RawGuestTrap(pVM, pVCpu);
89 rc = emR3RawPatchTrap(pVM, pVCpu, pCtx, rc);
120 | (CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0));
122 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
127 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
138 AssertMsg(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL),
165 rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
184 Assert(TRPMHasTrap(pVCpu));
187 if (TRPMHasTrap(pVCpu))
190 uint8_t u8Interrupt = TRPMGetTrapNo(pVCpu);
205 rc = emR3RawRingSwitch(pVM, pVCpu);
214 rc = emR3ExecuteIOInstruction(pVM, pVCpu);
223 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
231 rc = emR3ExecuteInstruction(pVM, pVCpu, "MSR");
243 rc = HMR3PatchTprInstr(pVM, pVCpu, pCtx);
252 rc = emR3ExecuteInstruction(pVM, pVCpu, "LDT FAULT: ");
255 rc = emR3ExecuteInstruction(pVM, pVCpu, "GDT FAULT: ");
258 rc = emR3ExecuteInstruction(pVM, pVCpu, "IDT FAULT: ");
261 rc = emR3ExecuteInstruction(pVM, pVCpu, "TSS FAULT: ");
264 rc = emR3ExecuteInstruction(pVM, pVCpu, "PD FAULT: ");
268 rc = emR3RawPrivileged(pVM, pVCpu);
274 rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
282 rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ");
287 rc = VBOXSTRICTRC_VAL(IEMInjectTrpmEvent(pVCpu));
290 rc = emR3ExecuteInstruction(pVM, pVCpu, "EVENT: ");
293 rc = emR3ExecuteInstruction(pVM, pVCpu, "EVENT: ");
317 AssertMsg(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_SELM_SYNC_TSS),