Lines Matching refs:pVCpu
68 uint32_t const fDbgEFlags1 = CPUMRawGetEFlags(pVCpu); \
73 uint32_t const fDbgEFlags2 = CPUMRawGetEFlags(pVCpu); \
153 * @param pVCpu Pointer to the VMCPU.
159 static int trpmGCExitTrap(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTXCORE pRegFrame)
161 uint32_t uOldActiveVector = pVCpu->trpm.s.uActiveVector;
167 pVCpu->trpm.s.uActiveVector = UINT32_MAX;
182 TMTimerPollVoid(pVM, pVCpu);
184 VM_FF_IS_PENDING(pVM, VM_FF_TM_VIRTUAL_SYNC), VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TIMER)));
192 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
194 Log2(("VM_FF_INHIBIT_INTERRUPTS at %08RX32 successor %RGv\n", pRegFrame->eip, EMGetInhibitInterruptsPC(pVCpu)));
195 if (pRegFrame->eip != EMGetInhibitInterruptsPC(pVCpu))
202 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
212 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_TO_R3 | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC
224 else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TO_R3 | VMCPU_FF_PDM_CRITSECT))
226 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
230 else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TIMER))
241 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
244 else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_SELM_SYNC_TSS))
247 else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)
248 && !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
253 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
256 rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_HARDWARE_INT, uOldActiveVector);
265 TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
273 else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
276 PGMRZDynMapReleaseAutoSet(pVCpu);
277 PGMRZDynMapStartAutoSet(pVCpu);
278 rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
286 PGMRZDynMapReleaseAutoSet(pVCpu);
306 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
307 LogFlow(("TRPMGC01: cs:eip=%04x:%08x uDr6=%RTreg EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, uDr6, CPUMRawGetEFlags(pVCpu)));
316 ASMGetDR7(), CPUMGetHyperDR7(pVCpu), uDr6),
323 PGMRZDynMapStartAutoSet(pVCpu);
324 int rc = DBGFRZTrap01Handler(pVM, pVCpu, pRegFrame, uDr6, false /*fAltStepping*/);
327 CPUMSetGuestDR6(pVCpu, (CPUMGetGuestDR6(pVCpu) & ~X86_DR6_B_MASK) | uDr6);
328 if (CPUMGetGuestDR7(pVCpu) & X86_DR7_GD)
329 CPUMSetGuestDR7(pVCpu, CPUMGetGuestDR7(pVCpu) & ~X86_DR7_GD);
334 rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
335 Log6(("TRPMGC01: %Rrc (%04x:%08x %RTreg %EFlag=%#x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, uDr6, CPUMRawGetEFlags(pVCpu)));
360 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
370 ASMGetDR7(), CPUMGetHyperDR7(pVCpu), uDr6),
377 int rc = DBGFRZTrap01Handler(pVM, pVCpu, pRegFrame, uDr6, false /*fAltStepping*/);
451 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
453 LogFlow(("TRPMGC03: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
455 PGMRZDynMapStartAutoSet(pVCpu);
470 rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
471 Log6(("TRPMGC03: %Rrc (%04x:%08x EFL=%x) (PATM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
476 rc = DBGFRZTrap03Handler(pVM, pVCpu, pRegFrame);
479 rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
480 Log6(("TRPMGC03: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
503 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
504 LogFlow(("TRPMGCHyper03: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
510 int rc = DBGFRZTrap03Handler(pVM, pVCpu, pRegFrame);
513 Log6(("TRPMGCHyper03: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
533 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
535 LogFlow(("TRPMGC06: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, pRegFrame->eflags.u32, CPUMRawGetEFlags(pVCpu)));
537 PGMRZDynMapStartAutoSet(pVCpu);
539 if (CPUMGetGuestCPL(pVCpu) <= (EMIsRawRing1Enabled(pVM) ? 1U : 0U))
545 rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
550 rc = trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_GUEST_TRAP, pRegFrame);
551 Log6(("TRPMGC06: %Rrc (%04x:%08x EFL=%x) (SELM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
558 rc = EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
561 rc = trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
562 Log6(("TRPMGC06: %Rrc (%04x:%08x EFL=%x) (EM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
584 rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
585 Log6(("TRPMGC06: %Rrc (%04x:%08x EFL=%x) (PATM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
598 rc = TRPMForwardTrap(pVCpu, pRegFrame, X86_XCPT_UD, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_TRAP, X86_XCPT_UD);
610 rc = EMInterpretInstructionDisasState(pVCpu, &Cpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR);
612 else if (GIMShouldTrapXcptUD(pVCpu))
615 rc = GIMXcptUD(pVCpu, CPUMCTX_FROM_CORE(pRegFrame), &Cpu);
632 rc = TRPMForwardTrap(pVCpu, pRegFrame, X86_XCPT_UD, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_TRAP, X86_XCPT_UD);
636 rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
637 Log6(("TRPMGC06: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
659 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
660 LogFlow(("TRPMGC07: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
662 PGMRZDynMapStartAutoSet(pVCpu);
664 int rc = CPUMHandleLazyFPU(pVCpu);
665 rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
666 Log6(("TRPMGC07: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
686 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
687 LogFlow(("TRPMGC0b: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
689 PGMRZDynMapStartAutoSet(pVCpu);
697 if ( SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
762 Log6(("TRPMGC0b: %Rrc (%04x:%08x EFL=%x) (CG)\n", VINF_EM_RAW_RING_SWITCH, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
764 PGMRZDynMapReleaseAutoSet(pVCpu);
772 Log6(("TRPMGC0b: %Rrc (%04x:%08x EFL=%x)\n", VINF_EM_RAW_GUEST_TRAP, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
773 PGMRZDynMapReleaseAutoSet(pVCpu);
787 * @param pVCpu Pointer to the VMCPU.
792 static int trpmGCTrap0dHandlerRing0(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC)
819 return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
822 rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->Param1.uValue, pCpu->cbInstr, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
826 return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
829 pVCpu->trpm.s.uActiveVector = (pVCpu->trpm.s.uActiveErrorCode & X86_TRAP_ERR_SEL_MASK) >> X86_TRAP_ERR_SEL_SHIFT;
830 pVCpu->trpm.s.enmActiveType = TRPM_SOFTWARE_INT;
831 return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH_INT, pRegFrame);
839 return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
849 return trpmGCExitTrap(pVM, pVCpu, VINF_EM_HALT, pRegFrame);
874 rc = EMInterpretInstructionDisasState(pVCpu, pCpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR);
878 return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
883 return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EXCEPTION_PRIVILEGED, pRegFrame);
895 * @param pVCpu Pointer to the VMCPU.
900 static int trpmGCTrap0dHandlerRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC)
922 rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->Param1.uValue, pCpu->cbInstr, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
926 return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
929 pVCpu->trpm.s.uActiveVector = (pVCpu->trpm.s.uActiveErrorCode & X86_TRAP_ERR_SEL_MASK) >> X86_TRAP_ERR_SEL_SHIFT;
930 pVCpu->trpm.s.enmActiveType = TRPM_SOFTWARE_INT;
932 return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH_INT, pRegFrame);
945 return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
951 pVCpu->trpm.s.uActiveVector = UINT32_MAX;
953 return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_RING_SWITCH, pRegFrame);
961 rc = EMInterpretInstructionDisasState(pVCpu, pCpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR);
965 return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
974 uint32_t efl = CPUMRawGetEFlags(pVCpu);
975 uint32_t cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
980 return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RESCHEDULE_REM, pRegFrame);
991 return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_GUEST_TRAP, pRegFrame);
1001 * @param pVCpu Pointer to the VMCPU.
1005 DECLINLINE(int) trpmGCTrap0dHandlerRdTsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1010 if (CPUMGetGuestCR4(pVCpu) & X86_CR4_TSD)
1013 return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame); /* will trap (optimize later). */
1016 uint64_t uTicks = TMCpuTickGet(pVCpu);
1021 return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
1038 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1039 LogFlow(("trpmGCTrap0dHandler: cs:eip=%RTsel:%08RX32 uErr=%RGv EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, pTrpmCpu->uActiveErrorCode, CPUMRawGetEFlags(pVCpu)));
1047 int rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
1055 return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
1063 rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, &Cpu, &cbOp);
1069 return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
1081 return trpmGCTrap0dHandlerRdTsc(pVM, pVCpu, pRegFrame);
1086 if ( pVCpu->trpm.s.uActiveErrorCode == 0
1089 VBOXSTRICTRC rcStrict = IOMRCIOPortHandler(pVM, pVCpu, pRegFrame, &Cpu);
1097 uint32_t const uDr7 = CPUMGetGuestDR7(pVCpu);
1100 && (CPUMGetGuestCR4(pVCpu) & X86_CR4_DE))
1120 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, CPUMCTX_FROM_CORE(pRegFrame), uPort, cbValue);
1124 TRPMResetTrap(pVCpu);
1125 TRPMAssertTrap(pVCpu, X86_XCPT_DE, TRPM_TRAP);
1138 return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1146 return trpmGCTrap0dHandlerRing0(pVM, pVCpu, pRegFrame, &Cpu, PC);
1152 return trpmGCTrap0dHandlerRing3(pVM, pVCpu, pRegFrame, &Cpu, PC);
1163 eflags.u32 = CPUMRawGetEFlags(pVCpu); /* Get the correct value. */
1169 rc = TRPMForwardTrap(pVCpu, pRegFrame, 0xD, 0, TRPM_TRAP_HAS_ERRORCODE, TRPM_TRAP, 0xd);
1172 return trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1175 return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
1193 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1194 LogFlow(("TRPMGC0d: %04x:%08x err=%x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode, CPUMRawGetEFlags(pVCpu)));
1197 PGMRZDynMapStartAutoSet(pVCpu);
1208 Assert(TRPMHasTrap(pVCpu));
1233 Log6(("TRPMGC0d: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));
1256 PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
1257 LogFlow(("TRPMGC0e: %04x:%08x err=%x cr2=%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode, (uint32_t)pVCpu->trpm.s.uActiveCR2, CPUMRawGetEFlags(pVCpu)));
1263 PGMRZDynMapStartAutoSet(pVCpu);
1264 int rc = PGMTrap0eHandler(pVCpu, pVCpu->trpm.s.uActiveErrorCode, pRegFrame, (RTGCPTR)pVCpu->trpm.s.uActiveCR2);
1280 PGMRZDynMapReleaseAutoSet(pVCpu);
1285 rc = TRPMForwardTrap(pVCpu, pRegFrame, 0xE, 0, TRPM_TRAP_HAS_ERRORCODE, TRPM_TRAP, 0xe);
1290 Assert(TRPMHasTrap(pVCpu));
1310 rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
1311 Log6(("TRPMGC0e: %Rrc (%04x:%08x EFL=%x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu)));