63 DECLINLINE(int) emR3HmExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
64 static int      emR3HmExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
65 static int      emR3HmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
84  * @param   pVCpu               Pointer to the cross context CPU structure for
89 VMMR3_INT_DECL(VBOXSTRICTRC) EMR3HmSingleInstruction(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
91     PCPUMCTX pCtx = pVCpu->em.s.pCtx;
104             || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
106             VBOXSTRICTRC rcStrict = emR3HmForcedActions(pVM, pVCpu, pCtx);
117         bool fOld = HMSetSingleInstruction(pVCpu, true);
118         VBOXSTRICTRC rcStrict = VMMR3HmRunGC(pVM, pVCpu);
119         HMSetSingleInstruction(pVCpu, fOld);
126         VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
128             || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
130             rcStrict = emR3HighPriorityPostForcedActions(pVM, pVCpu, VBOXSTRICTRC_TODO(rcStrict));
136             rcStrict = emR3HmHandleRC(pVM, pVCpu, pCtx, VBOXSTRICTRC_TODO(rcStrict));
162  * @param   pVCpu       Pointer to the VMCPU.
168 static int emR3HmExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC, const char *pszPrefix)
170 static int emR3HmExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC)
174     PCPUMCTX pCtx = pVCpu->em.s.pCtx;
187         DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, pszPrefix);
196     STAM_PROFILE_START(&pVCpu->em.s.StatIEMEmu, a);
197     rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu));
198     STAM_PROFILE_STOP(&pVCpu->em.s.StatIEMEmu, a);
205         STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, b);
213         if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
214             CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
215         pVM->em.s.idLastRemCpu = pVCpu->idCpu;
217         rc = REMR3EmulateInstruction(pVM, pVCpu);
219         STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, b);
226     if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HM)
227         HMR3NotifyEmulated(pVCpu);
239  * @param   pVCpu       Pointer to the VMCPU.
244 DECLINLINE(int) emR3HmExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
247     return emR3HmExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
249     return emR3HmExecuteInstructionWorker(pVM, pVCpu, rcGC);
258  * @param   pVCpu       Pointer to the VMCPU.
260 static int emR3HmExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
262     PCPUMCTX pCtx = pVCpu->em.s.pCtx;
264     STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
269     VBOXSTRICTRC rcStrict = HMR3RestartPendingIOInstr(pVM, pVCpu, pCtx);
272         STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoRestarted);
273         STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
283     rcStrict = IEMExecOne(pVCpu);
285     STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoIem);
286     STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
294     int rc2 = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
305                     STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
306                     rcStrict = IOMInterpretIN(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
312                     STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
313                     rcStrict = IOMInterpretOUT(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
325                     STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
326                     rcStrict = IOMInterpretINS(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
333                     STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
334                     rcStrict = IOMInterpretOUTS(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
347             STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
355             Assert(TRPMHasTrap(pVCpu));
356             STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
364             STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
371     STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
372     int rc3 = emR3HmExecuteInstruction(pVM, pVCpu, "IO: ");
387  * @param   pVCpu       Pointer to the VMCPU.
390 static int emR3HmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
395     if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
397         Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
398         int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
403         Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
408         rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
410             rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
418             rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
424         Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
462  * @param   pVCpu       Pointer to the VMCPU.
466 int emR3HmExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
469     PCPUMCTX pCtx = pVCpu->em.s.pCtx;
471     LogFlow(("emR3HmExecute%d: (cs:eip=%04x:%RGv)\n", pVCpu->idCpu, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
474     STAM_COUNTER_INC(&pVCpu->em.s.StatHmExecuteEntry);
477     HMR3NotifyScheduled(pVCpu);
485         STAM_PROFILE_ADV_START(&pVCpu->em.s.StatHmEntry, a);
498         Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
501             ||  VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
503             rc = emR3HmForcedActions(pVM, pVCpu, pCtx);
512         if (TRPMHasTrap(pVCpu))
513             Log(("CPU%d: Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", pVCpu->idCpu, TRPMGetTrapNo(pVCpu), pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
515         uint32_t cpl = CPUMGetGuestCPL(pVCpu);
529                 Log(("HWV86-CPU%d: %08X IF=%d\n", pVCpu->idCpu, pCtx->eip, pCtx->eflags.Bits.u1IF));
531                 Log(("HWR%d-CPU%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
533                 Log(("HWR%d-CPU%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs.Sel,          pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
540         STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatHmEntry, a);
542         if (RT_LIKELY(emR3IsExecutionAllowed(pVM, pVCpu)))
544             STAM_PROFILE_START(&pVCpu->em.s.StatHmExec, x);
545             rc = VMMR3HmRunGC(pVM, pVCpu);
546             STAM_PROFILE_STOP(&pVCpu->em.s.StatHmExec, x);
551             STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
553             STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
561         VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
563             ||  VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
564             rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
572         rc = emR3HmHandleRC(pVM, pVCpu, pCtx, rc);
580         TMTimerPollVoid(pVM, pVCpu);
583             ||  VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_ALL_MASK))
585             rc = emR3ForcedActions(pVM, pVCpu, rc);
586             VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);

Indexes created Tue Jul 24 14:28:13 CEST 2018