Lines Matching refs:pVCpu
61 PVMCPU pVCpu;
72 DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
73 DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
75 static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
76 static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
400 * @param pVCpu Pointer to the VMCPU.
405 VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
407 PVM pVM = pVCpu->CTX_SUFF(pVM);
409 Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
410 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, a);
411 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
423 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentWrite);
425 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentRead);
428 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSWrite);
430 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSReserved);
432 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNXE);
434 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSRead);
441 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentWrite);
443 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentRead);
446 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVWrite);
448 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSNXE);
450 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVReserved);
458 int rc = PGM_BTH_PFN(Trap0eHandler, pVCpu)(pVCpu, uErr, pRegFrame, pvFault, &fLockTaken);
488 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPF); });
489 STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
490 pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Misc; });
491 STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
506 * @param pVCpu Pointer to the VMCPU.
509 VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
511 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
512 int rc = PGM_BTH_PFN(PrefetchPage, pVCpu)(pVCpu, GCPtrPage);
513 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
549 * @param pVCpu Pointer to the VMCPU.
555 VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
567 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
591 return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
602 * @param pVCpu Pointer to the VMCPU.
607 VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
609 PVM pVM = pVCpu->CTX_SUFF(pVM);
617 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
645 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
655 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVCpu)(pVCpu, Addr, fPageGst, uErr);
669 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
692 rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
711 * @param pVCpu Pointer to the VMCPU.
720 VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
722 PVM pVM = pVCpu->CTX_SUFF(pVM);
741 && PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
744 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
749 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
761 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
763 rc = PGM_BTH_PFN(InvalidatePage, pVCpu)(pVCpu, GCPtrPage);
765 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
772 && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
774 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
805 * @param pVCpu Pointer to the VMCPU.
809 VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
812 VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, pRegFrame, pvFault);
825 * @param pVCpu Pointer to the VMCPU.
832 VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
834 pgmLock(pVCpu->CTX_SUFF(pVM));
835 int rc = PGM_SHW_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pHCPhys);
836 pgmUnlock(pVCpu->CTX_SUFF(pVM));
847 * @param pVCpu Pointer to the VMCPU.
855 DECLINLINE(int) pdmShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
862 PVM pVM = pVCpu->CTX_SUFF(pVM);
864 int rc = PGM_SHW_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, PAGE_SIZE, fFlags, fMask, fOpFlags);
875 * @param pVCpu Pointer to the VMCPU.
879 VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
881 return pdmShwModifyPage(pVCpu, GCPtr, 0, ~(uint64_t)X86_PTE_RW, fOpFlags);
894 * @param pVCpu Pointer to the VMCPU.
899 VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
901 return pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)0, fOpFlags);
910 * @param pVCpu Pointer to the VMCPU.
914 VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
916 return pdmShwModifyPage(pVCpu, GCPtr, 0, 0, fOpFlags);
927 * @param pVCpu Pointer to the VMCPU.
935 int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags)
937 int rc = pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)X86_PTE_US, fOpFlags);
941 switch (pVCpu->pgm.s.enmShadowMode)
945 PX86PDE pPde = pgmShwGet32BitPDEPtr(pVCpu, GCPtr);
955 PX86PDEPAE pPde = pgmShwGetPaePDEPtr(pVCpu, GCPtr);
974 * @param pVCpu Pointer to the VMCPU.
979 int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
982 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
984 PVM pVM = pVCpu->CTX_SUFF(pVM);
998 if (pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu))
1006 if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
1027 GCPdPt = CPUMGetGuestCR3(pVCpu);
1033 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1034 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, false /*fLockPage*/,
1049 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdpe);
1059 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1068 * @param pVCpu The current CPU.
1072 DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
1075 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1076 PVM pVM = pVCpu->CTX_SUFF(pVM);
1107 * @param pVCpu Pointer to the VMCPU.
1113 static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1115 PVM pVM = pVCpu->CTX_SUFF(pVM);
1118 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1119 bool fNestedPagingOrNoGstPaging = pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu);
1132 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1147 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1148 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /*fLockPage*/,
1160 pPml4e->u |= pShwPage->Core.Key | (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask);
1163 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1186 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1199 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask);
1201 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1210 * @param pVCpu Pointer to the VMCPU.
1215 DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1218 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1220 PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1231 PVM pVM = pVCpu->CTX_SUFF(pVM);
1237 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1244 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1255 * @param pVCpu Pointer to the VMCPU.
1260 static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1262 PVM pVM = pVCpu->CTX_SUFF(pVM);
1273 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1284 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1285 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /*fLockPage*/,
1303 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1314 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_EPT_PD_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1332 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1344 * @param pVCpu The current CPU.
1350 int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode)
1352 PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1360 rc = PGM_BTH_NAME_32BIT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1368 rc = PGM_BTH_NAME_PAE_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1376 rc = PGM_BTH_NAME_AMD64_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1383 rc = PGM_BTH_NAME_EPT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1404 * @param pVCpu The current CPU.
1410 VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1412 VMCPU_ASSERT_EMT(pVCpu);
1413 return PGM_GST_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pGCPhys);
1429 * @param pVCpu The current CPU.
1434 int pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk)
1436 VMCPU_ASSERT_EMT(pVCpu);
1437 switch (pVCpu->pgm.s.enmGuestMode)
1441 return PGM_GST_NAME_32BIT(Walk)(pVCpu, GCPtr, &pWalk->u.Legacy);
1446 return PGM_GST_NAME_PAE(Walk)(pVCpu, GCPtr, &pWalk->u.Pae);
1452 return PGM_GST_NAME_AMD64(Walk)(pVCpu, GCPtr, &pWalk->u.Amd64);
1479 * @param pVCpu Pointer to the VMCPU.
1482 VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
1484 VMCPU_ASSERT_EMT(pVCpu);
1485 int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
1494 * @param pVCpu Pointer to the VMCPU.
1499 VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1501 VMCPU_ASSERT_EMT(pVCpu);
1502 return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
1512 * @param pVCpu Pointer to the VMCPU.
1519 VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1521 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
1522 VMCPU_ASSERT_EMT(pVCpu);
1542 int rc = PGM_GST_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
1544 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
1555 * @param pVCpu The current CPU.
1559 int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd)
1561 PVM pVM = pVCpu->CTX_SUFF(pVM);
1564 Assert(!pVCpu->pgm.s.CTX_SUFF(pGst32BitPd));
1566 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAGE_MASK;
1575 pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1577 pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1598 * @param pVCpu The current CPU.
1602 int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt)
1604 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt));
1605 PVM pVM = pVCpu->CTX_SUFF(pVM);
1608 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAE_PAGE_MASK;
1617 pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1619 pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1641 * @param pVCpu The current CPU.
1646 int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd)
1648 PVM pVM = pVCpu->CTX_SUFF(pVM);
1651 PX86PDPT pGuestPDPT = pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt);
1655 bool const fChanged = pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] != GCPhys;
1674 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1676 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1680 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = GCPhys;
1681 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1684 *ppPd = pVCpu->pgm.s.CTX_SUFF(apGstPaePDs)[iPdpt];
1691 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1692 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = 0;
1694 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = 0;
1696 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = 0;
1708 * @param pVCpu The current CPU.
1712 int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4)
1714 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstAmd64Pml4));
1715 PVM pVM = pVCpu->CTX_SUFF(pVM);
1718 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK;
1727 pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1729 pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1749 * @param pVCpu Pointer to the VMCPU.
1753 VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPU pVCpu, PX86PDPE paPdpes)
1755 Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1757 paPdpes[0] = pVCpu->pgm.s.aGstPaePdpeRegs[0];
1758 paPdpes[1] = pVCpu->pgm.s.aGstPaePdpeRegs[1];
1759 paPdpes[2] = pVCpu->pgm.s.aGstPaePdpeRegs[2];
1760 paPdpes[3] = pVCpu->pgm.s.aGstPaePdpeRegs[3];
1770 * @param pVCpu Pointer to the VMCPU.
1776 VMM_INT_DECL(void) PGMGstUpdatePaePdpes(PVMCPU pVCpu, PCX86PDPE paPdpes)
1778 Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1780 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.aGstPaePdpeRegs); i++)
1782 if (pVCpu->pgm.s.aGstPaePdpeRegs[i].u != paPdpes[i].u)
1784 pVCpu->pgm.s.aGstPaePdpeRegs[i] = paPdpes[i];
1787 pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
1789 pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
1791 pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
1792 pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1796 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
1803 * @param pVCpu Pointer to the VMCPU.
1805 VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
1807 PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1816 * @param pVCpu Pointer to the VMCPU.
1818 VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
1821 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1822 return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1862 * @param pVCpu Pointer to the VMCPU.
1864 VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
1866 switch (pVCpu->pgm.s.enmShadowMode)
1884 AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
1931 * @param pVCpu Pointer to the VMCPU.
1935 VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
1937 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
1938 PVM pVM = pVCpu->CTX_SUFF(pVM);
1940 VMCPU_ASSERT_EMT(pVCpu);
1946 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1948 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1949 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
1956 switch (pVCpu->pgm.s.enmGuestMode)
1970 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
1972 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1974 RTGCPHYS GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
1975 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1976 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1980 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1985 Assert(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3));
1986 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1987 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
1989 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1993 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1995 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3));
2011 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
2013 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2017 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3Global));
2019 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3));
2022 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
2041 * @param pVCpu Pointer to the VMCPU.
2044 VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
2046 VMCPU_ASSERT_EMT(pVCpu);
2047 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
2050 Assert(pVCpu->CTX_SUFF(pVM)->pgm.s.fNestedPaging || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
2051 Assert(!pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM)));
2052 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
2059 switch (pVCpu->pgm.s.enmGuestMode)
2073 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2075 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
2077 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2078 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
2082 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2095 * @param pVCpu Pointer to the VMCPU.
2101 VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
2105 VMCPU_ASSERT_EMT(pVCpu);
2111 rc = pgmPoolSyncCR3(pVCpu);
2122 if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
2125 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2126 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2127 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2135 VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
2141 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
2143 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
2145 RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3; NOREF(GCPhysCR3Old);
2147 switch (pVCpu->pgm.s.enmGuestMode)
2161 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2163 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
2165 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2166 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
2171 || (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2175 rc = pgmPoolSyncCR3(pVCpu);
2178 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
2189 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2190 rc = PGM_BTH_PFN(SyncCR3, pVCpu)(pVCpu, cr0, cr3, cr4, fGlobal);
2191 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2195 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2201 if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
2203 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2204 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2205 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2211 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
2213 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2214 Assert(!pVCpu->CTX_SUFF(pVM)->pgm.s.fMappingsFixed);
2215 Assert(pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM)));
2223 PGM_INVL_VCPU_TLBS(pVCpu);
2238 * @param pVCpu Pointer to the VMCPU.
2243 VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
2247 VMCPU_ASSERT_EMT(pVCpu);
2259 if (pVCpu->pgm.s.fGst32BitPageSizeExtension != fPse)
2260 Log(("PGMChangeMode: CR4.PSE %d -> %d\n", pVCpu->pgm.s.fGst32BitPageSizeExtension, fPse));
2261 pVCpu->pgm.s.fGst32BitPageSizeExtension = fPse;
2282 if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
2286 PGM_INVL_VCPU_TLBS(pVCpu);
2289 return PGMR3ChangeMode(pVCpu->CTX_SUFF(pVM), pVCpu, enmGuestMode);
2300 * @param pVCpu The cross context virtual CPU structure of the caller.
2303 VMMDECL(void) PGMCr0WpEnabled(PVMCPU pVCpu)
2313 if (pVCpu->pgm.s.cNetwareWp0Hacks > 0)
2315 Assert(pVCpu->CTX_SUFF(pVM)->cCpus == 1);
2317 Log(("PGMCr0WpEnabled: %llu WP0 hacks active - clearing page pool\n", pVCpu->pgm.s.cNetwareWp0Hacks));
2318 pVCpu->pgm.s.cNetwareWp0Hacks = 0;
2319 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL;
2320 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2331 * @param pVCpu Pointer to the VMCPU.
2333 VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
2335 return pVCpu->pgm.s.enmGuestMode;
2343 * @param pVCpu Pointer to the VMCPU.
2345 VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
2347 return pVCpu->pgm.s.enmShadowMode;
2416 * @param pVCpu The virtual CPU for which EFER changed.
2419 VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe)
2421 /** @todo VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu); */
2424 pVCpu->pgm.s.fNoExecuteEnabled = fNxe;
2427 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2428 pVCpu->pgm.s.fGstPaeMbzPteMask &= ~X86_PTE_PAE_NX;
2429 pVCpu->pgm.s.fGstPaeMbzPdeMask &= ~X86_PDE_PAE_NX;
2430 pVCpu->pgm.s.fGstPaeMbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2431 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask - N/A */
2432 pVCpu->pgm.s.fGstAmd64MbzPteMask &= ~X86_PTE_PAE_NX;
2433 pVCpu->pgm.s.fGstAmd64MbzPdeMask &= ~X86_PDE_PAE_NX;
2434 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2435 pVCpu->pgm.s.fGstAmd64MbzPdpeMask &= ~X86_PDPE_LM_NX;
2436 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask &= ~X86_PDPE_LM_NX;
2437 pVCpu->pgm.s.fGstAmd64MbzPml4eMask &= ~X86_PML4E_NX;
2439 pVCpu->pgm.s.fGst64ShadowedPteMask |= X86_PTE_PAE_NX;
2440 pVCpu->pgm.s.fGst64ShadowedPdeMask |= X86_PDE_PAE_NX;
2441 pVCpu->pgm.s.fGst64ShadowedBigPdeMask |= X86_PDE2M_PAE_NX;
2442 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask |= X86_PDE2M_PAE_NX;
2443 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask |= X86_PDPE_LM_NX;
2444 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask |= X86_PML4E_NX;
2448 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2449 pVCpu->pgm.s.fGstPaeMbzPteMask |= X86_PTE_PAE_NX;
2450 pVCpu->pgm.s.fGstPaeMbzPdeMask |= X86_PDE_PAE_NX;
2451 pVCpu->pgm.s.fGstPaeMbzBigPdeMask |= X86_PDE2M_PAE_NX;
2452 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask -N/A */
2453 pVCpu->pgm.s.fGstAmd64MbzPteMask |= X86_PTE_PAE_NX;
2454 pVCpu->pgm.s.fGstAmd64MbzPdeMask |= X86_PDE_PAE_NX;
2455 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask |= X86_PDE2M_PAE_NX;
2456 pVCpu->pgm.s.fGstAmd64MbzPdpeMask |= X86_PDPE_LM_NX;
2457 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask |= X86_PDPE_LM_NX;
2458 pVCpu->pgm.s.fGstAmd64MbzPml4eMask |= X86_PML4E_NX;
2460 pVCpu->pgm.s.fGst64ShadowedPteMask &= ~X86_PTE_PAE_NX;
2461 pVCpu->pgm.s.fGst64ShadowedPdeMask &= ~X86_PDE_PAE_NX;
2462 pVCpu->pgm.s.fGst64ShadowedBigPdeMask &= ~X86_PDE2M_PAE_NX;
2463 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask &= ~X86_PDE2M_PAE_NX;
2464 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask &= ~X86_PDPE_LM_NX;
2465 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask &= ~X86_PML4E_NX;
2558 * @param pVCpu The current CPU.
2563 int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL)
2578 rc = pgmRZDynMapHCPageInlined(pVCpu, PGM_PAGE_GET_HCPHYS(pPage), &pv RTLOG_COMMA_SRC_POS_ARGS);
2764 PVMCPU pVCpu = &pVM->aCpus[0];
2778 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
2801 * @param pVCpu Pointer to the VMCPU.
2805 VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
2807 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2809 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVCpu)(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
2811 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);