Lines Matching refs:pVCpu

114 PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode);
115 PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta);
116 PGM_SHW_DECL(int, Exit)(PVMCPU pVCpu);
119 PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
120 PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags);
171 * @param pVCpu Pointer to the VMCPU.
174 PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode)
186 PVM pVM = pVCpu->pVMR3;
190 Assert(!pVCpu->pgm.s.pShwPageCR3R3);
194 int rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_ROOT_NESTED, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
199 pVCpu->pgm.s.pShwPageCR3R3 = pNewShwPageCR3;
201 pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.pShwPageCR3R3);
202 pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.pShwPageCR3R3);
206 Log(("Enter nested shadow paging mode: root %RHv phys %RHp\n", pVCpu->pgm.s.pShwPageCR3R3, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key));
208 NOREF(pVCpu); NOREF(fIs64BitsPagingMode);
218 * @param pVCpu Pointer to the VMCPU.
221 PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta)
223 pVCpu->pgm.s.pShwPageCR3RC += offDelta;
232 * @param pVCpu Pointer to the VMCPU.
234 PGM_SHW_DECL(int, Exit)(PVMCPU pVCpu)
236 PVM pVM = pVCpu->pVMR3;
238 if ( ( pVCpu->pgm.s.enmShadowMode == PGMMODE_NESTED
239 || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT)
240 && pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
251 /* pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)); */
253 pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
254 pVCpu->pgm.s.pShwPageCR3R3 = 0;
255 pVCpu->pgm.s.pShwPageCR3R0 = 0;
256 pVCpu->pgm.s.pShwPageCR3RC = 0;