CPUM,IEM: Expose GuestFeatures and HostFeatures (exploded CPUID), making IEM use it. Early XSAVE/AVX guest support preps.

VMM/CPUM: nit.

CPUM: Use XSAVE/XRSTOR for host state.

CPUM: State saving fixes.

Remove CPUFeatures and CPUFeaturesExt from CPUM, use HostFeatures instead. Extended HostFeatures.

Removed support for host CPUs without FXSAVE/FXRSTOR support.

gcc build fix

VMM,REM: Allocate the FPU/SSE/AVX/FUTURE state stuff. We need to use pointers to substates anyway and this will make CPUMCPU much smaller.

docs

CPUMCTX,CPUMHOST: Replaced the fpu (X86FXSAVE) member with an XState (X86XSAVEAREA) member.

Corrected x86.h/mac typo.

Forgot this one again.

CPUM: Increase the max cpuid leaves a lot. Fixed incorrect sanitizing of leaf 4.

CPUM: Increase the max cpuid leaves a lot. Fixed incorrect sanitizing of leaf 4.

VMM,REM: CPUID revamp - almost there now.

PATM,CPUM: CPUID patch update.

CPUM: Working on refactoring the guest CPUID handling.

Moved all the CPUID related code from CPUM.cpp to CPUMR3CpuId.cpp

VMM/CPUM: Fix crash while dumping hypervisor leafs

doc nits

@cfgm adjustments.

VMM/CPUM: nit.

VMM/CPUM: Dump hypervisor CPUID leaves to the release log.

VMM/CPUM: nit.

VMM/CPUM: Show invariant TSC support in the release log.

VMM: Fix restoring 32-bit guest FPU state on 64-bit capable VMs.

VMM/GIM: Keep Minimal GIM provider guest agnostic.

VMM/CPUM: todo.

VMM: Retire aGuestCpuIdHyper legacy array.

VMM: Implemented hyper heap realloc. and adjusted CPUM CpuId arrays and MSR ranges handling to optionally work with the hyper heap.

VMM/CPUM: comment typo.

CPUM,VMM: More work related to bus, cpu and tsc frequency info. Should cover older core and p6 as well as p4 now.

VMM: two undocumented CPUID bits

CPUM.cpp: Enable SSE4.1 and SSE4.2 by default for trunk.

CPUM.cpp: Added /CPUM/SSE4.1 and /CPUM/SSE4.2 configuration overrides for enabling SSE 4.1 and 4.2 when supported by the host CPU. This will later be made default.

CPUM: Don't use stale pStdFeatureLeaf and pExtFeatureLeaf pointers. Inserting and removing cpuid entires makes them go stale.

CPUM: Make sure a minimum of commonly used MSRs are present by default.

CPUM: More msr hacking.

CPUM.cpp: Off by one bug in new CPUID count limiting code.

VMM: Mapped the MSRs for a core 2 penryn cpu.

CPUM: Fixed CPUID(5) copy&paste regression.

MSR rewrite: initial hacking - half disabled.

VMM/CPUM: typo

Added ASMCpuIdExSlow and made CPUM use it.

VMM: FPU cleanup.

Nit.

Introduced /CPUM/MaxIntelFamilyModelStep config variable to hack Mac OS X guests into working.

VMM/CPUM: Clarify by explicit comment that the msrApicBase shouldn't be added to CPUMCTX.

Implement MSR_PKG_CST_CONFIG_CONTROL for mac os x.

cpumguestinstr: always print what the disassembler returns, and make it return the cached instruction bytes on failure.

CPUMRecalcHyperDRx: Host single stepping in HM-mode fix.

CPU.cpp: Must recalc DRx values on relocation.

CPUM,++: Fix DR6 and DR7 read-as-1 (RA1) and read-as-zero (RAZ) values on load since REM didn't set them right for years. Introduced constants for these values.

VMM/CPUM: cosmetical fix

Runtime/r3/mp-win, Runtime/Makefile: Support for getting physical core count for Windows.

RT_STR_TUPLE

Made dSYM-bundle loading work as well as line numbers in the stack traces (when possible).

VMM/CPUM: show all CPUID leaves in the log, not only the leaves we privode to the guest

VMM/CPUM: Undo r85381 as it breaks SMP debug builds.

VMM/CPUM: Reset TSC to 0 on CPUMR3ResetCpu().

Don't call MMHyperIsInsideArea if we're using HM to execute code, it will return bogus results!

VBOX_WITH_RAW_MODE changes.

- *: Where possible, drop the #ifdef VBOX_WITH_RAW_RING1 when EMIsRawRing1Enabled is used. - SELM: Don't shadow TSS.esp1/ss1 unless ring-1 compression is enabled (also fixed a log statement there). - SELM: selmGuestToShadowDesc should not push ring-1 selectors into ring-2 unless EMIsRawRing1Enabled() holds true. - REM: Don't set CPU_INTERRUPT_EXTERNAL_EXIT in helper_ltr() for now.

Ring-1 compression patches, courtesy of trivirt AG: - main: diff to remove the hwvirt requirement for QNX - rem: diff for dealing with raw ring 0/1 selectors and general changes to allowed guest execution states - vmm: changes for using the guest's TSS selector index as our hypervisor TSS selector (makes str safe) (VBOX_WITH_SAFE_STR ) - vmm: changes for dealing with guest ring 1 code (VBOX_WITH_RAW_RING1) - vmm: change to emulate smsw in RC/R0 (QNX uses this old style instruction a lot so going to qemu for emulation is very expensive) - vmm: change (hack) to kick out patm virtual handlers in case they conflict with guest GDT/TSS write monitors; we should allow multiple handlers per page, but that change would be rather invasive

DBGF,DBGC,++: PVM -> PUVM. Some refactoring and cleanup as well.

PATM: Changed two Main APIs to use PUVM instead of PVM (one of them directly accessed it). Lot's of function scope cleanups.

cpumR3DetectVendor: Use ASMIsXyzCpuEx.

VMMR0/CPUMR0: atomic update of aGuestCpuId*(); fix return type of CPUMR3LogCpuIds()

VMM: don't pass certain CPUID features to the guest if the feature is not supported on some host cores

VMM: allow to disable MONITOR by setting the CFG key "VBoxInternal/CPUM/MONITOR" to 0

Make VBOX_WITH_RAW_MODE= link.

VMM: APIC refactor, cache APIC base MSR during init phase.

VMM: APIC refactor. Moved APIC base MSR to the VCPU (where it belongs) for lockless accesses.

VMM: HM cleanup.

VMM: nits.

VMM/VMMR3/CPUM: CFGM option for exposing CmpXchg16b if the host supports it.

nit.

VMM/VMMR3/CPUMR3: VIA CpuId comments.

CPUMR3ResetCpu: Set the accessed bit in the segment registers. Hope this is right and good.

VMMR3/CPUM.cpp: fix VIA specific CPUID feature dump

Eliminating CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID and CPUMAreHiddenSelRegsValid. Addressing some LDTR and TR things (saved stated, transition to REM).

Fixed blunder in CPUMR3RemLeave (since r62771).

CPUM: Save and restore the internal selector fields.

CPUM: CPUMCPUVENDOR_VIA

cpum.cpp: nits

VMM: RDTSCP support on Intel. Segregated some common CPU features from the AMD superset into Extended features as they're now available on Intel too.

CPUMGetGuestCPL: Drop the context core pointer and use the Guest state in CPUMCPU via pVCpu.

TRPM: Save state directly to the CPUMCPU context member instead of putting on the stack. this avoid copying the state around before returning to host context to service an IRQ, or before using IEM.

CPUM: Combined the visible and hidden selector register data into one structure. Preparing for lazily resolving+caching of hidden registers in raw-mode.

CPUMCTX++: Rearranging the CPUMCTX structure in preparation of some hidden selector register improvments.

CPUM: Fixed saved state bustage. Got two padding equally wrong and shifted the registers inbetween...

CPUM: Changed the _IGNORE SSM field descriptors to _OLD so that I can change the structures more freely. Fixed dr6 restore bug.

CPUM: Changed the loading of the 1.6 state to use fields.

CPUM: Working over the saved state code to put/get structures using field descriptors instead of memory blobs. Found a bustage restoring the 1.6 state wrt hyper state not being subjected to the same restore procedure as the guest one... Probably very relevant since nobody complained.

Doxygen.

Doxygen.

Doxygen.

Doxygen.

Doxygen, comment typos.

bugref..

CPUM/cpumR3DisasInstrRead: Read max size when possible.

DIS: Chagned FNDISREADBYTES to permit reading more bytes that the immeidate request. Not using the read-ahead feature in any important code path yet, that's comming next, bit by bit.

DIS: Split up apvUserData, dropping the 3rd entry. 2nd entry (now pvUser2) is only used by CSAM. Reduces the DISCPUSTATE by another 8 bytes.

DIS: The start of the scoping exercise... Fixed PREFIX_ADDRSIZE that I just busted in the previous commit.

DISCoreOne* -> DISCore*.

DISInstr* -> DISInstrToStr + cbOutput argument.

DIS,VMM,REM,IPRT: Disassembler API adjustments.

CPUM: cosmetical typo

Optionally present basic hypervisor CPUID leaves.

MSRs and MTRRs, CPUM saved state changed. (linux 2.4.31 seems to ignore the capabilites when it comes to fixed MTRRs.)

CPUM.cpp: MXCSR_MASK always was 0xffff not 0 (0xffbf) because of REM.

VMM: Don't use generic IPE status codes, use specific ones. Part 2.

VMM: -Wunused-parameter

CPUM: Option to set Hypervisor Present bit.

CPUM,x86.h: Hypervisor present bit.

CPUM.cpp: Corrected initial FTW value.

CPUM: Don't assert if the supported standard CPUID level is smaller than 4 because eax might contain garbage in that case (happened on very old Intel Xeons)

build fix.

IEM: bsf, bsr, bt, btc, bts, btr and leave. Some cleaning up.

VMM: Change initial TSS attribs to what guests expect.

CPUM,Debugger: Registers, still some details left.

VMM reorg: Moving the public include files from include/VBox to include/VBox/vmm.

VMM source reorg.