PGMInternal.h revision 2afbe132eb7931e0125141eabe3a48e08f1ffab5
/* $Id$ */
/** @file
* PGM - Internal header file.
*/
/*
* Copyright (C) 2006-2010 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
#ifndef ___PGMInternal_h
#define ___PGMInternal_h
#include <iprt/critsect.h>
/** @defgroup grp_pgm_int Internals
* @ingroup grp_pgm
* @internal
* @{
*/
/** @name PGM Compile Time Config
* @{
*/
/**
* Indicates that there are no guest mappings to care about.
* Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
*/
#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
# define PGM_WITHOUT_MAPPINGS
#endif
/**
* Check and skip global PDEs for non-global flushes
*/
/**
* Optimization for PAE page tables that are modified often
*/
//#if 0 /* disabled again while debugging */
#ifndef IN_RC
# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
#endif
//#endif
/**
* Large page support enabled only on 64 bits hosts; applies to nested paging only.
*/
# define PGM_WITH_LARGE_PAGES
#endif
/**
* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
* VMX_EXIT_EPT_MISCONFIG.
*/
#if 1 /* testing */
# define PGM_WITH_MMIO_OPTIMIZATIONS
#endif
/**
* Sync N pages instead of a whole page table
*/
#define PGM_SYNC_N_PAGES
/**
* Number of pages to sync during a page fault
*
* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
*
* world switch overhead, so let's sync more.
*/
# ifdef IN_RING0
/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
* but ~5% fewer faults.
*/
# define PGM_SYNC_NR_PAGES 32
#else
# define PGM_SYNC_NR_PAGES 8
#endif
/**
* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
*/
#define PGM_MAX_PHYSCACHE_ENTRIES 64
/** @def PGMPOOL_CFG_MAX_GROW
* The maximum number of pages to add to the pool in one go.
*/
/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
* Enables some extra assertions for virtual handlers (mainly phys2virt related).
*/
#ifdef VBOX_STRICT
# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
#endif
/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
* Enables the experimental lazy page allocation code. */
/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
* Enables real write monitoring of pages, i.e. mapping them read-only and
* only making them writable when getting a write access #PF. */
/** @} */
/** @name PDPT and PML4 flags.
* These are placed in the three bits available for system programs in
* the PDPT and PML4 entries.
* @{ */
/** The entry is a permanent one and it's must always be present.
* Never free such an entry. */
/** Mapping (hypervisor allocated pagetable). */
/** @} */
/** @name Page directory flags.
* These are placed in the three bits available for system programs in
* the page directory entries.
* @{ */
/** Mapping (hypervisor allocated pagetable). */
/** Made read-only to facilitate dirty bit tracking. */
/** @} */
/** @name Page flags.
* These are placed in the three bits available for system programs in
* the page entries.
* @{ */
/** Made read-only to facilitate dirty bit tracking. */
#ifndef PGM_PTFLAGS_CSAM_VALIDATED
/** Scanned and approved by CSAM (tm).
* NOTE: Must be identical to the one defined in CSAMInternal.h!!
#endif
/** @} */
/** @name Defines used to indicate the shadow and guest paging in the templates.
* @{ */
#define PGM_TYPE_REAL 1
#define PGM_TYPE_PROT 2
#define PGM_TYPE_32BIT 3
#define PGM_TYPE_PAE 4
#define PGM_TYPE_AMD64 5
#define PGM_TYPE_NESTED 6
#define PGM_TYPE_EPT 7
#define PGM_TYPE_MAX PGM_TYPE_EPT
/** @} */
/** Macro for checking if the guest is using paging.
* @param uGstType PGM_TYPE_*
* @param uShwType PGM_TYPE_*
* @remark ASSUMES certain order of the PGM_TYPE_* values.
*/
( (uGstType) >= PGM_TYPE_32BIT \
&& (uShwType) != PGM_TYPE_NESTED \
&& (uShwType) != PGM_TYPE_EPT)
/** Macro for checking if the guest supports the NX bit.
* @param uGstType PGM_TYPE_*
* @param uShwType PGM_TYPE_*
* @remark ASSUMES certain order of the PGM_TYPE_* values.
*/
( (uGstType) >= PGM_TYPE_PAE \
&& (uShwType) != PGM_TYPE_NESTED \
&& (uShwType) != PGM_TYPE_EPT)
/** @def PGM_HCPHYS_2_PTR
* Maps a HC physical page pool address to a virtual address.
*
* @returns VBox status code.
* @param pVM The VM handle.
* @param pVCpu The current CPU.
* @param HCPhys The HC physical address to map to a virtual one.
* @param ppv Where to store the virtual address. No need to cast
* this.
*
* @remark Use with care as we don't have so much dynamic mapping space in
* ring-0 on 32-bit darwin and in RC.
* @remark There is no need to assert on the result.
*/
#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
#else
#endif
/** @def PGM_GCPHYS_2_PTR_V2
* Maps a GC physical page address to a virtual address.
*
* @returns VBox status code.
* @param pVM The VM handle.
* @param pVCpu The current CPU.
* @param GCPhys The GC physical address to map to a virtual one.
* @param ppv Where to store the virtual address. No need to cast this.
*
* @remark Use with care as we don't have so much dynamic mapping space in
* ring-0 on 32-bit darwin and in RC.
* @remark There is no need to assert on the result.
*/
#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
#else
#endif
/** @def PGM_GCPHYS_2_PTR
* Maps a GC physical page address to a virtual address.
*
* @returns VBox status code.
* @param pVM The VM handle.
* @param GCPhys The GC physical address to map to a virtual one.
* @param ppv Where to store the virtual address. No need to cast this.
*
* @remark Use with care as we don't have so much dynamic mapping space in
* ring-0 on 32-bit darwin and in RC.
* @remark There is no need to assert on the result.
*/
/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
* Maps a GC physical page address to a virtual address.
*
* @returns VBox status code.
* @param pVCpu The current CPU.
* @param GCPhys The GC physical address to map to a virtual one.
* @param ppv Where to store the virtual address. No need to cast this.
*
* @remark Use with care as we don't have so much dynamic mapping space in
* ring-0 on 32-bit darwin and in RC.
* @remark There is no need to assert on the result.
*/
#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
/** @def PGM_GCPHYS_2_PTR_EX
* Maps a unaligned GC physical page address to a virtual address.
*
* @returns VBox status code.
* @param pVM The VM handle.
* @param GCPhys The GC physical address to map to a virtual one.
* @param ppv Where to store the virtual address. No need to cast this.
*
* @remark Use with care as we don't have so much dynamic mapping space in
* ring-0 on 32-bit darwin and in RC.
* @remark There is no need to assert on the result.
*/
#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
#else
#endif
/** @def PGM_DYNMAP_UNUSED_HINT
* is no longer used.
*
* For best effect only apply this to the page that was mapped most recently.
*
* @param pVCpu The current CPU.
* @param pvPage The pool page.
*/
#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
# ifdef LOG_ENABLED
# else
# endif
#else
#endif
/** @def PGM_DYNMAP_UNUSED_HINT_VM
* is no longer used.
*
* For best effect only apply this to the page that was mapped most recently.
*
* @param pVM The VM handle.
* @param pvPage The pool page.
*/
/** @def PGM_INVL_PG
* Invalidates a page.
*
* @param pVCpu The VMCPU handle.
* @param GCVirt The virtual address of the page to invalidate.
*/
#ifdef IN_RC
#else
#endif
/** @def PGM_INVL_PG_ALL_VCPU
* Invalidates a page on all VCPUs
*
* @param pVM The VM handle.
* @param GCVirt The virtual address of the page to invalidate.
*/
#ifdef IN_RC
#else
#endif
/** @def PGM_INVL_BIG_PG
* Invalidates a 4MB page directory entry.
*
* @param pVCpu The VMCPU handle.
* @param GCVirt The virtual address within the page directory to invalidate.
*/
#ifdef IN_RC
#else
#endif
/** @def PGM_INVL_VCPU_TLBS()
* Invalidates the TLBs of the specified VCPU
*
* @param pVCpu The VMCPU handle.
*/
#ifdef IN_RC
#else
#endif
/** @def PGM_INVL_ALL_VCPU_TLBS()
* Invalidates the TLBs of all VCPUs
*
* @param pVM The VM handle.
*/
#ifdef IN_RC
#else
#endif
* present.
*
* @{
*/
#if 1
/**
* For making sure that u1Present and X86_PTE_P checks doesn't mistake
* invalid entries for present.
* @sa X86PTEPAE.
*/
typedef union PGMSHWPTEPAE
{
/** Unsigned integer view */
/* Not other views. */
} PGMSHWPTEPAE;
# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
/**
* For making sure that u1Present and X86_PTE_P checks doesn't mistake
* invalid entries for present.
* @sa X86PTPAE.
*/
typedef struct PGMSHWPTPAE
{
} PGMSHWPTPAE;
#else
typedef X86PTEPAE PGMSHWPTEPAE;
typedef X86PTPAE PGMSHWPTPAE;
# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
#endif
/** Pointer to a shadow PAE PTE. */
typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
/** Pointer to a const shadow PAE PTE. */
typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
/** Pointer to a shadow PAE page table. */
typedef PGMSHWPTPAE *PPGMSHWPTPAE;
/** Pointer to a const shadow PAE page table. */
typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
/** @} */
/** Size of the GCPtrConflict array in PGMMAPPING.
* @remarks Must be a power of two. */
#define PGMMAPPING_CONFLICT_MAX 8
/**
* Structure for tracking GC Mappings.
*
* This structure is used by linked list in both GC and HC.
*/
typedef struct PGMMAPPING
{
/** Pointer to next entry. */
/** Pointer to next entry. */
/** Pointer to next entry. */
/** Indicate whether this entry is finalized. */
bool fFinalized;
/** Start Virtual address. */
/** Last Virtual address (inclusive). */
/** Range size (bytes). */
/** Pointer to relocation callback function. */
/** User argument to the callback. */
/** Mapping description / name. For easing debugging. */
/** Last 8 addresses that caused conflicts. */
/** Number of conflicts for this hypervisor mapping. */
/** Number of page tables. */
/** Array of page table mapping data. Each entry
* describes one page table. The array can be longer
* than the declared length.
*/
struct
{
/** The HC physical address of the page table. */
/** The HC physical address of the first PAE page table. */
/** The HC physical address of the second PAE page table. */
/** The HC virtual address of the 32-bit page table. */
/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
/** The RC virtual address of the 32-bit page table. */
/** The RC virtual address of the two PAE page table. */
/** The R0 virtual address of the 32-bit page table. */
/** The R0 virtual address of the two PAE page table. */
} aPTs[1];
} PGMMAPPING;
/** Pointer to structure for tracking GC Mappings. */
typedef struct PGMMAPPING *PPGMMAPPING;
/**
* Physical page access handler structure.
*
* This is used to keep track of physical address ranges
* which are being monitored in some kind of way.
*/
typedef struct PGMPHYSHANDLER
{
/** Access type. */
/** Number of pages to update. */
/** Set if we have pages that have been aliased. */
/** Set if we have pages that have temporarily been disabled. */
/** Pointer to R3 callback function. */
/** User argument for R3 handlers. */
/** Pointer to R0 callback function. */
/** User argument for R0 handlers. */
/** Pointer to RC callback function. */
/** User argument for RC handlers. */
/** Description / Name. For easing debugging. */
#ifdef VBOX_WITH_STATISTICS
/** Profiling of this handler. */
#endif
/** Pointer to a physical page access handler structure. */
typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
/**
* Cache node for the physical addresses covered by a virtual handler.
*/
typedef struct PGMPHYS2VIRTHANDLER
{
/** Core node for the tree based on physical ranges. */
/** Offset from this struct to the PGMVIRTHANDLER structure. */
/** Offset of the next alias relative to this one.
* Bit 0 is used for indicating whether we're in the tree.
* Bit 1 is used for indicating that we're the head node.
*/
/** Pointer to a phys to virtual handler structure. */
typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
* node is in the tree. */
#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
* node is in the head of an alias chain.
* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
/**
* Virtual page access handler structure.
*
* This is used to keep track of virtual address ranges
* which are being monitored in some kind of way.
*/
typedef struct PGMVIRTHANDLER
{
/** Core node for the tree based on virtual ranges. */
/** Size of the range (in bytes). */
/** Number of cache pages. */
/** Access type. */
/** Pointer to the RC callback function. */
#if HC_ARCH_BITS == 64
#endif
/** Pointer to the R3 callback function for invalidation. */
/** Pointer to the R3 callback function. */
/** Description / Name. For easing debugging. */
#ifdef VBOX_WITH_STATISTICS
/** Profiling of this handler. */
#endif
/** Array of cached physical addresses for the monitored ranged. */
/** Pointer to a virtual page access handler structure. */
typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
/** @name Page type predicates.
* @{ */
/** @} */
/**
* A Physical Guest Page tracking structure.
*
* The format of this structure is complicated because we have to fit a lot
* of information into as few bits as possible. The format is also subject
* to change (there is one coming up soon). Which means that for we'll be
* using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
* accesses to the structure.
*/
typedef union PGMPAGE
{
/** Structured view. */
struct
{
/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_*). */
/** 3:2 - Paging structure needed to map the page
* (PGM_PAGE_PDE_TYPE_*). */
/** 4 - Indicator of dirty page for fault tolerance tracking. */
/** 5 - Flag indicating that a write monitored page was written to
* when set. */
/** 7:6 - Unused. */
/** 9:8 - The physical handler state (PGM_PAGE_HNDL_VIRT_STATE_*). */
/** 11:10 - Unused. */
/** 12:48 - The host physical frame number (shift left to get the
* address). */
/** 50:48 - The page state. */
/** 51:53 - The page type (PGMPAGETYPE). */
/** 63:54 - PTE index for usage tracking (page pool). */
/** The GMM page ID. */
/** Usage tracking (page pool). */
/** The number of read locks on this page. */
/** The number of write locks on this page. */
} s;
/** 64-bit integer view. */
/** 16-bit view. */
/** 16-bit view. */
/** 8-bit view. */
} PGMPAGE;
/** Pointer to a physical guest page. */
/** Pointer to a const physical guest page. */
/** Pointer to a physical guest page pointer. */
/**
* Clears the page structure.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
#define PGM_PAGE_CLEAR(a_pPage) \
do { \
} while (0)
/**
* Initializes the page structure.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
do { \
} while (0)
/**
* Initializes the page structure of a ZERO page.
* @param a_pPage Pointer to the physical guest page tracking structure.
* @param a_pVM The VM handle (for getting the zero page address).
* @param a_uType The page type (PGMPAGETYPE).
*/
PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
/** @name The Page state, PGMPAGE::uStateY.
* @{ */
/** The zero page.
* This is a per-VM page that's never ever mapped writable. */
#define PGM_PAGE_STATE_ZERO 0
/** A allocated page.
* This is a per-VM page allocated from the page pool (or wherever
* we get MMIO2 pages from if the type is MMIO2).
*/
#define PGM_PAGE_STATE_ALLOCATED 1
/** A allocated page that's being monitored for writes.
* The shadow page table mappings are read-only. When a write occurs, the
* fWrittenTo member is set, the page remapped as read-write and the state
* moved back to allocated. */
#define PGM_PAGE_STATE_WRITE_MONITORED 2
/** The page is shared, aka. copy-on-write.
* This is a page that's shared with other VMs. */
#define PGM_PAGE_STATE_SHARED 3
/** The page is ballooned, so no longer available for this VM. */
#define PGM_PAGE_STATE_BALLOONED 4
/** @} */
/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
#else
# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
#endif
/**
* Gets the page state.
* @returns page state (PGM_PAGE_STATE_*).
* @param a_pPage Pointer to the physical guest page tracking structure.
*
* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
* builds.
*/
#if defined(__GNUC__) && defined(VBOX_STRICT)
# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
#else
# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
#endif
/**
* Sets the page state.
* @param a_pVM The VM handle, only used for lock ownership assertions.
* @param a_pPage Pointer to the physical guest page tracking structure.
* @param a_uState The new page state.
*/
/**
* Gets the host physical address of the guest page.
* @returns host physical address (RTHCPHYS).
* @param a_pPage Pointer to the physical guest page tracking structure.
*
* @remarks In strict builds on gcc platforms, this macro will make some ugly
* current context. It will use this pVM variable to assert that the
* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
* pVM is not around.
*/
#if 0
#else
# if defined(__GNUC__) && defined(VBOX_STRICT)
# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
# else
# endif
#endif
/**
* Sets the host physical address of the guest page.
*
* @param a_pVM The VM handle, only used for lock ownership assertions.
* @param a_pPage Pointer to the physical guest page tracking structure.
* @param a_HCPhys The new host physical address.
*/
do { \
} while (0)
/**
* Get the Page ID.
* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/**
* Sets the Page ID.
* @param a_pVM The VM handle, only used for lock ownership assertions.
* @param a_pPage Pointer to the physical guest page tracking structure.
* @param a_idPage The new page ID.
*/
do { \
} while (0)
/**
* Get the Chunk ID.
* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/**
* Get the index of the page within the allocation chunk.
* @returns The page index.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/**
* Gets the page type.
* @returns The page type.
* @param a_pPage Pointer to the physical guest page tracking structure.
*
* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
* builds.
*/
#if defined(__GNUC__) && defined(VBOX_STRICT)
# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
#else
# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
#endif
/**
* Sets the page type.
*
* @param a_pVM The VM handle, only used for lock ownership assertions.
* @param a_pPage Pointer to the physical guest page tracking structure.
* @param a_enmType The new page type (PGMPAGETYPE).
*/
/**
* Gets the page table index
* @returns The page table index.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/**
* Sets the page table index.
* @param a_pVM The VM handle, only used for lock ownership assertions.
* @param a_pPage Pointer to the physical guest page tracking structure.
* @param a_iPte New page table index.
*/
/**
* Checks if the page is marked for MMIO.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/**
* Checks if the page is backed by the ZERO page.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/**
* Checks if the page is backed by a SHARED page.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/**
* Checks if the page is ballooned.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/**
* Checks if the page is allocated.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/**
* Marks the page as written to (for GMM change monitoring).
* @param a_pVM The VM handle, only used for lock ownership assertions.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/**
* Clears the written-to indicator.
* @param a_pVM The VM handle, only used for lock ownership assertions.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/**
* Checks if the page was marked as written-to.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/**
* Marks the page as dirty for FTM
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/**
* Clears the FTM dirty indicator
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/**
* Checks if the page was marked as dirty for FTM
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/** @name PT usage values (PGMPAGE::u2PDEType).
*
* @{ */
/** Either as a PT or PDE. */
#define PGM_PAGE_PDE_TYPE_DONTCARE 0
/** Must use a page table to map the range. */
#define PGM_PAGE_PDE_TYPE_PT 1
/** Can use a page directory entry to map the continuous range. */
#define PGM_PAGE_PDE_TYPE_PDE 2
/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
/** @} */
/**
* Set the PDE type of the page
* @param a_pVM The VM handle, only used for lock ownership assertions.
* @param a_pPage Pointer to the physical guest page tracking structure.
* @param a_uType PGM_PAGE_PDE_TYPE_*.
*/
/**
* Checks if the page was marked being part of a large page
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/** Enabled optimized access handler tests.
* These optimizations makes ASSUMPTIONS about the state values and the s1
* layout. When enabled, the compiler should normally generate more compact
* code.
*/
#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
*
* @remarks The values are assigned in order of priority, so we can calculate
* the correct state for a page with different handlers installed.
* @{ */
/** No handler installed. */
#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
/** Monitoring is temporarily disabled. */
#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
/** Write access is monitored. */
#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
/** All access is monitored. */
#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
/** @} */
/**
* Gets the physical access handler state of a page.
* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/**
* Sets the physical access handler state of a page.
* @param a_pPage Pointer to the physical guest page tracking structure.
* @param a_uState The new state value.
*/
/**
* Checks if the page has any physical access handlers, including temporarily disabled ones.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
/**
* Checks if the page has any active physical access handlers.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
*
* @remarks The values are assigned in order of priority, so we can calculate
* the correct state for a page with different handlers installed.
* @{ */
/** No handler installed. */
#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
/* 1 is reserved so the lineup is identical with the physical ones. */
/** Write access is monitored. */
#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
/** All access is monitored. */
#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
/** @} */
/**
* Gets the virtual access handler state of a page.
* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/**
* Sets the virtual access handler state of a page.
* @param a_pPage Pointer to the physical guest page tracking structure.
* @param a_uState The new state value.
*/
/**
* Checks if the page has any virtual access handlers.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage) \
/**
* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
* virtual handlers.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
/**
* Checks if the page has any access handlers, including temporarily disabled ones.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
#else
# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
#endif
/**
* Checks if the page has any active access handlers.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
#else
# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
#endif
/**
* Checks if the page has any active access handlers catching all accesses.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
#else
# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
#endif
/** @def PGM_PAGE_GET_TRACKING
* Gets the packed shadow page pool tracking data associated with a guest page.
* @returns uint16_t containing the data.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
#if defined(__GNUC__) && defined(VBOX_STRICT)
# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
#else
#endif
/** @def PGM_PAGE_SET_TRACKING
* Sets the packed shadow page pool tracking data associated with a guest page.
* @param a_pVM The VM handle, only used for lock ownership assertions.
* @param a_pPage Pointer to the physical guest page tracking structure.
* @param a_u16TrackingData The tracking data to store.
*/
/** @def PGM_PAGE_GET_TD_CREFS
* Gets the @a cRefs tracking data member.
* @returns cRefs.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
/** @def PGM_PAGE_GET_TD_IDX
* Gets the @a idx tracking data member.
* @returns idx.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
#define PGM_PAGE_GET_TD_IDX(a_pPage) \
#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
/** Max number of locks on a page. */
/** Get the read lock count.
* @returns count.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/** Get the write lock count.
* @returns count.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/** Decrement the read lock counter.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/** Decrement the write lock counter.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/** Increment the read lock counter.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
/** Increment the write lock counter.
* @param a_pPage Pointer to the physical guest page tracking structure.
*/
#if 0
/** Enables sanity checking of write monitoring using CRC-32. */
# define PGMLIVESAVERAMPAGE_WITH_CRC32
#endif
/**
* Per page live save tracking data.
*/
typedef struct PGMLIVESAVERAMPAGE
{
/** Number of times it has been dirtied. */
/** Whether it is currently dirty. */
/** Ignore the page.
* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
* deal with these after pausing the VM and DevPCI have said it bit about
* remappings. */
/** Was a ZERO page last time around. */
/** Was a SHARED page last time around. */
/** Bits reserved for future use. */
/** CRC-32 for the page. This is for internal consistency checks. */
#endif
#else
#endif
/** Pointer to the per page live save tracking data. */
typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
/**
* RAM range for GC Phys to HC Phys conversion.
*
* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
* conversions too, but we'll let MM handle that for now.
*
* This structure is used by linked lists in both GC and HC.
*/
typedef struct PGMRAMRANGE
{
/** Start of the range. Page aligned. */
/** Size of the range. (Page aligned of course). */
/** Pointer to the next RAM range - for R3. */
/** Pointer to the next RAM range - for R0. */
/** Pointer to the next RAM range - for RC. */
/** PGM_RAM_RANGE_FLAGS_* flags. */
/** Last address in the range (inclusive). Page aligned (-1). */
/** Start of the HC mapping of the range. This is only used for MMIO2. */
/** Live save per page tracking data. */
/** The range description. */
/** Pointer to self - R0 pointer. */
/** Pointer to self - RC pointer. */
/** Alignment padding. */
/** Pointer to the left search three node - ring-3 context. */
/** Pointer to the right search three node - ring-3 context. */
/** Pointer to the left search three node - ring-0 context. */
/** Pointer to the right search three node - ring-0 context. */
/** Pointer to the left search three node - raw-mode context. */
/** Pointer to the right search three node - raw-mode context. */
/** Padding to make aPage aligned on sizeof(PGMPAGE). */
#if HC_ARCH_BITS == 32
#endif
/** Array of physical guest page tracking structures. */
} PGMRAMRANGE;
/** Pointer to RAM range for GC Phys to HC Phys conversion. */
typedef PGMRAMRANGE *PPGMRAMRANGE;
/** @name PGMRAMRANGE::fFlags
* @{ */
/** The RAM range is floating around as an independent guest mapping. */
/** Ad hoc RAM range for an ROM mapping. */
/** Ad hoc RAM range for an MMIO mapping. */
/** Ad hoc RAM range for an MMIO2 mapping. */
/** @} */
/** Tests if a RAM range is an ad hoc one or not.
* @param pRam The RAM range.
*/
#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
/** The number of entries in the RAM range TLBs (there is one for each
* context). Must be a power of two. */
#define PGM_RAMRANGE_TLB_ENTRIES 8
/**
* Calculates the RAM range TLB index for the physical address.
*
* @returns RAM range TLB index.
* @param GCPhys The guest physical address.
*/
/**
* Per page tracking structure for ROM image.
*
* A ROM image may have a shadow page, in which case we may have two pages
* backing it. This structure contains the PGMPAGE for both while
* PGMRAMRANGE have a copy of the active one. It is important that these
* aren't out of sync in any regard other than page pool tracking data.
*/
typedef struct PGMROMPAGE
{
/** The page structure for the virgin ROM page. */
/** The page structure for the shadow RAM page. */
/** The current protection setting. */
/** Live save status information. Makes use of unused alignment space. */
struct
{
/** The previous protection value. */
/** Written to flag set by the handler. */
bool fWrittenTo;
/** Whether the shadow page is dirty or not. */
bool fDirty;
/** Whether it was dirtied in the recently. */
bool fDirtiedRecently;
} LiveSave;
} PGMROMPAGE;
/** Pointer to a ROM page tracking structure. */
typedef PGMROMPAGE *PPGMROMPAGE;
/**
* A registered ROM image.
*
* This is needed to keep track of ROM image since they generally intrude
* into a PGMRAMRANGE. It also keeps track of additional info like the
* two page sets (read-only virgin and read-write shadow), the current
* state of each page.
*
* Because access handlers cannot easily be executed in a different
* context, the ROM ranges needs to be accessible and in all contexts.
*/
typedef struct PGMROMRANGE
{
/** Pointer to the next range - R3. */
/** Pointer to the next range - R0. */
/** Pointer to the next range - RC. */
/** Pointer alignment */
/** Address of the range. */
/** Address of the last byte in the range. */
/** Size of the range. */
/** The flags (PGMPHYS_ROM_FLAGS_*). */
/** The saved state range ID. */
/** Alignment padding. */
/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
/** The size bits pvOriginal points to. */
/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
* This is used for strictness checks. */
R3PTRTYPE(const void *) pvOriginal;
/** The ROM description. */
/** The per page tracking structures. */
} PGMROMRANGE;
/** Pointer to a ROM range. */
typedef PGMROMRANGE *PPGMROMRANGE;
/**
* Live save per page data for an MMIO2 page.
*
* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
* CRC-32 for detecting changes as well as special handling of zero pages. This
* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
* because of speed (2.5x and 6x slower).)
*
* @todo Implement dirty MMIO2 page reporting that can be enabled during live
* save but normally is disabled. Since we can write monitor guest
* accesses on our own, we only need this for host accesses. Shouldn't be
* too difficult for DevVGA, VMMDev might be doable, the planned
* networking fun will be fun since it involves ring-0.
*/
typedef struct PGMLIVESAVEMMIO2PAGE
{
/** Set if the page is considered dirty. */
bool fDirty;
/** The number of scans this page has remained unchanged for.
* Only updated for dirty pages. */
/** Whether this page was zero at the last scan. */
bool fZero;
/** Alignment padding. */
bool fReserved;
/** CRC-32 for the first half of the page.
* This is used together with u32CrcH2 to quickly detect changes in the page
* during the non-final passes. */
/** CRC-32 for the second half of the page. */
/** SHA-1 for the saved page.
* This is used in the final pass to skip pages without changes. */
/** Pointer to a live save status data for an MMIO2 page. */
typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
/**
* A registered MMIO2 (= Device RAM) range.
*
* There are a few reason why we need to keep track of these
* registrations. One of them is the deregistration & cleanup stuff,
* while another is that the PGMRAMRANGE associated with such a region may
* have to be removed from the ram range list.
*
* Overlapping with a RAM range has to be 100% or none at all. The pages
* in the existing RAM range must not be ROM nor MMIO. A guru meditation
* will be raised if a partial overlap or an overlap of ROM pages is
* encountered. On an overlap we will free all the existing RAM pages and
* put in the ram range pages instead.
*/
typedef struct PGMMMIO2RANGE
{
/** The owner of the range. (a device) */
/** Pointer to the ring-3 mapping of the allocation. */
/** Pointer to the next range - R3. */
/** Whether it's mapped or not. */
bool fMapped;
/** Whether it's overlapping or not. */
bool fOverlapping;
/** The PCI region number.
* @remarks This ASSUMES that nobody will ever really need to have multiple
* PCI devices with matching MMIO region numbers on a single device. */
/** The saved state range ID. */
/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
/** Live save per page tracking data. */
/** The associated RAM range. */
/** Pointer to a MMIO2 range. */
typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
/**
* PGMPhysRead/Write cache entry
*/
typedef struct PGMPHYSCACHEENTRY
{
/** R3 pointer to physical page. */
/** GC Physical address for cache entry */
#endif
/**
* PGMPhysRead/Write cache to reduce REM memory access overhead
*/
typedef struct PGMPHYSCACHE
{
/** Bitmap of valid cache entries */
/** Cache entries */
} PGMPHYSCACHE;
/** Pointer to an allocation chunk ring-3 mapping. */
typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
/** Pointer to an allocation chunk ring-3 mapping pointer. */
typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
/**
* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
*
* The primary tree (Core) uses the chunk id as key.
*/
typedef struct PGMCHUNKR3MAP
{
/** The key is the chunk id. */
/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
* selection. */
/** The current reference count. */
/** The current permanent reference count. */
/** The mapping address. */
void *pv;
/**
* Allocation chunk ring-3 mapping TLB entry.
*/
typedef struct PGMCHUNKR3MAPTLBE
{
/** The chunk id. */
#if HC_ARCH_BITS == 64
#endif
/** The chunk map. */
#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
#else
#endif
/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
/** The number of TLB entries in PGMCHUNKR3MAPTLB.
* @remark Must be a power of two value. */
#define PGM_CHUNKR3MAPTLB_ENTRIES 64
/**
* Allocation chunk ring-3 mapping TLB.
*
* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
* At first glance this might look kinda odd since AVL trees are
* supposed to give the most optimal lookup times of all trees
* due to their balancing. However, take a tree with 1023 nodes
* in it, that's 10 levels, meaning that most searches has to go
* down 9 levels before they find what they want. This isn't fast
* compared to a TLB hit. There is the factor of cache misses,
* and of course the problem with trees and branch prediction.
* This is why we use TLBs in front of most of the trees.
*
* @todo Generalize this TLB + AVL stuff, shouldn't be all that
* difficult when we switch to the new inlined AVL trees (from kStuff).
*/
typedef struct PGMCHUNKR3MAPTLB
{
/** The TLB entries. */
/**
* Calculates the index of a guest page in the Ring-3 Chunk TLB.
* @returns Chunk TLB index.
* @param idChunk The Chunk ID.
*/
/**
* Ring-3 guest page mapping TLB entry.
* @remarks used in ring-0 as well at the moment.
*/
typedef struct PGMPAGER3MAPTLBE
{
/** Address of the page. */
/** The guest page. */
#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
#else
#endif
/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
#else
#endif
/** The address */
#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
#else
R3R0PTRTYPE(void *) volatile pv;
#endif
#if HC_ARCH_BITS == 32
#endif
/** Pointer to an entry in the HC physical TLB. */
typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
/** The number of entries in the ring-3 guest page mapping TLB.
* @remarks The value must be a power of two. */
#define PGM_PAGER3MAPTLB_ENTRIES 256
/**
* Ring-3 guest page mapping TLB.
* @remarks used in ring-0 as well at the moment.
*/
typedef struct PGMPAGER3MAPTLB
{
/** The TLB entries. */
/** Pointer to the ring-3 guest page mapping TLB. */
typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
/**
* Calculates the index of the TLB entry for the specified guest page.
* @returns Physical TLB index.
* @param GCPhys The guest physical address.
*/
/**
* Raw-mode context dynamic mapping cache entry.
*
* Because of raw-mode context being reloctable and all relocations are applied
* in ring-3, this has to be defined here and be RC specific.
*
* @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
*/
typedef struct PGMRCDYNMAPENTRY
{
/** The physical address of the currently mapped page.
* This is duplicate for three reasons: cache locality, cache policy of the PT
* mappings and sanity checks. */
/** Pointer to the page. */
/** The number of references. */
/** PTE pointer union. */
struct PGMRCDYNMAPENTRY_PPTE
{
/** PTE pointer, 32-bit legacy version. */
/** PTE pointer, PAE version. */
} uPte;
/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
/**
* Dynamic mapping cache for the raw-mode context.
*
* This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
* paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
* so that we can perform relocations from PGMR3Relocate. This has the
* consequence that we must have separate ring-0 and raw-mode context versions
* of this struct even if they share the basic elements.
*
* @sa PPGMRZDYNMAP, PGMR0DYNMAP.
*/
typedef struct PGMRCDYNMAP
{
/** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
/** Array for tracking and managing the pages. */
/** The cache size given as a number of pages. */
/** The current load.
* This does not include guard pages. */
/** The max load ever.
* This is maintained to get trigger adding of more mapping space. */
/** The number of guard pages. */
/** The number of users (protected by hInitLock). */
} PGMRCDYNMAP;
/** Pointer to the dynamic cache for the raw-mode context. */
typedef PGMRCDYNMAP *PPGMRCDYNMAP;
/**
* Mapping cache usage set entry.
*
* @remarks 16-bit ints was chosen as the set is not expected to be used beyond
* the dynamic ring-0 and (to some extent) raw-mode context mapping
* cache. If it's extended to include ring-3, well, then something
* will have be changed here...
*/
typedef struct PGMMAPSETENTRY
{
/** Pointer to the page. */
#ifndef IN_RC
#else
# if HC_ARCH_BITS == 64
# endif
#endif
/** The mapping cache index. */
/** The number of references.
* The max is UINT16_MAX - 1. */
/** The number inlined references.
* The max is UINT16_MAX - 1. */
/** Unreferences. */
#if HC_ARCH_BITS == 32
#endif
/** The physical address for this entry. */
/** Pointer to a mapping cache usage set entry. */
typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
/**
* Mapping cache usage set.
*
* This is used in ring-0 and the raw-mode context to track dynamic mappings
* done during exits / traps. The set is
*/
typedef struct PGMMAPSET
{
/** The number of occupied entries.
* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
* dynamic mappings. */
/** The start of the current subset.
* This is UINT32_MAX if no subset is currently open. */
/** The index of the current CPU, only valid if the set is open. */
/** The entries. */
/** HCPhys -> iEntry fast lookup table.
* Use PGMMAPSET_HASH for hashing.
* The entries may or may not be valid, check against cEntries. */
} PGMMAPSET;
/** Pointer to the mapping cache set. */
typedef PGMMAPSET *PPGMMAPSET;
/** PGMMAPSET::cEntries value for a closed set. */
/** Hash function for aiHashTable. */
/** @name Context neutral page mapper TLB.
*
* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
* code is writting in a kind of context neutral way. Time will show whether
* this actually makes sense or not...
*
* context ends up using a global mapping cache on some platforms
* (darwin).
*
* @{ */
/** @typedef PPGMPAGEMAPTLB
* The page mapper TLB pointer type for the current context. */
/** @typedef PPGMPAGEMAPTLB
* The page mapper TLB entry pointer type for the current context. */
/** @typedef PPGMPAGEMAPTLB
* The page mapper TLB entry pointer pointer type for the current context. */
/** @def PGM_PAGEMAPTLB_ENTRIES
* The number of TLB entries in the page mapper TLB for the current context. */
/** @def PGM_PAGEMAPTLB_IDX
* Calculate the TLB index for a guest physical address.
* @returns The TLB index.
* @param GCPhys The guest physical address. */
/** @typedef PPGMPAGEMAP
* Pointer to a page mapper unit for current context. */
/** @typedef PPPGMPAGEMAP
* Pointer to a page mapper unit pointer for current context. */
#ifdef IN_RC
// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
typedef void * PPGMPAGEMAP;
typedef void ** PPPGMPAGEMAP;
//#elif IN_RING0
// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
#else
typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
#endif
/** @} */
/** @name PGM Pool Indexes.
* Aka. the unique shadow page identifier.
* @{ */
/** NIL page pool IDX. */
#define NIL_PGMPOOL_IDX 0
/** The first normal index. */
#define PGMPOOL_IDX_FIRST_SPECIAL 1
/** Page directory (32-bit root). */
#define PGMPOOL_IDX_PD 1
/** Page Directory Pointer Table (PAE root). */
#define PGMPOOL_IDX_PDPT 2
/** AMD64 CR3 level index.*/
#define PGMPOOL_IDX_AMD64_CR3 3
/** Nested paging root.*/
#define PGMPOOL_IDX_NESTED_ROOT 4
/** The first normal index. */
#define PGMPOOL_IDX_FIRST 5
/** The last valid index. (inclusive, 14 bits) */
#define PGMPOOL_IDX_LAST 0x3fff
/** @} */
/** The NIL index for the parent chain. */
/**
* Node in the chain linking a shadowed page to it's parent (user).
*/
#pragma pack(1)
typedef struct PGMPOOLUSER
{
/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
/** The user page index. */
/** Index into the user table. */
} PGMPOOLUSER, *PPGMPOOLUSER;
typedef const PGMPOOLUSER *PCPGMPOOLUSER;
#pragma pack()
/** The NIL index for the phys ext chain. */
/** The NIL pte index for a phys ext chain slot. */
/**
* Node in the chain of physical cross reference extents.
* @todo Calling this an 'extent' is not quite right, find a better name.
* @todo find out the optimal size of the aidx array
*/
#pragma pack(1)
typedef struct PGMPOOLPHYSEXT
{
/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
/** Alignment. */
/** The user page index. */
/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
#pragma pack()
/**
* The kind of page that's being shadowed.
*/
typedef enum PGMPOOLKIND
{
/** The virtual invalid 0 entry. */
PGMPOOLKIND_INVALID = 0,
/** The entry is free (=unused). */
/** Shw: 32-bit page table; Gst: no paging */
/** Shw: 32-bit page table; Gst: 32-bit page table. */
/** Shw: 32-bit page table; Gst: 4MB page. */
/** Shw: PAE page table; Gst: no paging */
/** Shw: PAE page table; Gst: 32-bit page table. */
/** Shw: PAE page table; Gst: Half of a 4MB page. */
/** Shw: PAE page table; Gst: PAE page table. */
/** Shw: PAE page table; Gst: 2MB page. */
/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
/** Shw: 32-bit page directory. Gst: no paging. */
/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
/** Shw: PAE page directory; Gst: PAE page directory. */
/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
/** Shw: 64-bit page directory pointer table; Gst: no paging */
/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
/** Shw: 64-bit page directory table; Gst: no paging */
PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
/** Shw: EPT page directory pointer table; Gst: no paging */
/** Shw: EPT page directory table; Gst: no paging */
/** Shw: EPT page table; Gst: no paging */
/** Shw: Root Nested paging table. */
/** The last valid entry. */
} PGMPOOLKIND;
/**
* The access attributes of the page; only applies to big pages.
*/
typedef enum
{
/**
* The tracking data for a page in the pool.
*/
typedef struct PGMPOOLPAGE
{
/** AVL node code with the (R3) physical address of this page. */
/** Pointer to the R3 mapping of the page. */
#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
#else
R3R0PTRTYPE(void *) pvPageR3;
#endif
/** The guest physical address. */
#endif
/** Access handler statistics to determine whether the guest is (re)initializing a page table. */
/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
/** The index of this page. */
/** The next entry in the list this page currently resides in.
* It's either in the free list or in the GCPhys hash. */
/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
/** The number of present entries. */
/** The first entry in the table which is present. */
/** The number of modifications to the monitored page. */
/** The next modified page. NIL_PGMPOOL_IDX if tail. */
/** The previous modified page. NIL_PGMPOOL_IDX if head. */
/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
/** The next page in the age list. */
/** The previous page in the age list. */
/** Used to indicate that the page is zeroed. */
bool fZeroed;
/** Used to indicate that a PT has non-global entries. */
bool fSeenNonGlobal;
/** Used to indicate that we're monitoring writes to the guest page. */
bool fMonitored;
/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
* (All pages are in the age list.) */
bool fCached;
/** This is used by the R3 access handlers when invoked by an async thread.
* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
bool volatile fReusedFlushPending;
/** Used to mark the page as dirty (write monitoring is temporarily
* off). */
bool fDirty;
/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
/** Pointer to a const pool page. */
typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
/** The hash table size. */
# define PGMPOOL_HASH_SIZE 0x40
/** The hash function. */
/**
* The shadow page pool instance data.
*
* It's all one big allocation made at init time, except for the
* pages that is. The user nodes follows immediately after the
* page structures.
*/
typedef struct PGMPOOL
{
/** The VM handle - R3 Ptr. */
/** The VM handle - R0 Ptr. */
/** The VM handle - RC Ptr. */
/** The max pool size. This includes the special IDs. */
/** The current pool size. */
/** The head of the free page list. */
/* Padding. */
/** Head of the chain of free user nodes. */
/** The number of user nodes we've allocated. */
/** The number of present page table entries in the entire pool. */
/** Pointer to the array of user nodes - RC pointer. */
/** Pointer to the array of user nodes - R3 pointer. */
/** Pointer to the array of user nodes - R0 pointer. */
/** Head of the chain of free phys ext nodes. */
/** The number of user nodes we've allocated. */
/** Pointer to the array of physical xref extent - RC pointer. */
/** Pointer to the array of physical xref extent nodes - R3 pointer. */
/** Pointer to the array of physical xref extent nodes - R0 pointer. */
/** Hash table for GCPhys addresses. */
/** The head of the age list. */
/** The tail of the age list. */
/** Set if the cache is enabled. */
bool fCacheEnabled;
/** Alignment padding. */
bool afPadding1[3];
/** Head of the list of modified pages. */
/** The current number of modified pages. */
/** Access handler, RC. */
/** Access handler, R0. */
/** Access handler, R3. */
/** The access handler description (R3 ptr). */
R3PTRTYPE(const char *) pszAccessHandler;
# if HC_ARCH_BITS == 32
/** Alignment padding. */
# endif
/* Next available slot. */
/* Number of active dirty pages. */
/* Array of current dirty pgm pool page indices. */
struct
{
} aDirtyPages[16];
/** The number of pages currently in use. */
#ifdef VBOX_WITH_STATISTICS
/** The high water mark for cUsedPages. */
/** Profiling pgmPoolAlloc(). */
/** Profiling pgmR3PoolClearDoIt(). */
/** Profiling pgmR3PoolReset(). */
/** Profiling pgmPoolFlushPage(). */
/** Profiling pgmPoolFree(). */
/** Counting explicit flushes by PGMPoolFlushPage(). */
/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
/** Counting flushes for reused pages. */
/** Profiling time spent zeroing pages. */
/** Profiling of pgmPoolTrackDeref. */
/** Profiling pgmTrackFlushGCPhysPT. */
/** Profiling pgmTrackFlushGCPhysPTs. */
/** Profiling pgmTrackFlushGCPhysPTsSlow. */
/** Number of times we've been out of user records. */
/** Nr of flushed entries. */
/** Nr of updated entries. */
/** Profiling deref activity related tracking GC physical pages. */
/** Number of linear searches for a HCPhys in the ram ranges. */
/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
/** Times we've failed interpreting the instruction. */
/* Times we've detected a page table reinit. */
/** Counting flushes for pages that are modified too often. */
/** Times we've detected fork(). */
/** Times we've failed interpreting a patch code instruction. */
/** Times we've failed interpreting a patch code instruction during flushing. */
/** The number of times we've seen rep prefixes we can't handle. */
/** Profiling the REP STOSD cases we've handled. */
/** Nr of handled PT faults. */
/** Nr of handled PD faults. */
/** Nr of handled PDPT faults. */
/** Nr of handled PML4 faults. */
/** Profiling the R3 access handler. */
/** Times we've failed interpreting the instruction. */
/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
/* Times we've detected a page table reinit. */
/** Counting flushes for pages that are modified too often. */
/** Times we've detected fork(). */
/** Profiling the R3 access we've handled (except REP STOSD). */
/** The number of times we've seen rep prefixes we can't handle. */
/** Profiling the REP STOSD cases we've handled. */
/** Nr of handled PT faults. */
/** Nr of handled PD faults. */
/** Nr of handled PDPT faults. */
/** Nr of handled PML4 faults. */
/** The number of times we're called in an async thread an need to flush. */
/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
/** Times we've called pgmPoolAddDirtyPage. */
/** Times we've had to flush duplicates for dirty page management. */
/** Times we've had to flush because of overflow. */
/** The high water mark for cModifiedPages. */
/** The number of cache hits. */
/** The number of cache misses. */
/** The number of times we've got a conflict of 'kind' in the cache. */
/** Number of times we've been out of pages. */
/** The number of cacheable allocations. */
/** The number of uncacheable allocations. */
#else
#endif
/** The AVL tree for looking up a page by its HC physical address. */
/** Array of pages. (cMaxPages in length)
* The Id is the index into thist array.
*/
#ifdef VBOX_WITH_STATISTICS
#endif
/** @def PGMPOOL_PAGE_2_PTR
* Maps a pool page pool into the current context.
*
* @returns VBox status code.
* @param a_pVM The VM handle.
* @param a_pPage The pool page.
*
* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
* small page window employeed by that function. Be careful.
* @remark There is no need to assert on the result.
*/
#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
#elif defined(VBOX_STRICT)
{
}
#else
#endif
/** @def PGMPOOL_PAGE_2_PTR_V2
* Maps a pool page pool into the current context, taking both VM and VMCPU.
*
* @returns VBox status code.
* @param a_pVM The VM handle.
* @param a_pVCpu The current CPU.
* @param a_pPage The pool page.
*
* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
* small page window employeed by that function. Be careful.
* @remark There is no need to assert on the result.
*/
#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
#else
#endif
/** @name Per guest page tracking data.
* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
* is to use more bits for it and split it up later on. But for now we'll play
* safe and change as little as possible.
*
* The 16-bit word has two parts:
*
* The first 14-bit forms the @a idx field. It is either the index of a page in
* the shadow page pool, or and index into the extent list.
*
* The 2 topmost bits makes up the @a cRefs field, which counts the number of
* shadow page pool references to the page. If cRefs equals
* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
* (misnomer) table and not the shadow page pool.
*
* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
* the 16-bit word.
*
* @{ */
/** The shift count for getting to the cRefs part. */
#define PGMPOOL_TD_CREFS_SHIFT 14
/** The mask applied after shifting the tracking data down by
* PGMPOOL_TD_CREFS_SHIFT. */
#define PGMPOOL_TD_CREFS_MASK 0x3
/** The cRefs value used to indicate that the idx is the head of a
* physical cross reference list. */
/** The shift used to get idx. */
#define PGMPOOL_TD_IDX_SHIFT 0
/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
#define PGMPOOL_TD_IDX_MASK 0x3fff
* simply too many mappings of this page. */
/** @def PGMPOOL_TD_MAKE
* Makes a 16-bit tracking data word.
*
* @returns tracking data.
* @param cRefs The @a cRefs field. Must be within bounds!
* @param idx The @a idx field. Must also be within bounds! */
/** @def PGMPOOL_TD_GET_CREFS
* Get the @a cRefs field from a tracking data word.
*
* @returns The @a cRefs field
* @param u16 The tracking data word.
* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
* non-zero @a u16. */
/** @def PGMPOOL_TD_GET_IDX
* Get the @a idx field from a tracking data word.
*
* @returns The @a idx field
* @param u16 The tracking data word. */
/** @} */
/**
* Trees are using self relative offsets as pointers.
* So, all its data, including the root pointer, must be in the heap for HC and GC
* to have the same layout.
*/
typedef struct PGMTREES
{
/** Physical access handlers (AVL range+offsetptr tree). */
/** Virtual access handlers (AVL range + GC ptr tree). */
/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
} PGMTREES;
/** Pointer to PGM trees. */
/**
* Page fault guest state for the AMD64 paging mode.
*/
typedef struct PGMPTWALKCORE
{
/** The guest virtual address that is being resolved by the walk
* (input). */
/** The guest physical address that is the result of the walk.
* @remarks only valid if fSucceeded is set. */
/** Set if the walk succeeded, i.d. GCPhys is valid. */
bool fSucceeded;
/** The level problem arrised at.
* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
* level 8. This is 0 on success. */
/** Set if the page isn't present. */
bool fNotPresent;
/** Encountered a bad physical address. */
bool fBadPhysAddr;
/** Set if there was reserved bit violations. */
bool fRsvdError;
/** Set if it involves a big page (2/4 MB). */
bool fBigPage;
/** Set if it involves a gigantic page (1 GB). */
bool fGigantPage;
/** The effect X86_PTE_US flag for the address. */
bool fEffectiveUS;
/** The effect X86_PTE_RW flag for the address. */
bool fEffectiveRW;
/** The effect X86_PTE_NX flag for the address. */
bool fEffectiveNX;
/**
* Guest page table walk for the AMD64 mode.
*/
typedef struct PGMPTWALKGSTAMD64
{
/** The common core. */
/** Pointer to a AMD64 guest page table walk. */
typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
/** Pointer to a const AMD64 guest page table walk. */
typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
/**
* Guest page table walk for the PAE mode.
*/
typedef struct PGMPTWALKGSTPAE
{
/** The common core. */
/** Pointer to a PAE guest page table walk. */
typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
/** Pointer to a const AMD64 guest page table walk. */
typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
/**
* Guest page table walk for the 32-bit mode.
*/
typedef struct PGMPTWALKGST32BIT
{
/** The common core. */
/** Pointer to a 32-bit guest page table walk. */
typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
/** Pointer to a const 32-bit guest page table walk. */
typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
/** @name Paging mode macros
* @{
*/
#ifdef IN_RC
# define PGM_CTX_STR(a,b) a "GC" b
#else
# ifdef IN_RING3
# define PGM_CTX_STR(a,b) a "R3" b
# else
# define PGM_CTX_STR(a,b) a "R0" b
# endif
#endif
/* Shw_Gst */
/** @} */
/**
* Data for each paging mode.
*/
typedef struct PGMMODEDATA
{
/** The guest mode type. */
/** The shadow mode type. */
/** @name Function pointers for Shadow paging.
* @{
*/
DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
/** @} */
/** @name Function pointers for Guest paging.
* @{
*/
DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
/** @} */
/** @name Function pointers for Both Shadow and Guest paging.
* @{
*/
/* no pfnR3BthTrap0eHandler */
DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
#ifdef VBOX_STRICT
DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
#endif
DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
#ifdef VBOX_STRICT
DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
#endif
DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
#ifdef VBOX_STRICT
DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
#endif
/** @} */
} PGMMODEDATA, *PPGMMODEDATA;
#ifdef VBOX_WITH_STATISTICS
/**
* PGM statistics.
*
* These lives on the heap when compiled in as they would otherwise waste
* unnecessary space in release builds.
*/
typedef struct PGMSTATS
{
/* R3 only: */
STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
/* R3+RZ */
STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
/* RC only: */
STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
/** Time spent by the host OS for large page allocation. */
/** Time spent clearing the newly allocated large pages. */
/** The number of times allocating a large pages takes more than the allowed period. */
/** pgmPhysIsValidLargePage profiling - R3 */
/** pgmPhysIsValidLargePage profiling - RZ*/
} PGMSTATS;
#endif /* VBOX_WITH_STATISTICS */
/**
* Converts a PGM pointer into a VM pointer.
* @returns Pointer to the VM structure the PGM is part of.
* @param pPGM Pointer to PGM instance data.
*/
/**
* PGM Data (part of VM)
*/
typedef struct PGM
{
/** Offset to the VM structure. */
/** Offset of the PGMCPU structure relative to VMCPU. */
/** @cfgm{RamPreAlloc, boolean, false}
* Indicates whether the base RAM should all be allocated before starting
* the VM (default), or if it should be allocated when first written to.
*/
bool fRamPreAlloc;
/** Indicates whether write monitoring is currently in use.
* This is used to prevent conflicts between live saving and page sharing
* detection. */
/** Set if the CPU has less than 52-bit physical address width.
* This is used */
/** Set when nested paging is active.
* This is meant to save calls to HWACCMIsNestedPagingActive and let the
* compilers optimize the code better. Whether we use nested paging or
* not is something we find out during VMM initialization and we won't
* change this later on. */
bool fNestedPaging;
/** The host paging mode. (This is what SUPLib reports.) */
/** We're not in a state which permits writes to guest memory.
* (Only used in strict builds.) */
bool fNoMorePhysWrites;
/** Set if PCI passthrough is enabled. */
bool fPciPassthrough;
/** Alignment padding that makes the next member start on a 8 byte boundary. */
bool afAlignment1[2];
/** Indicates that PGMR3FinalizeMappings has been called and that further
* PGMR3MapIntermediate calls will be rejected. */
bool fFinalizedMappings;
/** If set no conflict checks are required. */
bool fMappingsFixed;
/** If set if restored as fixed but we were unable to re-fixate at the old
* location because of room or address incompatibilities. */
bool fMappingsFixedRestored;
/** If set, then no mappings are put into the shadow page table.
* Use pgmMapAreMappingsEnabled() instead of direct access. */
bool fMappingsDisabled;
/** Size of fixed mapping.
* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
/** Generation ID for the RAM ranges. This member is incremented everytime
* a RAM range is linked or unlinked. */
uint32_t volatile idRamRangesGen;
/** Base address (GC) of fixed mapping.
* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
/** The address of the previous RAM range mapping. */
/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
/** Mask containing the invalid bits of a guest physical address.
* @remarks this does not stop at bit 52. */
/** RAM range TLB for R3. */
/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
* This is sorted by physical address and contains no overlapping ranges. */
/** Root of the RAM range search tree for ring-3. */
/** PGM offset based trees - R3 Ptr. */
/** Caching the last physical handler we looked up in R3. */
/** Shadow Page Pool - R3 Ptr. */
/** Linked list of GC mappings - for HC.
* The list is sorted ascending on address. */
/** Pointer to the list of ROM ranges - for R3.
* This is sorted by physical address and contains no overlapping ranges. */
/** Pointer to the list of MMIO2 ranges - for R3.
* Registration order. */
/** Pointer to SHW+GST mode data (function pointers).
* The index into this table is made up from */
/** RAM range TLB for R0. */
/** R0 pointer corresponding to PGM::pRamRangesXR3. */
/** Root of the RAM range search tree for ring-0. */
/** PGM offset based trees - R0 Ptr. */
/** Caching the last physical handler we looked up in R0. */
/** Shadow Page Pool - R0 Ptr. */
/** Linked list of GC mappings - for R0.
* The list is sorted ascending on address. */
/** R0 pointer corresponding to PGM::pRomRangesR3. */
/** RAM range TLB for RC. */
/** RC pointer corresponding to PGM::pRamRangesXR3. */
/** Root of the RAM range search tree for raw-mode context. */
/** PGM offset based trees - RC Ptr. */
/** Caching the last physical handler we looked up in RC. */
/** Shadow Page Pool - RC Ptr. */
/** Linked list of GC mappings - for RC.
* The list is sorted ascending on address. */
/** RC pointer corresponding to PGM::pRomRangesR3. */
/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
/** Pointer to the 5 page CR3 content mapping.
* The first page is always the CR3 (in some form) while the 4 other pages
* are used of the PDs in PAE mode. */
/** @name Intermediate Context
* @{ */
/** Pointer to the intermediate page directory - Normal. */
/** Pointer to the intermediate page tables - Normal.
* There are two page tables, one for the identity mapping and one for
* the host context mapping (of the core code). */
/** Pointer to the intermediate page tables - PAE. */
/** Pointer to the intermediate page directory - PAE. */
/** Pointer to the intermediate page directory - PAE. */
/** Pointer to the intermediate page-map level 4 - AMD64. */
/** Pointer to the intermediate page directory - AMD64. */
/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
/** @} */
/** Base address of the dynamic page mapping area.
* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
*
* @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
* work out. Some cleaning up of the initialization that would
* remove this memory is yet to be done...
*/
/** The address of the raw-mode context mapping cache. */
/** The address of the ring-0 mapping cache if we're making use of it. */
/** Hack: Number of deprecated page mapping locks taken by the current lock
* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
#if HC_ARCH_BITS == 64
/** Alignment padding. */
#endif
/** PGM critical section.
* This protects the physical & virtual access handlers, ram ranges,
* and the page flag updating (some of it anyway).
*/
/**
* Data associated with managing the ring-3 mappings of the allocation chunks.
*/
struct
{
/** The chunk tree, ordered by chunk id. */
#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
#else
#endif
#if HC_ARCH_BITS == 32
#endif
/** The chunk mapping TLB. */
/** The number of mapped chunks. */
uint32_t c;
/** The maximum number of mapped chunks.
* @cfgm PGM/MaxRing3Chunks */
/** The current time. This is incremented whenever a chunk is inserted. */
/** Alignment padding. */
} ChunkR3Map;
/**
* The page mapping TLB for ring-3 and (for the time being) ring-0.
*/
/** @name The zero page.
* @{ */
/** The host physical address of the zero page. */
/** The ring-3 mapping of the zero page. */
/** The ring-0 mapping of the zero page. */
/** The GC mapping of the zero page. */
/** @}*/
/** @name The Invalid MMIO page.
* This page is filled with 0xfeedface.
* @{ */
/** The host physical address of the invalid MMIO page. */
/** The host pysical address of the invalid MMIO page plus all invalid
* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
* @remarks Check fLessThan52PhysicalAddressBits before use. */
/** The ring-3 mapping of the invalid MMIO page. */
#if HC_ARCH_BITS == 32
#endif
/** @} */
/** The number of handy pages. */
/** The number of large handy pages. */
/**
* Array of handy pages.
*
* This array is used in a two way communication between pgmPhysAllocPage
* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
* an intermediary.
*
* The size of this array is important, see pgmPhysEnsureHandyPage for details.
* (The current size of 32 pages, means 128 KB of handy memory.)
*/
/**
* Array of large handy pages. (currently size 1)
*
* This array is used in a two way communication between pgmPhysAllocLargePage
* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
* an intermediary.
*/
/**
* Live save data.
*/
struct
{
/** Per type statistics. */
struct
{
/** The number of ready pages. */
/** The number of dirty pages. */
/** The number of ready zero pages. */
/** The number of write monitored pages. */
} Rom,
Ram;
/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
/** Indicates that a live save operation is active. */
bool fActive;
/** Padding. */
bool afReserved[2];
/** The next history index. */
/** History of the total amount of dirty pages. */
/** Short term dirty page average. */
/** Long term dirty page average. */
/** The number of saved pages. This is used to get some kind of estimate of the
* link speed so we can decide when we're done. It is reset after the first
* 7 passes so the speed estimate doesn't get inflated by the initial set of
* zero pages. */
/** The nanosecond timestamp when cSavedPages was 0. */
/** Pages per second (for statistics). */
} LiveSave;
/** @name Error injection.
* @{ */
/** Inject handy page allocation errors pretending we're completely out of
* memory. */
bool volatile fErrInjHandyPages;
/** Padding. */
bool afReserved[3];
/** @} */
/** @name Release Statistics
* @{ */
uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
/* uint32_t aAlignment4[1]; */
/** The number of times we were forced to change the hypervisor region location. */
/** @} */
#ifdef VBOX_WITH_STATISTICS
/** @name Statistics on the heap.
* @{ */
/** @} */
#endif
} PGM;
#ifndef IN_TSTVMSTRUCTGC /* HACK */
#endif /* !IN_TSTVMSTRUCTGC */
/** Pointer to the PGM instance data. */
typedef struct PGMCPUSTATS
{
/* Common */
/* R0 only: */
STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
/* RZ only: */
STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
//STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
/* HC - R3 and (maybe) R0: */
/* RZ & R3: */
STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
/** @} */
} PGMCPUSTATS;
/**
* Converts a PGMCPU pointer into a VM pointer.
* @returns Pointer to the VM structure the PGM is part of.
* @param pPGM Pointer to PGMCPU instance data.
*/
/**
* Converts a PGMCPU pointer into a PGM pointer.
* @returns Pointer to the VM structure the PGM is part of.
* @param pPGM Pointer to PGMCPU instance data.
*/
/**
* PGMCPU Data (part of VMCPU).
*/
typedef struct PGMCPU
{
/** Offset to the VM structure. */
/** Offset to the VMCPU structure. */
/** Offset of the PGM structure relative to VMCPU. */
#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
/** Automatically tracked physical memory mapping set.
* Ring-0 and strict raw-mode builds. */
#endif
/** A20 gate mask.
* Our current approach to A20 emulation is to let REM do it and don't bother
* anywhere else. The interesting Guests will be operating with it enabled anyway.
* But whould need arrise, we'll subject physical addresses to this mask. */
/** A20 gate state - boolean! */
bool fA20Enabled;
/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
bool fNoExecuteEnabled;
/** Unused bits. */
bool afUnused[2];
/** What needs syncing (PGM_SYNC_*).
* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
* PGMFlushTLB, and PGMR3Load. */
/** The shadow paging mode. */
/** The guest paging mode. */
/** The current physical address representing in the guest CR3 register. */
/** @name 32-bit Guest Paging.
* @{ */
/** The guest's page directory, R3 pointer. */
#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
/** The guest's page directory, R0 pointer. */
#endif
/** The guest's page directory, static RC mapping. */
/** Mask containing the MBZ bits of a big page PDE. */
/** Set if the page size extension (PSE) is enabled. */
/** Alignment padding. */
bool afAlignment2[3];
/** @} */
/** @name PAE Guest Paging.
* @{ */
/** The guest's page directory pointer table, static RC mapping. */
/** The guest's page directory pointer table, R3 pointer. */
#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
/** The guest's page directory pointer table, R0 pointer. */
#endif
/** The guest's page directories, R3 pointers.
* These are individual pointers and don't have to be adjacent.
* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
/** The guest's page directories, R0 pointers.
* Same restrictions as apGstPaePDsR3. */
#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
#endif
/** The guest's page directories, static GC mapping.
* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
* @todo Remove this and use aGstPaePdpeRegs instead? */
/** The values of the 4 PDPE CPU registers (PAE). */
/** The physical addresses of the monitored guest page directories (PAE). */
/** Mask containing the MBZ PTE bits. */
/** Mask containing the MBZ PDE bits. */
/** Mask containing the MBZ big page PDE bits. */
/** Mask containing the MBZ PDPE bits. */
/** @} */
/** @name AMD64 Guest Paging.
* @{ */
/** The guest's page directory pointer table, R3 pointer. */
#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
/** The guest's page directory pointer table, R0 pointer. */
#else
#endif
/** Mask containing the MBZ PTE bits. */
/** Mask containing the MBZ PDE bits. */
/** Mask containing the MBZ big page PDE bits. */
/** Mask containing the MBZ PDPE bits. */
/** Mask containing the MBZ big page PDPE bits. */
/** Mask containing the MBZ PML4E bits. */
/** Mask containing the PDPE bits that we shadow. */
/** Mask containing the PML4E bits that we shadow. */
/** @} */
/** @name PAE and AMD64 Guest Paging.
* @{ */
/** Mask containing the PTE bits that we shadow. */
/** Mask containing the PDE bits that we shadow. */
/** Mask containing the big page PDE bits that we shadow in the PDE. */
/** Mask containing the big page PDE bits that we shadow in the PTE. */
/** @} */
/** Pointer to the page of the current active CR3 - R3 Ptr. */
/** Pointer to the page of the current active CR3 - R0 Ptr. */
/** Pointer to the page of the current active CR3 - RC Ptr. */
/* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
/* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
# if HC_ARCH_BITS == 64
# endif
/** @} */
/** @name Function pointers for Shadow paging.
* @{
*/
DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
/** @} */
/** @name Function pointers for Guest paging.
* @{
*/
DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
#if HC_ARCH_BITS == 64
#endif
DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
/** @} */
/** @name Function pointers for Both Shadow and Guest paging.
* @{
*/
/* no pfnR3BthTrap0eHandler */
DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
#if 0
#endif
/** @} */
/** For saving stack space, the disassembler state is allocated here instead of
* on the stack.
union
{
/** The disassembler scratch space. */
/** Padding. */
};
/** Count the number of pgm pool access handler calls. */
/** @name Release Statistics
* @{ */
/** The number of times the guest has switched mode since last reset or statistics reset. */
/** @} */
#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
/** @name Statistics
* @{ */
/** RC: Pointer to the statistics. */
/** RC: Which statistic this \#PF should be attributed to. */
/** R0: Pointer to the statistics. */
/** R0: Which statistic this \#PF should be attributed to. */
/** R3: Pointer to the statistics. */
/** Alignment padding. */
/** @} */
#endif /* VBOX_WITH_STATISTICS */
} PGMCPU;
/** Pointer to the per-cpu PGM data. */
/** @name PGM::fSyncFlags Flags
* @{
*/
/** Updates the virtual access handler state bit in PGMPAGE. */
#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
/** Always sync CR3. */
/** Check monitoring on next CR3 (re)load and invalidate page.
* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
/** Check guest mapping in SyncCR3. */
/** Clear the page pool (a light weight flush). */
#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
/** @} */
/**
* Asserts that the caller owns the PDM lock.
* This is the internal variant of PGMIsLockOwner.
* @param a_pVM The VM handle.
*/
/**
* Asserts that the caller owns the PDM lock.
* This is the internal variant of PGMIsLockOwner.
* @param a_pVM The VM handle.
* @param a_pVCpu The current CPU handle.
*/
#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, pVCpu))
int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
#else
# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
#endif
int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
#ifdef IN_RING3
DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
#endif /* IN_RING3 */
#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
# ifdef LOG_ENABLED
# else
# endif
#endif
int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser,
DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable,
{
return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, false, ppPage);
}
int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
# endif
/** @} */
#endif