CPUMR3CpuId.cpp revision f5906f8fb3e7988cbedcbb78fc7170b9b57bf026
/* $Id$ */
/** @file
* CPUM - CPU ID part.
*/
/*
* Copyright (C) 2013-2015 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_CPUM
#include "CPUMInternal.h"
#include <iprt/asm-amd64-x86.h>
/*******************************************************************************
* Global Variables *
*******************************************************************************/
/**
* The intel pentium family.
*/
static const CPUMMICROARCH g_aenmIntelFamily06[] =
{
/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
/* [31(0x1f)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
/* [45(0x2d)] = */ kCpumMicroarch_Intel_Core7_SandyBridge, /* SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
/* [71(0x47)] = */ kCpumMicroarch_Intel_Unknown,
/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
/* [76(0x4c)] = */ kCpumMicroarch_Intel_Unknown,
/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
/* [78(0x4e)] = */ kCpumMicroarch_Intel_Unknown,
/* [79(0x4f)] = */ kCpumMicroarch_Intel_Unknown,
};
/**
* Figures out the (sub-)micro architecture given a bit of CPUID info.
*
* @returns Micro architecture.
* @param enmVendor The CPU vendor .
* @param bFamily The CPU family.
* @param bModel The CPU model.
* @param bStepping The CPU stepping.
*/
{
if (enmVendor == CPUMCPUVENDOR_AMD)
{
switch (bFamily)
{
case 0x03: return kCpumMicroarch_AMD_Am386;
case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
case 0x06:
switch (bModel)
{
case 0: kCpumMicroarch_AMD_K7_Palomino;
case 1: kCpumMicroarch_AMD_K7_Palomino;
case 2: kCpumMicroarch_AMD_K7_Palomino;
case 3: kCpumMicroarch_AMD_K7_Spitfire;
case 4: kCpumMicroarch_AMD_K7_Thunderbird;
case 6: kCpumMicroarch_AMD_K7_Palomino;
case 7: kCpumMicroarch_AMD_K7_Morgan;
case 8: kCpumMicroarch_AMD_K7_Thoroughbred;
}
return kCpumMicroarch_AMD_K7_Unknown;
case 0x0f:
/*
* This family is a friggin mess. Trying my best to make some
* sense out of it. Too much happened in the 0x0f family to
* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
*
* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
* cpu-world.com, and other places:
* - 130nm:
* - 90nm:
* - 90nm introducing Dual core:
* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
*
* - 65nm:
*/
if (bModel < 0x10)
return kCpumMicroarch_AMD_K8_130nm;
return kCpumMicroarch_AMD_K8_65nm;
if (bModel >= 0x40)
return kCpumMicroarch_AMD_K8_90nm_AMDV;
switch (bModel)
{
case 0x21:
case 0x23:
case 0x2b:
case 0x2f:
case 0x37:
case 0x3f:
}
return kCpumMicroarch_AMD_K8_90nm;
case 0x10:
return kCpumMicroarch_AMD_K10;
case 0x11:
return kCpumMicroarch_AMD_K10_Lion;
case 0x12:
return kCpumMicroarch_AMD_K10_Llano;
case 0x14:
return kCpumMicroarch_AMD_Bobcat;
case 0x15:
switch (bModel)
{
case 0x11: /* ?? */
case 0x12: /* ?? */
}
return kCpumMicroarch_AMD_15h_Unknown;
case 0x16:
return kCpumMicroarch_AMD_Jaguar;
}
return kCpumMicroarch_AMD_Unknown;
}
if (enmVendor == CPUMCPUVENDOR_INTEL)
{
switch (bFamily)
{
case 3:
return kCpumMicroarch_Intel_80386;
case 4:
return kCpumMicroarch_Intel_80486;
case 5:
return kCpumMicroarch_Intel_P5;
case 6:
return g_aenmIntelFamily06[bModel];
case 15:
switch (bModel)
{
case 0: return kCpumMicroarch_Intel_NB_Willamette;
case 1: return kCpumMicroarch_Intel_NB_Willamette;
case 2: return kCpumMicroarch_Intel_NB_Northwood;
case 3: return kCpumMicroarch_Intel_NB_Prescott;
case 6: return kCpumMicroarch_Intel_NB_CedarMill;
case 7: return kCpumMicroarch_Intel_NB_Gallatin;
default: return kCpumMicroarch_Intel_NB_Unknown;
}
break;
/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
case 1:
return kCpumMicroarch_Intel_8086;
case 2:
return kCpumMicroarch_Intel_80286;
}
return kCpumMicroarch_Intel_Unknown;
}
if (enmVendor == CPUMCPUVENDOR_VIA)
{
switch (bFamily)
{
case 5:
switch (bModel)
{
case 1: return kCpumMicroarch_Centaur_C6;
case 4: return kCpumMicroarch_Centaur_C6;
case 8: return kCpumMicroarch_Centaur_C2;
case 9: return kCpumMicroarch_Centaur_C3;
}
break;
case 6:
switch (bModel)
{
case 5: return kCpumMicroarch_VIA_C3_M2;
case 6: return kCpumMicroarch_VIA_C3_C5A;
case 8: return kCpumMicroarch_VIA_C3_C5N;
case 10: return kCpumMicroarch_VIA_C7_C5J;
case 15: return kCpumMicroarch_VIA_Isaiah;
}
break;
}
return kCpumMicroarch_VIA_Unknown;
}
if (enmVendor == CPUMCPUVENDOR_CYRIX)
{
switch (bFamily)
{
case 4:
switch (bModel)
{
case 9: return kCpumMicroarch_Cyrix_5x86;
}
break;
case 5:
switch (bModel)
{
case 2: return kCpumMicroarch_Cyrix_M1;
case 4: return kCpumMicroarch_Cyrix_MediaGX;
case 5: return kCpumMicroarch_Cyrix_MediaGXm;
}
break;
case 6:
switch (bModel)
{
case 0: return kCpumMicroarch_Cyrix_M2;
}
break;
}
return kCpumMicroarch_Cyrix_Unknown;
}
return kCpumMicroarch_Unknown;
}
/**
* Translates a microarchitecture enum value to the corresponding string
* constant.
*
* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
* NULL if the value is invalid.
*
* @param enmMicroarch The enum value to convert.
*/
{
switch (enmMicroarch)
{
case kCpumMicroarch_Invalid:
case kCpumMicroarch_Intel_End:
case kCpumMicroarch_AMD_End:
case kCpumMicroarch_VIA_End:
case kCpumMicroarch_Cyrix_End:
case kCpumMicroarch_32BitHack:
break;
/* no default! */
}
return NULL;
}
/**
* Gets a matching leaf in the CPUID leaf array.
*
* @returns Pointer to the matching leaf, or NULL if not found.
* @param paLeaves The CPUID leaves to search. This is sorted.
* @param cLeaves The number of leaves in the array.
* @param uLeaf The leaf to locate.
* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
*/
PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
{
/* Lazy bird does linear lookup here since this is only used for the
occational CPUID overrides. */
return &paLeaves[i];
return NULL;
}
/**
* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
*
* @returns true if found, false it not.
* @param paLeaves The CPUID leaves to search. This is sorted.
* @param cLeaves The number of leaves in the array.
* @param uLeaf The leaf to locate.
* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
* @param pLegacy The legacy output leaf.
*/
bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf, PCPUMCPUID pLegacy)
{
if (pLeaf)
{
return true;
}
return false;
}
/**
* Ensures that the CPUID leaf array can hold one more leaf.
*
* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
* failure.
* @param pVM Pointer to the VM, used as the heap selector. Passing
* NULL uses the host-context heap, otherwise the VM's
* hyper heap is used.
* @param ppaLeaves Pointer to the variable holding the array pointer
* @param cLeaves The current array size.
*
* @remarks This function will automatically update the R0 and RC pointers when
* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
* be the corresponding VM's CPUID arrays (which is asserted).
*/
{
if (!pVM)
else
{
/*
* We're using the hyper heap now, but when the arrays were copied over to it from
* the host-context heap, we only copy the exact size and not the ensured size.
* See @bugref{7270}.
*/
}
{
void *pvNew;
#ifndef IN_VBOX_CPU_REPORT
if (pVM)
{
if (RT_FAILURE(rc))
{
return NULL;
}
}
else
#endif
{
if (!pvNew)
{
return NULL;
}
}
}
#ifndef IN_VBOX_CPU_REPORT
/* Update the R0 and RC pointers. */
if (pVM)
{
}
#endif
return *ppaLeaves;
}
/**
* Append a CPUID leaf or sub-leaf.
*
* ASSUMES linear insertion order, so we'll won't need to do any searching or
* replace anything. Use cpumR3CpuIdInsert() for those cases.
*
* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
* the caller need do no more work.
* @param ppaLeaves Pointer to the the pointer to the array of sorted
* CPUID leaves and sub-leaves.
* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
* @param uLeaf The leaf we're adding.
* @param uSubLeaf The sub-leaf number.
* @param fSubLeafMask The sub-leaf mask.
* @param uEax The EAX value.
* @param uEbx The EBX value.
* @param uEcx The ECX value.
* @param uEdx The EDX value.
* @param fFlags The flags.
*/
{
return VERR_NO_MEMORY;
*pcLeaves += 1;
return VINF_SUCCESS;
}
/**
* Inserts a CPU ID leaf, replacing any existing ones.
*
* When inserting a simple leaf where we already got a series of subleaves with
* the same leaf number (eax), the simple leaf will replace the whole series.
*
* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
* host-context heap and has only been allocated/reallocated by the
* cpumR3CpuIdEnsureSpace function.
*
* @returns VBox status code.
* @param pVM Pointer to the VM, used as the heap selector.
* Passing NULL uses the host-context heap, otherwise
* the VM's hyper heap is used.
* @param ppaLeaves Pointer to the the pointer to the array of sorted
* CPUID leaves and sub-leaves. Must be NULL if using
* the hyper heap.
* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must be
* NULL if using the hyper heap.
* @param pNewLeaf Pointer to the data of the new leaf we're about to
* insert.
*/
int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
{
/*
* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
*/
if (pVM)
{
}
/*
* Validate the new leaf a little.
*/
AssertReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf, VERR_INVALID_PARAMETER);
/*
* Find insertion point. The lazy bird uses the same excuse as in
* cpumR3CpuIdGetLeaf().
*/
uint32_t i = 0;
while ( i < cLeaves
i++;
if ( i < cLeaves
{
{
/*
* The subleaf mask differs, replace all existing leaves with the
* same leaf number.
*/
uint32_t c = 1;
while ( i + c < cLeaves
c++;
if (c > 1 && i + c < cLeaves)
{
}
return VINF_SUCCESS;
}
/* Find subleaf insertion point. */
while ( i < cLeaves
i++;
/*
* If we've got an exactly matching leaf, replace it.
*/
{
return VINF_SUCCESS;
}
}
/*
* Adding a new leaf at 'i'.
*/
if (!paLeaves)
return VERR_NO_MEMORY;
if (i < cLeaves)
*pcLeaves += 1;
return VINF_SUCCESS;
}
/**
* Removes a range of CPUID leaves.
*
* This will not reallocate the array.
*
* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
* @param pcLeaves Where we keep the leaf count for @a paLeaves.
* @param uFirst The first leaf.
* @param uLast The last leaf.
*/
void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
{
/*
* Find the first one.
*/
iFirst++;
/*
* Find the end (last + 1).
*/
iEnd++;
/*
* Adjust the array if anything needs removing.
*/
{
}
}
/**
* Checks if ECX make a difference when reading a given CPUID leaf.
*
* @returns @c true if it does, @c false if it doesn't.
* @param uLeaf The leaf we're reading.
* @param pcSubLeaves Number of sub-leaves accessible via ECX.
* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
* final sub-leaf.
*/
static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t *pcSubLeaves, bool *pfFinalEcxUnchanged)
{
*pfFinalEcxUnchanged = false;
/* Look for sub-leaves. */
for (;;)
{
break;
/* Advance / give up. */
uSubLeaf++;
if (uSubLeaf >= 64)
{
*pcSubLeaves = 1;
return false;
}
}
/* Count sub-leaves. */
uSubLeaf = 0;
for (;;)
{
/* Figuring out when to stop isn't entirely straight forward as we need
to cover undocumented behavior up to a point and implementation shortcuts. */
/* 1. Look for zero values. */
if ( auCur[0] == 0
&& auCur[1] == 0
break;
/* 2. Look for more than 4 repeating value sets. */
{
cRepeats++;
if (cRepeats > 4)
break;
}
else
cRepeats = 0;
/* 3. Leaf 0xb level type 0 check. */
if ( uLeaf == 0xb
break;
/* 99. Give up. */
if (uSubLeaf >= 128)
{
#ifndef IN_VBOX_CPU_REPORT
/* Ok, limit it according to the documentation if possible just to
avoid annoying users with these detection issues. */
if (uLeaf == 0x4)
cDocLimit = 4;
else if (uLeaf == 0x7)
cDocLimit = 1;
else if (uLeaf == 0xf)
cDocLimit = 2;
if (cDocLimit != UINT32_MAX)
{
return true;
}
#endif
return true;
}
/* Advance. */
uSubLeaf++;
}
/* Standard exit. */
return true;
}
/**
* Gets a CPU ID leaf.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pLeaf Where to store the found leaf.
* @param uLeaf The leaf to locate.
* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
*/
{
PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
if (pcLeaf)
{
return VINF_SUCCESS;
}
return VERR_NOT_FOUND;
}
/**
* Inserts a CPU ID leaf, replacing any existing ones.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pNewLeaf Pointer to the leaf being inserted.
*/
{
/*
* Validate parameters.
*/
/*
* Disallow replacing CPU ID leaves that this API currently cannot manage.
* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
*/
{
return VERR_NOT_SUPPORTED;
}
}
/**
* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
*
* @returns VBox status code.
* @param ppaLeaves Where to return the array pointer on success.
* Use RTMemFree to release.
* @param pcLeaves Where to return the size of the array on
* success.
*/
{
*pcLeaves = 0;
/*
* Try out various candidates. This must be sorted!
*/
{
{ UINT32_C(0x00000000), false },
{ UINT32_C(0x10000000), false },
{ UINT32_C(0x20000000), false },
{ UINT32_C(0x30000000), false },
{ UINT32_C(0x40000000), false },
{ UINT32_C(0x50000000), false },
{ UINT32_C(0x60000000), false },
{ UINT32_C(0x70000000), false },
{ UINT32_C(0x80000000), false },
{ UINT32_C(0x80860000), false },
{ UINT32_C(0x8ffffffe), true },
{ UINT32_C(0x8fffffff), true },
{ UINT32_C(0x90000000), false },
{ UINT32_C(0xa0000000), false },
{ UINT32_C(0xb0000000), false },
{ UINT32_C(0xc0000000), false },
{ UINT32_C(0xd0000000), false },
{ UINT32_C(0xe0000000), false },
{ UINT32_C(0xf0000000), false },
};
{
/*
* Does EAX look like a typical leaf count value?
*/
{
/* Yes, dump them. */
while (cLeaves-- > 0)
{
/* Check three times here to reduce the chance of CPU migration
resulting in false positives with things like the APIC ID. */
bool fFinalEcxUnchanged;
{
if (cSubLeaves > 16)
{
/* This shouldn't happen. But in case it does, file all
relevant details in the release log. */
LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
LogRel(("------------------ dump of problematic subleaves ------------------\n"));
{
LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
}
LogRel(("----------------- dump of what we've found so far -----------------\n"));
LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
}
{
if (RT_FAILURE(rc))
return rc;
}
}
else
{
if (RT_FAILURE(rc))
return rc;
}
/* next */
uLeaf++;
}
}
/*
* Special CPUIDs needs special handling as they don't follow the
* leaf count principle used above.
*/
{
bool fKeep = false;
fKeep = true;
else if ( uLeaf == 0x8fffffff
fKeep = true;
if (fKeep)
{
if (RT_FAILURE(rc))
return rc;
}
}
}
return VINF_SUCCESS;
}
/**
* Determines the method the CPU uses to handle unknown CPUID leaves.
*
* @returns VBox status code.
* @param penmUnknownMethod Where to return the method.
* @param pDefUnknown Where to return default unknown values. This
* will be set, even if the resulting method
* doesn't actually needs it.
*/
VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
{
if (!ASMIsValidExtRange(uLastExt))
uLastExt = 0x80000000;
{
uLastStd + 1,
uLastStd + 5,
uLastStd + 8,
uLastStd + 32,
uLastStd + 251,
uLastExt + 1,
uLastExt + 8,
uLastExt + 15,
uLastExt + 63,
uLastExt + 255,
0x7fbbffcc,
0x833f7872,
0xefff2353,
0x35779456,
0x1ef6d33e,
};
static const uint32_t s_auValues[] =
{
0xa95d2156,
0x00000001,
0x00000002,
0x00000008,
0x00000000,
0x55773399,
0x93401769,
0x12039587,
};
/*
* Simple method, all zeros.
*/
pDefUnknown->uEax = 0;
pDefUnknown->uEbx = 0;
pDefUnknown->uEcx = 0;
pDefUnknown->uEdx = 0;
/*
* Intel has been observed returning the last standard leaf.
*/
while (cChecks > 0)
{
break;
cChecks--;
}
if (cChecks == 0)
{
/* Now, what happens when the input changes? Esp. ECX. */
uint32_t cLastWithEcx = 0;
while (cValues > 0)
{
while (cChecks > 0)
{
ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
{
cSame++;
cLastWithEcx++;
}
cLastWithEcx++;
else
cNeither++;
cTotal++;
cChecks--;
}
cValues--;
}
Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
else if (cLastWithEcx == cTotal)
else
return VINF_SUCCESS;
}
/*
* Unchanged register values?
*/
while (cChecks > 0)
{
while (cValues > 0)
{
break;
cValues--;
}
if (cValues != 0)
break;
cChecks--;
}
if (cChecks == 0)
{
return VINF_SUCCESS;
}
/*
* Just go with the simple method.
*/
return VINF_SUCCESS;
}
/**
* Translates a unknow CPUID leaf method into the constant name (sans prefix).
*
* @returns Read only name string.
* @param enmUnknownMethod The method to translate.
*/
{
switch (enmUnknownMethod)
{
case CPUMUKNOWNCPUID_DEFAULTS: return "DEFAULTS";
case CPUMUKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
case CPUMUKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
case CPUMUKNOWNCPUID_PASSTHRU: return "PASSTHRU";
case CPUMUKNOWNCPUID_INVALID:
case CPUMUKNOWNCPUID_END:
break;
}
return "Invalid-unknown-CPUID-method";
}
/**
* Detect the CPU vendor give n the
*
* @returns The vendor.
* @param uEAX EAX from CPUID(0).
* @param uEBX EBX from CPUID(0).
* @param uECX ECX from CPUID(0).
* @param uEDX EDX from CPUID(0).
*/
VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
{
if (ASMIsValidStdRange(uEAX))
{
return CPUMCPUVENDOR_AMD;
return CPUMCPUVENDOR_INTEL;
return CPUMCPUVENDOR_VIA;
return CPUMCPUVENDOR_CYRIX;
/* "Geode by NSC", example: family 5, model 9. */
/** @todo detect the other buggers... */
}
return CPUMCPUVENDOR_UNKNOWN;
}
/**
* Translates a CPU vendor enum value into the corresponding string constant.
*
* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
* value name. This can be useful when generating code.
*
* @returns Read only name string.
* @param enmVendor The CPU vendor value.
*/
{
switch (enmVendor)
{
case CPUMCPUVENDOR_INTEL: return "INTEL";
case CPUMCPUVENDOR_AMD: return "AMD";
case CPUMCPUVENDOR_VIA: return "VIA";
case CPUMCPUVENDOR_CYRIX: return "CYRIX";
case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
case CPUMCPUVENDOR_INVALID:
case CPUMCPUVENDOR_32BIT_HACK:
break;
}
return "Invalid-cpu-vendor";
}
static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
{
/* Could do binary search, doing linear now because I'm lazy. */
while (cLeaves-- > 0)
{
return pLeaf;
pLeaf++;
}
return NULL;
}
{
if (cLeaves >= 2)
{
pFeatures->uModel = ASMGetCpuModel(paLeaves[1].uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
if (pLeaf)
else
/* Standard features. */
if (pMWaitLeaf)
{
pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
}
/* Extended features. */
if (pExtLeaf)
{
}
if ( pExtLeaf
{
/* AMD features. */
}
/*
* Quirks.
*/
}
else
return VINF_SUCCESS;
}
/*
*
* Init related code.
* Init related code.
* Init related code.
*
*
*/
#ifdef VBOX_IN_VMM
/**
* Loads MSR range overrides.
*
* This must be called before the MSR ranges are moved from the normal heap to
* the hyper heap!
*
* @returns VBox status code (VMSetError called).
* @param pVM Pointer to the cross context VM structure
* @param pMsrNode The CFGM node with the MSR overrides.
*/
{
{
/*
* Assemble a valid MSR range.
*/
MsrRange.offCpumCpu = 0;
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
char szType[32];
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
{
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
}
else
/*
* MSR ranges).
*/
rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
&MsrRange);
if (RT_FAILURE(rc))
}
return VINF_SUCCESS;
}
/**
* Loads CPUID leaf overrides.
*
* This must be called before the CPUID leaves are moved from the normal
* heap to the hyper heap!
*
* @returns VBox status code (VMSetError called).
* @param pVM Pointer to the cross context VM structure
* @param pParentNode The CFGM node with the CPUID leaves.
* @param pszLabel How to label the overrides we're loading.
*/
{
{
/*
* Get the leaf and subleaf numbers.
*/
char szName[128];
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
/* The leaf number is either specified directly or thru the node name. */
if (rc == VERR_CFGM_VALUE_NOT_FOUND)
{
if (rc != VINF_SUCCESS)
}
else if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
/*
* Look up the specified leaf, since the output register values
* defaults to any existing values. This allows overriding a single
* register, without needing to know the other values.
*/
PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
if (pLeaf)
else
if (RT_FAILURE(rc))
if (RT_FAILURE(rc))
if (RT_FAILURE(rc))
if (RT_FAILURE(rc))
/*
* Insert the leaf into the table (replaces existing ones).
*/
rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
&Leaf);
if (RT_FAILURE(rc))
}
return VINF_SUCCESS;
}
/**
* Fetches overrides for a CPUID leaf.
*
* @returns VBox status code.
* @param pLeaf The leaf to load the overrides into.
* @param pCfgNode The CFGM node containing the overrides
* @param iLeaf The CPUID leaf number.
*/
{
if (pLeafNode)
{
if (RT_SUCCESS(rc))
else
if (RT_SUCCESS(rc))
else
if (RT_SUCCESS(rc))
else
if (RT_SUCCESS(rc))
else
}
return VINF_SUCCESS;
}
/**
* Load the overrides for a set of CPUID leaves.
*
* @returns VBox status code.
* @param paLeaves The leaf array.
* @param cLeaves The number of leaves.
* @param uStart The start leaf number.
* @param pCfgNode The CFGM node containing the overrides
*/
static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
{
{
if (RT_FAILURE(rc))
return rc;
}
return VINF_SUCCESS;
}
/**
* Init a set of host CPUID leaves.
*
* @returns VBox status code.
* @param paLeaves The leaf array.
* @param cLeaves The number of leaves.
* @param uStart The start leaf number.
*/
static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
{
/* Using the ECX variant for all of them can't hurt... */
ASMCpuIdExSlow(uStart + i, 0, 0, 0, &paLeaves[i].uEax, &paLeaves[i].uEbx, &paLeaves[i].uEcx, &paLeaves[i].uEdx);
/* Load CPUID leaf override; we currently don't care if the user
specifies features the host CPU doesn't support. */
}
static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCPUM, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
{
/*
* Install the CPUID information.
*/
Assert(MMHyperR0ToR3(pVM, pCPUM->GuestInfo.paCpuIdLeavesR0) == (void *)pCPUM->GuestInfo.paCpuIdLeavesR3);
Assert(MMHyperRCToR3(pVM, pCPUM->GuestInfo.paCpuIdLeavesRC) == (void *)pCPUM->GuestInfo.paCpuIdLeavesR3);
/*
* Explode the guest CPU features.
*/
rc = cpumR3CpuIdExplodeFeatures(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, &pCPUM->GuestFeatures);
/*
* Adjust the scalable bus frequency according to the CPUID information
* we're now using.
*/
pCPUM->GuestInfo.uScalableBusFreq = pCPUM->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
/*
* Populate the legacy arrays. Currently used for everything, later only
* for patch manager.
*/
{
};
{
while (cLeft-- > 0)
{
uLeaf--;
pLegacyLeaf--;
PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, uLeaf,
0 /* uSubLeaf */);
if (pLeaf)
{
}
else
}
}
return VINF_SUCCESS;
}
/**
* Initializes the emulated CPU's cpuid information.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
int rc;
{ \
}
{ \
}
/*
* Read the configuration.
*/
/** @cfgm{/CPUM/SyntheticCpu, boolean, false}
* Enables the Synthetic CPU. The Vendor ID and Processor Name are
* completely overridden by VirtualBox custom strings. Some
* CPUID information is withheld, like the cache info.
*
* This is obsoleted by PortableCpuIdLevel. */
bool fSyntheticCpu;
/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
* When non-zero CPUID features that could cause portability issues will be
* stripped. The higher the value the more features gets stripped. Higher
* values should only be used when older CPUs are involved since it may
* harm performance and maybe also cause problems with specific guests. */
rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, fSyntheticCpu ? 1 : 0);
/** @cfgm{/CPUM/GuestCpuName, string}
* The name of the CPU we're to emulate. The default is the host CPU.
* Note! CPUs other than "host" one is currently unsupported. */
char szCpuName[128];
/** @cfgm{/CPUM/CMPXCHG16B, boolean, false}
* Expose CMPXCHG16B to the guest if supported by the host.
*/
bool fCmpXchg16b;
*/
bool fMonitor;
/** @cfgm{/CPUM/MWaitExtensions, boolean, false}
* Expose MWAIT extended features to the guest. For now we expose just MWAIT
* break on interrupt feature (bit 1).
*/
bool fMWaitExtensions;
* Expose SSE4.1 to the guest if available.
*/
bool fSse41;
* Expose SSE4.2 to the guest if available.
*/
bool fSse42;
/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
*/
bool fNt4LeafLimit;
/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
* Restrict the reported CPU family+model+stepping of intel CPUs. This is
* probably going to be a temporary hack, so don't depend on this.
* The 1st byte of the value is the stepping, the 2nd byte value is the model
* number and the 3rd byte value is the family, and the 4th value must be zero.
*/
/*
*/
if (RT_FAILURE(rc))
return rc == VERR_CPUM_DB_CPU_NOT_FOUND
"Info on guest CPU '%s' could not be found. Please, select a different CPU.", szCpuName)
: rc;
* Overrides the guest MSRs.
*/
* Overrides the CPUID leaf values (from the host CPU usually) used for
* calculating the guest CPUID leaves. This can be used to preserve the CPUID
* values when moving a VM to a different machine. Another use is restricting
* (or extending) the feature set exposed to the guest. */
if (RT_SUCCESS(rc))
"Please use IMachine::setCPUIDLeaf() instead.");
/*
* Pre-explode the CPUID info.
*/
if (RT_SUCCESS(rc))
rc = cpumR3CpuIdExplodeFeatures(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, &pCPUM->GuestFeatures);
if (RT_FAILURE(rc))
{
return rc;
}
/* ... split this function about here ... */
/* Cpuid 1:
* Only report features we can support.
*
* Note! When enabling new features the Synthetic CPU and Portable CPUID
* options may require adjusting (i.e. stripping what was enabled).
*/
PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves,
1, 0); /* Note! Must refetch when used later. */
//| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
//| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
//| X86_CPUID_FEATURE_EDX_SEP
//| X86_CPUID_FEATURE_EDX_PSN - no serial number.
//| X86_CPUID_FEATURE_EDX_DS - no debug store.
//| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
//| X86_CPUID_FEATURE_EDX_SS - no self snoop.
//| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
//| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
//| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
| 0;
pStdFeatureLeaf->uEcx &= 0
/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
//| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
//| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
//| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
//| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
//| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
| (fCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
//| X86_CPUID_FEATURE_ECX_TPRUPDATE
| (fSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
| (fSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
/* ECX Bit 21 - x2APIC support - not yet. */
// | X86_CPUID_FEATURE_ECX_X2APIC
/* ECX Bit 23 - POPCNT instruction. */
//| X86_CPUID_FEATURE_ECX_POPCNT
| 0;
if (pCPUM->u8PortableCpuIdLevel > 0)
{
PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
)));
)));
}
/* Cpuid 0x80000001:
* Only report features we can support.
*
* Note! When enabling new features the Synthetic CPU and Portable CPUID
* options may require adjusting (i.e. stripping what was enabled).
*
* ASSUMES that this is ALWAYS the AMD defined feature set if present.
*/
PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves,
if (pExtFeatureLeaf)
{
| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
//| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
//| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
//| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
//| X86_CPUID_EXT_FEATURE_EDX_SEP
//| X86_CPUID_EXT_FEATURE_EDX_NX - not virtualized, requires PAE.
//| X86_CPUID_AMD_FEATURE_EDX_AXMMX
//| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
//| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
| 0;
pExtFeatureLeaf->uEcx &= 0
//| X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
//| X86_CPUID_AMD_FEATURE_ECX_CMPL
//| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
//| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
/* Note: This could prevent teleporting from AMD to Intel CPUs! */
| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
//| X86_CPUID_AMD_FEATURE_ECX_ABM
//| X86_CPUID_AMD_FEATURE_ECX_SSE4A
//| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
//| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
//| X86_CPUID_AMD_FEATURE_ECX_OSVW
//| X86_CPUID_AMD_FEATURE_ECX_IBS
//| X86_CPUID_AMD_FEATURE_ECX_SSE5
//| X86_CPUID_AMD_FEATURE_ECX_SKINIT
//| X86_CPUID_AMD_FEATURE_ECX_WDT
| 0;
if (pCPUM->u8PortableCpuIdLevel > 0)
{
PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
PORTABLE_DISABLE_FEATURE_BIT(2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
| UINT32_C(0xffffc000)
)));
| RT_BIT(18)
| RT_BIT(19)
| RT_BIT(21)
| RT_BIT(28)
)));
}
}
/*
* Hide HTT, multicode, SMP, whatever.
* (APIC-ID := 0 and #LogCpus := 0)
*/
#ifdef VBOX_WITH_MULTI_CORE
{
/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
pStdFeatureLeaf->uEdx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
}
#endif
/* Cpuid 2:
* Intel: Cache and TLB information
* AMD: Reserved
* VIA: Reserved
* Safe to expose; restrict the number of calls to 1 for the portable case.
*/
PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 2, 0);
if ( pCPUM->u8PortableCpuIdLevel > 0
&& pCurLeaf
{
}
/* Cpuid 3:
* Intel: EAX, EBX - reserved (transmeta uses these)
* ECX, EDX - Processor Serial Number if available, otherwise reserved
* AMD: Reserved
* VIA: Reserved
* Safe to expose
*/
pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 3, 0);
pStdFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 1, 0);
&& pCurLeaf)
{
if (pCPUM->u8PortableCpuIdLevel > 0)
}
/* Cpuid 4:
* Intel: Deterministic Cache Parameters Leaf
* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
* AMD: Reserved
* VIA: Reserved
* Safe to expose, except for EAX:
* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
* Bits 31-26: Maximum number of processor cores in this physical package**
* Note: These SMP values are constant regardless of ECX
*/
pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 4, 0);
if (pCurLeaf)
{
NewLeaf.fSubLeafMask = 0;
#ifdef VBOX_WITH_MULTI_CORE
{
/* One logical processor with possibly multiple cores. */
/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
}
#endif
rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves, &NewLeaf);
}
* Intel: ECX, EDX - reserved
* EAX, EBX - Smallest and largest monitor line size
* AMD: EDX - reserved
* EAX, EBX - Smallest and largest monitor line size
* ECX - extensions (ignored for now)
* VIA: Reserved
* Safe to expose
*/
pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 5, 0);
if (pCurLeaf)
{
pStdFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 1, 0);
if (fMWaitExtensions)
{
/** @todo: for now we just expose host's MWAIT C-states, although conceptually
it shall be part of our power management virtualization model */
#if 0
/* MWAIT sub C-states */
(0 << 0) /* 0 in C0 */ |
(2 << 4) /* 2 in C1 */ |
(2 << 8) /* 2 in C2 */ |
(2 << 12) /* 2 in C3 */ |
(0 << 16) /* 0 in C4 */
;
#endif
}
else
}
/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
* Safe to pass on to the guest.
*
* Intel: 0x800000005 reserved
* 0x800000006 L2 cache information
* AMD: 0x800000005 L1 cache information
* VIA: 0x800000005 TLB and L1 cache information
* 0x800000006 L2 cache information
*/
/* Cpuid 0x800000007:
* Intel: Reserved
* AMD: EAX, EBX, ECX - reserved
* EDX: Advanced Power Management Information
* VIA: Reserved
*/
pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0x80000007), 0);
if (pCurLeaf)
{
{
/* Only expose the TSC invariant capability bit to the guest. */
//| X86_CPUID_AMD_ADVPOWER_EDX_TS
//| X86_CPUID_AMD_ADVPOWER_EDX_FID
//| X86_CPUID_AMD_ADVPOWER_EDX_VID
//| X86_CPUID_AMD_ADVPOWER_EDX_TTP
//| X86_CPUID_AMD_ADVPOWER_EDX_TM
//| X86_CPUID_AMD_ADVPOWER_EDX_STC
//| X86_CPUID_AMD_ADVPOWER_EDX_MC
//| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
#if 0
/*
* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
* Linux kernels blindly assume that the AMD performance counters work
* if this is set for 64 bits guests. (Can't really find a CPUID feature
* bit for them though.)
*/
#endif
| 0;
}
else
}
/* Cpuid 0x800000008:
* EBX, ECX, EDX - reserved
* AMD: EBX, EDX - reserved
* ECX: Number of cores + APICIdCoreIdSize
* EBX, ECX, EDX - reserved
*/
pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0x80000008), 0);
if (pCurLeaf)
{
/* Only expose the virtual and physical address sizes to the guest. */
/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
* NC (0-7) Number of cores; 0 equals 1 core */
#ifdef VBOX_WITH_MULTI_CORE
{
/* Legacy method to determine the number of cores. */
pExtFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves,
UINT32_C(0x80000001), 0);
if (pExtFeatureLeaf)
}
#endif
}
/*
* Limit it the number of entries, zapping the remainder.
*
* The limits are masking off stuff about power saving and similar, this
* is perhaps a bit crudely done as there is probably some relatively harmless
* info too in these leaves (like words about having a constant TSC).
*/
pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 0, 0);
if (pCurLeaf)
{
{
}
/* NT4 hack, no zapping of extra leaves here. */
}
pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0x80000000), 0);
if (pCurLeaf)
{
{
}
}
/*
* Centaur stuff (VIA).
*
* The important part here (we think) is to make sure the 0xc0000000
* function returns 0xc0000001. As for the features, we don't currently
* let on about any of those... 0xc0000002 seems to be some
* temperature/hz/++ stuff, include it as well (static).
*/
pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0xc0000000), 0);
if (pCurLeaf)
{
{
UINT32_C(0xc0000001), 0);
if (pCurLeaf)
}
else
}
/*
* Hypervisor identification.
*
* We only return minimal information, primarily ensuring that the
* 0x40000000 function returns 0x40000001 and identifying ourselves.
* Hypervisor-specific interface is supported through GIM which will
* modify these leaves if required depending on the GIM provider.
*/
NewLeaf.fSubLeafMask = 0;
rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves, &NewLeaf);
rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves, &NewLeaf);
/*
* Mini CPU selection support for making Mac OS X happy.
*/
{
pStdFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 1, 0);
0);
{
if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
uNew |= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
}
}
/*
* MSR fudging.
*/
* Fudges some common MSRs if not present in the selected CPU database entry.
* This is for trying to keep VMs running when moved between different hosts
* and different CPU vendors. */
bool fEnable;
if (fEnable)
{
}
/*
* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
* guest CPU features again.
*/
int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCPUM, pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves);
/*
* Some more configuration that we're applying at the end of everything
* via the CPUMSetGuestCpuIdFeature API.
*/
/* Check if PAE was explicitely enabled by the user. */
if (fEnable)
/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
if (fEnable)
/* We don't enable the Hypervisor Present bit by default, but it may be needed by some guests. */
if (fEnable)
return VINF_SUCCESS;
}
/*
*
*
* Saved state related code.
* Saved state related code.
* Saved state related code.
*
*
*/
/**
* Called both in pass 0 and the final pass.
*
* @param pVM Pointer to the VM.
* @param pSSM The saved state handle.
*/
{
/*
* Save all the CPU ID leaves here so we can check them for compatibility
* upon loading.
*/
SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
/*
* Save a good portion of the raw CPU IDs as well as they may come in
* handy when validating features for raw mode.
*/
for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
}
static int cpumR3LoadCpuIdOneGuestArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
{
if (RT_SUCCESS(rc))
{
if (cCpuIds < 64)
{
{
if (RT_FAILURE(rc))
break;
NewLeaf.fSubLeafMask = 0;
}
}
else
}
if (RT_FAILURE(rc))
{
*pcLeaves = 0;
}
return rc;
}
static int cpumR3LoadCpuIdGuestArrays(PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
{
*pcLeaves = 0;
if (RT_SUCCESS(rc))
if (RT_SUCCESS(rc))
return rc;
}
/**
* Loads the CPU ID leaves saved by pass 0.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pSSM The saved state handle.
* @param uVersion The format version.
*/
{
AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
/*
* Define a bunch of macros for simplifying the code.
*/
/* Generic expression + failure message. */
do { \
if (!(expr)) \
{ \
if (fStrictCpuIdChecks) \
{ \
return rcCpuid; \
} \
} \
} while (0)
do { \
if (!(expr)) \
} while (0)
/* For comparing two values and bitch if they differs. */
do { \
{ \
if (fStrictCpuIdChecks) \
} \
} while (0)
do { \
} while (0)
/* For checking raw cpu features (raw mode). */
do { \
{ \
if (fStrictCpuIdChecks) \
} \
} while (0)
do { \
} while (0)
/* For checking guest features. */
do { \
) \
{ \
if (fStrictCpuIdChecks) \
} \
} while (0)
do { \
) \
} while (0)
do { \
) \
LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
} while (0)
/* For checking guest features if AMD guest CPU. */
do { \
&& fGuestAmd \
) \
{ \
if (fStrictCpuIdChecks) \
} \
} while (0)
do { \
&& fGuestAmd \
) \
} while (0)
do { \
&& fGuestAmd \
) \
LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
} while (0)
/* For checking AMD features which have a corresponding bit in the standard
range. (Intel defines very few bits in the extended feature sets.) */
do { \
&& !(fHostAmd \
) \
{ \
if (fStrictCpuIdChecks) \
LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
} \
} while (0)
do { \
&& !(fHostAmd \
) \
LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
} while (0)
do { \
&& !(fHostAmd \
) \
LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
} while (0)
/*
* Load them into stack buffers first.
*/
/** @todo we'll be leaking paLeaves on error return... */
ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
/*
* Get the raw CPU IDs for the current host.
*/
for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
/*
* Get the host and guest overrides so we don't reject the state because
* some feature was enabled thru these interfaces.
* Note! We currently only need the feature leaves, so skip rest.
*/
cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
/*
* This can be skipped.
*/
bool fStrictCpuIdChecks;
CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
/*
* For raw-mode we'll require that the CPUs are very similar since we don't
* intercept CPUID instructions for user mode applications.
*/
if (!HMIsEnabled(pVM))
{
/* CPUID(0) */
(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
/* CPUID(1).eax */
CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
/* CPUID(1).ecx */
/* CPUID(1).edx */
/* CPUID(2) - config, mostly about caches. ignore. */
/* CPUID(3) - processor serial number. ignore. */
/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
/* CPUID(6) - power management. ignore. */
/* CPUID(7) - ???. ignore. */
/* CPUID(8) - ???. ignore. */
/* CPUID(9) - DCA. ignore for now. */
/* CPUID(a) - PeMo info. ignore for now. */
/* CPUID(b) - topology info - takes ECX as input. ignore. */
/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
{
}
/* CPUID(0x80000000) - same as CPUID(0) except for eax.
will verify them as if it's an AMD CPU. */
CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
{
(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
/* CPUID(0x80000001).ecx */
/* CPUID(0x80000001).edx */
/** @todo verify the rest as well. */
}
}
/*
* Verify that we can support the features already exposed to the guest on
* this host.
*
* Most of the features we're emulating requires intercepting instruction
* and doing it the slow way, so there is no need to warn when they aren't
* present in the host CPU. Thus we use IGN instead of EMU on these.
*
* Trailing comments:
* "EMU" - Possible to emulate, could be lots of work and very slow.
* "EMU?" - Can this be emulated?
*/
/* CPUID(1).ecx */
/* CPUID(1).edx */
/* CPUID(0x80000000). */
{
/** @todo deal with no 0x80000001 on the host. */
bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
/* CPUID(0x80000001).ecx */
/* CPUID(0x80000001).edx */
CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
}
/*
* We're good, commit the CPU ID leaves.
*/
return VINF_SUCCESS;
}
# if defined(VBOX_WITH_RAW_MODE) || defined(DOXYGEN_RUNNING)
/** @name Patchmanager CPUID legacy table APIs
* @{
*/
/**
* Gets a pointer to the default CPUID leaf.
*
* @returns Raw-mode pointer to the default CPUID leaf (read-only).
* @param pVM Pointer to the VM.
* @remark Intended for PATM only.
*/
{
}
/**
* Gets a pointer to the CPUID leaf array.
*
* @returns Raw-mode pointer to the CPUID leaf array.
* @param pVM Pointer to the VM.
* @remark Intended for PATM only.
*/
{
Assert(MMHyperRCToR3(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesRC) == pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
}
/**
* Gets a pointer to the CPUID leaf array.
*
* @returns Raw-mode pointer to the end of CPUID leaf array (exclusive).
* @param pVM Pointer to the VM.
* @remark Intended for PATM only.
*/
{
Assert(MMHyperRCToR3(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesRC) == pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
}
/**
* Gets the unknown CPUID leaf method.
*
* @returns Unknown CPUID leaf method.
* @param pVM Pointer to the VM.
* @remark Intended for PATM only.
*/
{
}
/**
* Gets a number of standard CPUID leafs (PATM only).
*
* @returns Number of leafs.
* @param pVM Pointer to the VM.
* @remark Intended for PATM - legacy, don't use in new code.
*/
{
}
/**
* Gets a number of extended CPUID leafs (PATM only).
*
* @returns Number of leafs.
* @param pVM Pointer to the VM.
* @remark Intended for PATM - legacy, don't use in new code.
*/
{
}
/**
* Gets a number of centaur CPUID leafs.
*
* @returns Number of leafs.
* @param pVM Pointer to the VM.
* @remark Intended for PATM - legacy, don't use in new code.
*/
{
}
/**
* Gets a pointer to the array of standard CPUID leaves.
*
* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
*
* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
* @param pVM Pointer to the VM.
* @remark Intended for PATM - legacy, don't use in new code.
*/
{
}
/**
* Gets a pointer to the array of extended CPUID leaves.
*
* CPUMGetGuestCpuIdExtMax() give the size of the array.
*
* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
* @param pVM Pointer to the VM.
* @remark Intended for PATM - legacy, don't use in new code.
*/
{
}
/**
* Gets a pointer to the array of centaur CPUID leaves.
*
* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
*
* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
* @param pVM Pointer to the VM.
* @remark Intended for PATM - legacy, don't use in new code.
*/
{
}
/** @} */
# endif /* VBOX_WITH_RAW_MODE || DOXYGEN_RUNNING */
#endif /* VBOX_IN_VMM */