x86.h revision 447d6c76d88201b58c0bd7b0c8621088cf428951
/** @file
* IPRT - X86 and AMD64 Structures and Definitions.
*
* @note x86.mac is generated from this file by running 'kmk incs' in the root.
*/
/*
* Copyright (C) 2006-2014 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* The contents of this file may alternatively be used under the terms
* of the Common Development and Distribution License Version 1.0
* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
* VirtualBox OSE distribution, in which case the provisions of the
* CDDL are applicable instead of those of the GPL.
*
* You may elect to license modified versions of this file under the
* terms and conditions of either the GPL or the CDDL or both.
*/
#ifndef ___iprt_x86_h
#define ___iprt_x86_h
#ifndef VBOX_FOR_DTRACE_LIB
#else
#endif
#ifdef RT_OS_SOLARIS
#endif
/** @defgroup grp_rt_x86 x86 Types and Definitions
* @ingroup grp_rt
* @{
*/
#ifndef VBOX_FOR_DTRACE_LIB
/**
* EFLAGS Bits.
*/
typedef struct X86EFLAGSBITS
{
/** Bit 0 - CF - Carry flag - Status flag. */
unsigned u1CF : 1;
/** Bit 1 - 1 - Reserved flag. */
unsigned u1Reserved0 : 1;
/** Bit 2 - PF - Parity flag - Status flag. */
unsigned u1PF : 1;
/** Bit 3 - 0 - Reserved flag. */
unsigned u1Reserved1 : 1;
/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
unsigned u1AF : 1;
/** Bit 5 - 0 - Reserved flag. */
unsigned u1Reserved2 : 1;
/** Bit 6 - ZF - Zero flag - Status flag. */
unsigned u1ZF : 1;
/** Bit 7 - SF - Signed flag - Status flag. */
unsigned u1SF : 1;
/** Bit 8 - TF - Trap flag - System flag. */
unsigned u1TF : 1;
/** Bit 9 - IF - Interrupt flag - System flag. */
unsigned u1IF : 1;
/** Bit 10 - DF - Direction flag - Control flag. */
unsigned u1DF : 1;
/** Bit 11 - OF - Overflow flag - Status flag. */
unsigned u1OF : 1;
/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
unsigned u2IOPL : 2;
/** Bit 14 - NT - Nested task flag - System flag. */
unsigned u1NT : 1;
/** Bit 15 - 0 - Reserved flag. */
unsigned u1Reserved3 : 1;
/** Bit 16 - RF - Resume flag - System flag. */
unsigned u1RF : 1;
/** Bit 17 - VM - Virtual 8086 mode - System flag. */
unsigned u1VM : 1;
/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
unsigned u1AC : 1;
/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
unsigned u1VIF : 1;
/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
unsigned u1VIP : 1;
/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
unsigned u1ID : 1;
/** Bit 22-31 - 0 - Reserved flag. */
unsigned u10Reserved4 : 10;
/** Pointer to EFLAGS bits. */
typedef X86EFLAGSBITS *PX86EFLAGSBITS;
/** Pointer to const EFLAGS bits. */
typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
#endif /* !VBOX_FOR_DTRACE_LIB */
/**
* EFLAGS.
*/
typedef union X86EFLAGS
{
/** The plain unsigned view. */
uint32_t u;
#ifndef VBOX_FOR_DTRACE_LIB
/** The bitfield view. */
#endif
/** The 8-bit view. */
/** The 16-bit view. */
/** The 32-bit view. */
/** The 32-bit view. */
} X86EFLAGS;
/** Pointer to EFLAGS. */
typedef X86EFLAGS *PX86EFLAGS;
/** Pointer to const EFLAGS. */
typedef const X86EFLAGS *PCX86EFLAGS;
/**
* RFLAGS (32 upper bits are reserved).
*/
typedef union X86RFLAGS
{
/** The plain unsigned view. */
uint64_t u;
#ifndef VBOX_FOR_DTRACE_LIB
/** The bitfield view. */
#endif
/** The 8-bit view. */
/** The 16-bit view. */
/** The 32-bit view. */
/** The 64-bit view. */
/** The 64-bit view. */
} X86RFLAGS;
/** Pointer to RFLAGS. */
typedef X86RFLAGS *PX86RFLAGS;
/** Pointer to const RFLAGS. */
typedef const X86RFLAGS *PCX86RFLAGS;
/** @name EFLAGS
* @{
*/
/** Bit 0 - CF - Carry flag - Status flag. */
#define X86_EFL_CF RT_BIT(0)
#define X86_EFL_CF_BIT 0
/** Bit 1 - Reserved, reads as 1. */
/** Bit 2 - PF - Parity flag - Status flag. */
/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
#define X86_EFL_AF_BIT 4
/** Bit 6 - ZF - Zero flag - Status flag. */
#define X86_EFL_ZF_BIT 6
/** Bit 7 - SF - Signed flag - Status flag. */
#define X86_EFL_SF_BIT 7
/** Bit 8 - TF - Trap flag - System flag. */
/** Bit 9 - IF - Interrupt flag - System flag. */
/** Bit 10 - DF - Direction flag - Control flag. */
/** Bit 11 - OF - Overflow flag - Status flag. */
#define X86_EFL_OF_BIT 11
/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
/** Bit 14 - NT - Nested task flag - System flag. */
/** Bit 16 - RF - Resume flag - System flag. */
/** Bit 17 - VM - Virtual 8086 mode - System flag. */
/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
/** All live bits. */
/** Read as 1 bits. */
/** IOPL shift. */
#define X86_EFL_IOPL_SHIFT 12
/** The IOPL level from the flags. */
/** Bits restored by popf */
#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
/** The status bits commonly updated by arithmetic instructions. */
#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
/** @} */
/** CPUID Feature information - ECX.
* CPUID query with EAX=1.
*/
#ifndef VBOX_FOR_DTRACE_LIB
typedef struct X86CPUIDFEATECX
{
/** Bit 0 - SSE3 - Supports SSE3 or not. */
unsigned u1SSE3 : 1;
/** Bit 1 - PCLMULQDQ. */
unsigned u1PCLMULQDQ : 1;
/** Bit 2 - DS Area 64-bit layout. */
unsigned u1DTE64 : 1;
unsigned u1Monitor : 1;
/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
unsigned u1CPLDS : 1;
/** Bit 5 - VMX - Virtual Machine Technology. */
unsigned u1VMX : 1;
/** Bit 6 - SMX: Safer Mode Extensions. */
unsigned u1SMX : 1;
/** Bit 7 - EST - Enh. SpeedStep Tech. */
unsigned u1EST : 1;
/** Bit 8 - TM2 - Terminal Monitor 2. */
unsigned u1TM2 : 1;
/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
unsigned u1SSSE3 : 1;
/** Bit 10 - CNTX-ID - L1 Context ID. */
unsigned u1CNTXID : 1;
/** Bit 11 - Reserved. */
unsigned u1Reserved1 : 1;
/** Bit 12 - FMA. */
unsigned u1FMA : 1;
/** Bit 13 - CX16 - CMPXCHG16B. */
unsigned u1CX16 : 1;
/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
unsigned u1TPRUpdate : 1;
unsigned u1PDCM : 1;
/** Bit 16 - Reserved. */
unsigned u1Reserved2 : 1;
/** Bit 17 - PCID - Process-context identifiers. */
unsigned u1PCID : 1;
/** Bit 18 - Direct Cache Access. */
unsigned u1DCA : 1;
/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
unsigned u1SSE4_1 : 1;
/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
unsigned u1SSE4_2 : 1;
/** Bit 21 - x2APIC. */
unsigned u1x2APIC : 1;
/** Bit 22 - MOVBE - Supports MOVBE. */
unsigned u1MOVBE : 1;
/** Bit 23 - POPCNT - Supports POPCNT. */
unsigned u1POPCNT : 1;
/** Bit 24 - TSC-Deadline. */
unsigned u1TSCDEADLINE : 1;
/** Bit 25 - AES. */
unsigned u1AES : 1;
/** Bit 26 - XSAVE - Supports XSAVE. */
unsigned u1XSAVE : 1;
/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
unsigned u1OSXSAVE : 1;
/** Bit 28 - AVX - Supports AVX instruction extensions. */
unsigned u1AVX : 1;
/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
unsigned u1F16C : 1;
/** Bit 30 - RDRAND - Supports RDRAND. */
unsigned u1RDRAND : 1;
/** Bit 31 - Hypervisor present (we're a guest). */
unsigned u1HVP : 1;
#else /* VBOX_FOR_DTRACE_LIB */
typedef uint32_t X86CPUIDFEATECX;
#endif /* VBOX_FOR_DTRACE_LIB */
/** Pointer to CPUID Feature Information - ECX. */
typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
/** Pointer to const CPUID Feature Information - ECX. */
typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
/** CPUID Feature Information - EDX.
* CPUID query with EAX=1.
*/
#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
typedef struct X86CPUIDFEATEDX
{
/** Bit 0 - FPU - x87 FPU on Chip. */
unsigned u1FPU : 1;
/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
unsigned u1VME : 1;
/** Bit 2 - DE - Debugging extensions. */
unsigned u1DE : 1;
/** Bit 3 - PSE - Page Size Extension. */
unsigned u1PSE : 1;
/** Bit 4 - TSC - Time Stamp Counter. */
unsigned u1TSC : 1;
/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
unsigned u1MSR : 1;
/** Bit 6 - PAE - Physical Address Extension. */
unsigned u1PAE : 1;
/** Bit 7 - MCE - Machine Check Exception. */
unsigned u1MCE : 1;
/** Bit 8 - CX8 - CMPXCHG8B instruction. */
unsigned u1CX8 : 1;
/** Bit 9 - APIC - APIC On-Chip. */
unsigned u1APIC : 1;
/** Bit 10 - Reserved. */
unsigned u1Reserved1 : 1;
/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
unsigned u1SEP : 1;
/** Bit 12 - MTRR - Memory Type Range Registers. */
unsigned u1MTRR : 1;
/** Bit 13 - PGE - PTE Global Bit. */
unsigned u1PGE : 1;
/** Bit 14 - MCA - Machine Check Architecture. */
unsigned u1MCA : 1;
/** Bit 15 - CMOV - Conditional Move Instructions. */
unsigned u1CMOV : 1;
/** Bit 16 - PAT - Page Attribute Table. */
unsigned u1PAT : 1;
/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
unsigned u1PSE36 : 1;
/** Bit 18 - PSN - Processor Serial Number. */
unsigned u1PSN : 1;
/** Bit 19 - CLFSH - CLFLUSH Instruction. */
unsigned u1CLFSH : 1;
/** Bit 20 - Reserved. */
unsigned u1Reserved2 : 1;
/** Bit 21 - DS - Debug Store. */
unsigned u1DS : 1;
/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
unsigned u1ACPI : 1;
/** Bit 23 - MMX - Intel MMX 'Technology'. */
unsigned u1MMX : 1;
/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
unsigned u1FXSR : 1;
/** Bit 25 - SSE - SSE Support. */
unsigned u1SSE : 1;
/** Bit 26 - SSE2 - SSE2 Support. */
unsigned u1SSE2 : 1;
/** Bit 27 - SS - Self Snoop. */
unsigned u1SS : 1;
/** Bit 28 - HTT - Hyper-Threading Technology. */
unsigned u1HTT : 1;
/** Bit 29 - TM - Thermal Monitor. */
unsigned u1TM : 1;
/** Bit 30 - Reserved - . */
unsigned u1Reserved3 : 1;
/** Bit 31 - PBE - Pending Break Enabled. */
unsigned u1PBE : 1;
#else /* VBOX_FOR_DTRACE_LIB */
typedef uint32_t X86CPUIDFEATEDX;
#endif /* VBOX_FOR_DTRACE_LIB */
/** Pointer to CPUID Feature Information - EDX. */
typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
/** Pointer to const CPUID Feature Information - EDX. */
typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
/** @name CPUID Vendor information.
* CPUID query with EAX=0.
* @{
*/
/** @} */
/** @name CPUID Feature information.
* CPUID query with EAX=1.
* @{
*/
/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
/** ECX Bit 5 - VMX - Virtual Machine Technology. */
/** ECX Bit 6 - SMX - Safer Mode Extensions. */
/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
/** ECX Bit 12 - FMA. */
/** ECX Bit 13 - CX16 - CMPXCHG16B. */
/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
/** ECX Bit 17 - PCID - Process-context identifiers. */
/** ECX Bit 18 - DCA - Direct Cache Access. */
/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
/** ECX Bit 21 - x2APIC support. */
/** ECX Bit 22 - MOVBE instruction. */
/** ECX Bit 23 - POPCNT instruction. */
/** ECX Bir 24 - TSC-Deadline. */
/** ECX Bit 25 - AES instructions. */
/** ECX Bit 26 - XSAVE instruction. */
/** ECX Bit 27 - OSXSAVE instruction. */
/** ECX Bit 28 - AVX. */
/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
/** ECX Bit 30 - RDRAND instruction. */
/** ECX Bit 31 - Hypervisor Present (software only). */
/** Bit 0 - FPU - x87 FPU on Chip. */
#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
/** Bit 2 - DE - Debugging extensions. */
/** Bit 3 - PSE - Page Size Extension. */
/** Bit 4 - TSC - Time Stamp Counter. */
/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
/** Bit 6 - PAE - Physical Address Extension. */
/** Bit 7 - MCE - Machine Check Exception. */
/** Bit 8 - CX8 - CMPXCHG8B instruction. */
/** Bit 9 - APIC - APIC On-Chip. */
/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
/** Bit 12 - MTRR - Memory Type Range Registers. */
/** Bit 13 - PGE - PTE Global Bit. */
/** Bit 14 - MCA - Machine Check Architecture. */
/** Bit 15 - CMOV - Conditional Move Instructions. */
/** Bit 16 - PAT - Page Attribute Table. */
/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
/** Bit 18 - PSN - Processor Serial Number. */
/** Bit 19 - CLFSH - CLFLUSH Instruction. */
/** Bit 21 - DS - Debug Store. */
/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
/** Bit 23 - MMX - Intel MMX Technology. */
/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
/** Bit 25 - SSE - SSE Support. */
/** Bit 26 - SSE2 - SSE2 Support. */
/** Bit 27 - SS - Self Snoop. */
/** Bit 28 - HTT - Hyper-Threading Technology. */
/** Bit 29 - TM - Therm. Monitor. */
/** Bit 31 - PBE - Pending Break Enabled. */
/** @} */
* CPUID query with EAX=5.
* @{
*/
#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
/** @} */
/** @name CPUID Structured Extended Feature information.
* CPUID query with EAX=7.
* @{
*/
#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
/** EBX Bit 4 - HLE - Hardware Lock Elision. */
/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
/** EBX Bit 10 - INVPCID - Supports INVPCID. */
/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
/** EBX Bit 16 - AVX512F - Supports AVX512F. */
/** EBX Bit 18 - RDSEED - Supports RDSEED. */
/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT(0)
/** @} */
/** @name CPUID Extended Feature information.
* CPUID query with EAX=0x80000001.
* @{
*/
#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
/** EDX Bit 20 - No-Execute/Execute-Disable. */
/** EDX Bit 26 - 1 GB large page. */
/** EDX Bit 27 - RDTSCP. */
/** @}*/
/** @name CPUID AMD Feature information.
* CPUID query with EAX=0x80000001.
* @{
*/
/** Bit 0 - FPU - x87 FPU on Chip. */
#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
/** Bit 2 - DE - Debugging extensions. */
/** Bit 3 - PSE - Page Size Extension. */
/** Bit 4 - TSC - Time Stamp Counter. */
/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
/** Bit 6 - PAE - Physical Address Extension. */
/** Bit 7 - MCE - Machine Check Exception. */
/** Bit 8 - CX8 - CMPXCHG8B instruction. */
/** Bit 9 - APIC - APIC On-Chip. */
/** Bit 12 - MTRR - Memory Type Range Registers. */
/** Bit 13 - PGE - PTE Global Bit. */
/** Bit 14 - MCA - Machine Check Architecture. */
/** Bit 15 - CMOV - Conditional Move Instructions. */
/** Bit 16 - PAT - Page Attribute Table. */
/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
/** Bit 23 - MMX - Intel MMX Technology. */
/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
/** Bit 31 - 3DNOW - AMD 3DNow. */
/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
/** Bit 2 - SVM - AMD VM extensions. */
/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
/** Bit 9 - OSVW - AMD OS visible workaround. */
/** Bit 10 - IBS - Instruct based sampling. */
/** Bit 11 - XOP - Extended operation support (see APM6). */
/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
/** Bit 13 - WDT - AMD Watchdog timer support. */
/** Bit 15 - LWP - Lightweight profiling support. */
/** Bit 16 - FMA4 - Four operand FMA instruction support. */
/** Bit 19 - NodeId - Indicates support for
* MSR_C001_100C[NodeId,NodesPerProcessr]. */
/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
/** Bit 22 - TopologyExtensions - . */
/** @} */
/** @name CPUID AMD Feature information.
* CPUID query with EAX=0x80000007.
* @{
*/
/** Bit 0 - TS - Temperature Sensor. */
#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
/** Bit 1 - FID - Frequency ID Control. */
/** Bit 2 - VID - Voltage ID Control. */
/** Bit 3 - TTP - THERMTRIP. */
/** Bit 4 - TM - Hardware Thermal Control. */
/** Bit 5 - STC - Software Thermal Control. */
/** Bit 6 - MC - 100 Mhz Multiplier Control. */
/** Bit 7 - HWPSTATE - Hardware P-State Control. */
/** Bit 8 - TSCINVAR - TSC Invariant. */
/** Bit 9 - CPB - TSC Invariant. */
/** Bit 11 - PFI - Processor feedback interface (see EAX). */
/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
/** @} */
/** @name CR0
* @{ */
/** Bit 0 - PE - Protection Enabled */
#define X86_CR0_PE RT_BIT(0)
#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
/** Bit 1 - MP - Monitor Coprocessor */
/** Bit 2 - EM - Emulation. */
/** Bit 3 - TS - Task Switch. */
/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
/** Bit 5 - NE - Numeric error. */
/** Bit 16 - WP - Write Protect. */
/** Bit 18 - AM - Alignment Mask. */
/** Bit 29 - NW - Not Write-though. */
/** Bit 30 - WP - Cache Disable. */
/** Bit 31 - PG - Paging. */
/** @} */
/** @name CR3
* @{ */
/** Bit 3 - PWT - Page-level Writes Transparent. */
/** Bit 4 - PCD - Page-level Cache Disable. */
/** Bits 12-31 - - Page directory page number. */
#define X86_CR3_PAGE_MASK (0xfffff000)
/** Bits 5-31 - - PAE Page directory page number. */
#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
/** Bits 12-51 - - AMD64 Page directory page number. */
/** @} */
/** @name CR4
* @{ */
/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
#define X86_CR4_VME RT_BIT(0)
/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
/** Bit 2 - TSD - Time Stamp Disable. */
/** Bit 3 - DE - Debugging Extensions. */
/** Bit 4 - PSE - Page Size Extension. */
/** Bit 5 - PAE - Physical Address Extension. */
/** Bit 6 - MCE - Machine-Check Enable. */
/** Bit 7 - PGE - Page Global Enable. */
/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
/** Bit 13 - VMXE - VMX mode is enabled. */
/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
* extended states. */
/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
/** @} */
/** @name DR6
* @{ */
/** Bit 0 - B0 - Breakpoint 0 condition detected. */
#define X86_DR6_B0 RT_BIT(0)
/** Bit 1 - B1 - Breakpoint 1 condition detected. */
/** Bit 2 - B2 - Breakpoint 2 condition detected. */
/** Bit 3 - B3 - Breakpoint 3 condition detected. */
/** Mask of all the Bx bits. */
/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
/** Bit 14 - BS - Single step */
/** Bit 15 - BT - Task switch. (TSS T bit.) */
/** Bits which must be 1s in DR6. */
/** Bits which must be 0s in DR6. */
/** Bits which must be 0s on writes to DR6. */
/** @} */
/** Get the DR6.Bx bit for a the given breakpoint. */
/** @name DR7
* @{ */
/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
#define X86_DR7_L0 RT_BIT(0)
/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
/** L0, L1, L2, and L3. */
/** L0, L1, L2, and L3. */
/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
* instruction is executed.
* @see http://www.rcollins.org/secrets/DR7.html */
/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
* any DR register is accessed. */
/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
* Pentium. */
/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
/** Bits which reads as 1s. */
/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
/** Bits which must be 0s when writing to DR7. */
/** Calcs the L bit of Nth breakpoint.
* @param iBp The breakpoint number [0..3].
*/
/** Calcs the G bit of Nth breakpoint.
* @param iBp The breakpoint number [0..3].
*/
/** Calcs the L and G bits of Nth breakpoint.
* @param iBp The breakpoint number [0..3].
*/
* @{ */
/** Break on instruction fetch only. */
#define X86_DR7_RW_EO 0U
/** Break on write only. */
#define X86_DR7_RW_WO 1U
#define X86_DR7_RW_IO 2U
/** Break on read or write (but not instruction fetches). */
#define X86_DR7_RW_RW 3U
/** @} */
/** Shifts a X86_DR7_RW_* value to its right place.
* @param iBp The breakpoint number [0..3].
* @param fRw One of the X86_DR7_RW_* value.
*/
* one of the X86_DR7_RW_XXX constants).
*
* @returns X86_DR7_RW_XXX
* @param uDR7 DR7 value
* @param iBp The breakpoint number [0..3].
*/
#ifndef VBOX_FOR_DTRACE_LIB
/** Checks if there are any I/O breakpoint types configured in the RW
* registers. Does NOT check if these are enabled, sorry. */
# define X86_DR7_ANY_RW_IO(uDR7) \
#endif /* !VBOX_FOR_DTRACE_LIB */
/** @name Length values.
* @{ */
#define X86_DR7_LEN_BYTE 0U
#define X86_DR7_LEN_WORD 1U
#define X86_DR7_LEN_DWORD 3U
/** @} */
/** Shifts a X86_DR7_LEN_* value to its right place.
* @param iBp The breakpoint number [0..3].
* @param cb One of the X86_DR7_LEN_* values.
*/
/** Fetch the breakpoint length bits from the DR7 value.
* @param uDR7 DR7 value
* @param iBp The breakpoint number [0..3].
*/
/** Mask used to check if any breakpoints are enabled. */
/** LEN0, LEN1, LEN2, and LEN3. */
#define X86_DR7_INIT_VAL 0x400
/** @} */
/** @name Machine Specific Registers
* @{
*/
/** Machine check address register (P5). */
/** Machine check type register (P5). */
/** Time Stamp Counter. */
#define MSR_IA32_TSC 0x10
#define MSR_IA32_PLATFORM_ID 0x17
#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
# define MSR_IA32_APICBASE 0x1b
/** Local APIC enabled. */
/** X2APIC enabled (requires the EN bit to be set). */
/** The processor is the boot strap processor (BSP). */
/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
* width. */
#endif
/** Undocumented intel MSR for reporting thread and core counts.
* Judging from the XNU sources, it seems to be introduced in Nehalem. The
* first 16 bits is the thread count. The next 16 bits the core count, except
* on Westmere where it seems it's only the next 4 bits for some reason. */
#define MSR_CORE_THREAD_COUNT 0x35
/** CPU Feature control. */
#define MSR_IA32_FEATURE_CONTROL 0x3A
#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
/** Per-processor TSC adjust MSR. */
#define MSR_IA32_TSC_ADJUST 0x3B
/** BIOS update trigger (microcode update). */
#define MSR_IA32_BIOS_UPDT_TRIG 0x79
/** BIOS update signature (microcode). */
#define MSR_IA32_BIOS_SIGN_ID 0x8B
/** General performance counter no. 0. */
#define MSR_IA32_PMC0 0xC1
/** General performance counter no. 1. */
#define MSR_IA32_PMC1 0xC2
/** General performance counter no. 2. */
#define MSR_IA32_PMC2 0xC3
/** General performance counter no. 3. */
#define MSR_IA32_PMC3 0xC4
/** Nehalem power control. */
#define MSR_IA32_PLATFORM_INFO 0xCE
/** Get FSB clock status (Intel-specific). */
#define MSR_IA32_FSB_CLOCK_STS 0xCD
/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
/** C0 Maximum Frequency Clock Count */
#define MSR_IA32_MPERF 0xE7
/** C0 Actual Frequency Clock Count */
#define MSR_IA32_APERF 0xE8
/** MTRR Capabilities. */
#define MSR_IA32_MTRR_CAP 0xFE
#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
* R0 SS == CS + 8
* R3 CS == CS + 16
* R3 SS == CS + 24
*/
#define MSR_IA32_SYSENTER_CS 0x174
/** SYSENTER_ESP - the R0 ESP. */
#define MSR_IA32_SYSENTER_ESP 0x175
/** SYSENTER_EIP - the R0 EIP. */
#define MSR_IA32_SYSENTER_EIP 0x176
#endif
/** Machine Check Global Capabilities Register. */
#define MSR_IA32_MCG_CAP 0x179
/** Machine Check Global Status Register. */
#define MSR_IA32_MCG_STATUS 0x17A
/** Machine Check Global Control Register. */
#define MSR_IA32_MCG_CTRL 0x17B
/** Page Attribute Table. */
#define MSR_IA32_CR_PAT 0x277
/** Performance counter MSRs. (Intel only) */
#define MSR_IA32_PERFEVTSEL0 0x186
#define MSR_IA32_PERFEVTSEL1 0x187
/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
* The 16th bit whether flex ratio is being used, in which case bits 15:8
* holds a ratio that Apple takes for TSC granularity.
*
* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
#define MSR_FLEX_RATIO 0x194
/** Performance state value and starting with Intel core more.
* Apple uses the >=core features to determine TSC granularity on older CPUs. */
#define MSR_IA32_PERF_STATUS 0x198
#define MSR_IA32_PERF_CTL 0x199
#define MSR_IA32_THERM_STATUS 0x19c
/** Enable misc. processor features (R/W). */
#define MSR_IA32_MISC_ENABLE 0x1A0
/** Enable fast-strings feature (for REP MOVS and REP STORS). */
#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
/** Automatic Thermal Control Circuit Enable (R/W). */
/** Performance Monitoring Available (R). */
/** Branch Trace Storage Unavailable (R/O). */
/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
/** Enhanced Intel SpeedStep Technology Enable (R/W). */
/** Limit CPUID Maxval to 3 leafs (R/W). */
/** When set to 1, xTPR messages are disabled (R/W). */
/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
/** The number (0..3 or 0..15) of the last branch record register on P4 and
* related Xeons. */
/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
* @{ */
/** @} */
#define IA32_MTRR_PHYSBASE0 0x200
#define IA32_MTRR_PHYSMASK0 0x201
#define IA32_MTRR_PHYSBASE1 0x202
#define IA32_MTRR_PHYSMASK1 0x203
#define IA32_MTRR_PHYSBASE2 0x204
#define IA32_MTRR_PHYSMASK2 0x205
#define IA32_MTRR_PHYSBASE3 0x206
#define IA32_MTRR_PHYSMASK3 0x207
#define IA32_MTRR_PHYSBASE4 0x208
#define IA32_MTRR_PHYSMASK4 0x209
#define IA32_MTRR_PHYSBASE5 0x20a
#define IA32_MTRR_PHYSMASK5 0x20b
#define IA32_MTRR_PHYSBASE6 0x20c
#define IA32_MTRR_PHYSMASK6 0x20d
#define IA32_MTRR_PHYSBASE7 0x20e
#define IA32_MTRR_PHYSMASK7 0x20f
#define IA32_MTRR_PHYSBASE8 0x210
#define IA32_MTRR_PHYSMASK8 0x211
#define IA32_MTRR_PHYSBASE9 0x212
#define IA32_MTRR_PHYSMASK9 0x213
/** Fixed range MTRRs.
* @{ */
#define IA32_MTRR_FIX64K_00000 0x250
#define IA32_MTRR_FIX16K_80000 0x258
#define IA32_MTRR_FIX16K_A0000 0x259
#define IA32_MTRR_FIX4K_C0000 0x268
#define IA32_MTRR_FIX4K_C8000 0x269
#define IA32_MTRR_FIX4K_D0000 0x26a
#define IA32_MTRR_FIX4K_D8000 0x26b
#define IA32_MTRR_FIX4K_E0000 0x26c
#define IA32_MTRR_FIX4K_E8000 0x26d
#define IA32_MTRR_FIX4K_F0000 0x26e
#define IA32_MTRR_FIX4K_F8000 0x26f
/** @} */
/** MTRR Default Range. */
#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
#define MSR_IA32_MC0_CTL 0x400
#define MSR_IA32_MC0_STATUS 0x401
/** Basic VMX information. */
#define MSR_IA32_VMX_BASIC_INFO 0x480
/** Allowed settings for pin-based VM execution controls */
#define MSR_IA32_VMX_PINBASED_CTLS 0x481
/** Allowed settings for proc-based VM execution controls */
#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
/** Allowed settings for the VMX exit controls. */
#define MSR_IA32_VMX_EXIT_CTLS 0x483
/** Allowed settings for the VMX entry controls. */
#define MSR_IA32_VMX_ENTRY_CTLS 0x484
/** Misc VMX info. */
#define MSR_IA32_VMX_MISC 0x485
/** Fixed cleared bits in CR0. */
#define MSR_IA32_VMX_CR0_FIXED0 0x486
/** Fixed set bits in CR0. */
#define MSR_IA32_VMX_CR0_FIXED1 0x487
/** Fixed cleared bits in CR4. */
#define MSR_IA32_VMX_CR4_FIXED0 0x488
/** Fixed set bits in CR4. */
#define MSR_IA32_VMX_CR4_FIXED1 0x489
/** Information for enumerating fields in the VMCS. */
#define MSR_IA32_VMX_VMCS_ENUM 0x48A
/** Allowed settings for the VM-functions controls. */
#define MSR_IA32_VMX_VMFUNC 0x491
/** Allowed settings for secondary proc-based VM execution controls */
#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
/** EPT capabilities. */
#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
/** DS Save Area (R/W). */
#define MSR_IA32_DS_AREA 0x600
/** Running Average Power Limit (RAPL) power units. */
#define MSR_RAPL_POWER_UNIT 0x606
/** X2APIC MSR ranges. */
#define MSR_IA32_X2APIC_START 0x800
#define MSR_IA32_X2APIC_TPR 0x808
#define MSR_IA32_X2APIC_END 0xBFF
/** K6 EFER - Extended Feature Enable Register. */
/** @todo document EFER */
/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
#define MSR_K6_EFER_SCE RT_BIT(0)
/** Bit 8 - LME - Long mode enabled. (R/W) */
/** Bit 10 - LMA - Long mode active. (R) */
/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
/** Shift value for getting the SYSRET CS and SS value. */
#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
/** Shift value for getting the SYSCALL CS and SS value. */
#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
/** Selector mask for use after shifting. */
/** The mask which give the SYSCALL EIP. */
/** K6 WHCR - Write Handling Control Register. */
/** K6 PSOR - Processor State Observability Register. */
/** K6 PFIR - Page Flush/Invalidate Register. */
/** Performance counter MSRs. (AMD only) */
/** K8 LSTAR - Long mode SYSCALL target (RIP). */
/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
/** K8 FS.base - The 64-bit base FS register. */
/** K8 GS.base - The 64-bit base GS register. */
/** K8 KernelGSbase - Used with SWAPGS. */
/** K8 TSC_AUX - Used with RDTSCP. */
/** North bridge config? See BIOS & Kernel dev guides for
* details. */
/** Hypertransport interrupt pending register.
* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
* host state during world switch. */
/** @} */
/** @name Page Table / Directory / Directory Pointers / L4.
* @{
*/
typedef X86PGUINT *PX86PGUINT;
typedef X86PGUINT const *PCX86PGUINT;
#define X86_PG_ENTRIES 1024
typedef uint64_t X86PGPAEUINT;
typedef X86PGPAEUINT *PX86PGPAEUINT;
typedef X86PGPAEUINT const *PCX86PGPAEUINT;
#define X86_PG_PAE_ENTRIES 512
/** Number of entries in a PAE PDPT. */
#define X86_PG_PAE_PDPE_ENTRIES 4
/** Number of entries in an AMD64 PDPT.
* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
/** The size of a 4KB page. */
#define X86_PAGE_4K_SIZE _4K
/** The page shift of a 4KB page. */
#define X86_PAGE_4K_SHIFT 12
/** The 4KB page offset mask. */
#define X86_PAGE_4K_OFFSET_MASK 0xfff
/** The 4KB page base mask for virtual addresses. */
#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
/** The 4KB page base mask for virtual addresses - 32bit version. */
#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
/** The size of a 2MB page. */
#define X86_PAGE_2M_SIZE _2M
/** The page shift of a 2MB page. */
#define X86_PAGE_2M_SHIFT 21
/** The 2MB page offset mask. */
#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
/** The 2MB page base mask for virtual addresses. */
#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
/** The 2MB page base mask for virtual addresses - 32bit version. */
#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
/** The size of a 4MB page. */
#define X86_PAGE_4M_SIZE _4M
/** The page shift of a 4MB page. */
#define X86_PAGE_4M_SHIFT 22
/** The 4MB page offset mask. */
#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
/** The 4MB page base mask for virtual addresses. */
#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
/** The 4MB page base mask for virtual addresses - 32bit version. */
#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
/**
* Check if the given address is canonical.
*/
#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
/** @name Page Table Entry
* @{
*/
/** Bit 0 - P - Present bit. */
#define X86_PTE_BIT_P 0
/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
#define X86_PTE_BIT_RW 1
/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
#define X86_PTE_BIT_US 2
/** Bit 3 - PWT - Page level write thru bit. */
#define X86_PTE_BIT_PWT 3
/** Bit 4 - PCD - Page level cache disable bit. */
#define X86_PTE_BIT_PCD 4
/** Bit 5 - A - Access bit. */
#define X86_PTE_BIT_A 5
/** Bit 6 - D - Dirty bit. */
#define X86_PTE_BIT_D 6
/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
#define X86_PTE_BIT_PAT 7
/** Bit 8 - G - Global flag. */
#define X86_PTE_BIT_G 8
/** Bit 0 - P - Present bit mask. */
/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
/** Bit 3 - PWT - Page level write thru bit mask. */
/** Bit 4 - PCD - Page level cache disable bit mask. */
/** Bit 5 - A - Access bit mask. */
/** Bit 6 - D - Dirty bit mask. */
/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
/** Bit 8 - G - Global bit mask. */
/** Bits 9-11 - - Available for use to system software. */
/** Bits 12-31 - - Physical Page number of the next level. */
#define X86_PTE_PG_MASK ( 0xfffff000 )
/** Bits 12-51 - - PAE - Physical Page number of the next level. */
/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
/** Bits 63-52 - - PAE - MBZ bits when no NX. */
/** No bits - - LM - MBZ bits when NX is active. */
/** Bits 63 - - LM - MBZ bits when no NX. */
/**
* Page table entry.
*/
typedef struct X86PTEBITS
{
/** Flags whether(=1) or not the page is present. */
unsigned u1Present : 1;
/** Read(=0) / Write(=1) flag. */
unsigned u1Write : 1;
/** User(=1) / Supervisor (=0) flag. */
unsigned u1User : 1;
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
unsigned u1WriteThru : 1;
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
unsigned u1CacheDisable : 1;
/** Accessed flag.
* Indicates that the page have been read or written to. */
unsigned u1Accessed : 1;
/** Dirty flag.
* Indicates that the page has been written to. */
unsigned u1Dirty : 1;
/** Reserved / If PAT enabled, bit 2 of the index. */
unsigned u1PAT : 1;
/** Global flag. (Ignored in all but final level.) */
unsigned u1Global : 1;
/** Available for use to system software. */
unsigned u3Available : 3;
/** Physical Page number of the next level. */
unsigned u20PageNo : 20;
} X86PTEBITS;
/** Pointer to a page table entry. */
typedef X86PTEBITS *PX86PTEBITS;
/** Pointer to a const page table entry. */
typedef const X86PTEBITS *PCX86PTEBITS;
/**
* Page table entry.
*/
typedef union X86PTE
{
/** Unsigned integer view */
X86PGUINT u;
/** Bit field view. */
X86PTEBITS n;
/** 32-bit view. */
/** 16-bit view. */
/** 8-bit view. */
} X86PTE;
/** Pointer to a page table entry. */
/** Pointer to a const page table entry. */
/**
* PAE page table entry.
*/
typedef struct X86PTEPAEBITS
{
/** Flags whether(=1) or not the page is present. */
/** Read(=0) / Write(=1) flag. */
/** User(=1) / Supervisor(=0) flag. */
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
/** Accessed flag.
* Indicates that the page have been read or written to. */
/** Dirty flag.
* Indicates that the page has been written to. */
/** Reserved / If PAT enabled, bit 2 of the index. */
/** Global flag. (Ignored in all but final level.) */
/** Available for use to system software. */
/** Physical Page number of the next level - Low Part. Don't use this. */
/** Physical Page number of the next level - High Part. Don't use this. */
/** MBZ bits */
/** No Execute flag. */
/** Pointer to a page table entry. */
typedef X86PTEPAEBITS *PX86PTEPAEBITS;
/** Pointer to a page table entry. */
typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
/**
* PAE Page table entry.
*/
typedef union X86PTEPAE
{
/** Unsigned integer view */
X86PGPAEUINT u;
/** Bit field view. */
/** 32-bit view. */
/** 16-bit view. */
/** 8-bit view. */
} X86PTEPAE;
/** Pointer to a PAE page table entry. */
typedef X86PTEPAE *PX86PTEPAE;
/** Pointer to a const PAE page table entry. */
typedef const X86PTEPAE *PCX86PTEPAE;
/** @} */
/**
* Page table.
*/
typedef struct X86PT
{
/** PTE Array. */
X86PTE a[X86_PG_ENTRIES];
} X86PT;
/** Pointer to a page table. */
/** Pointer to a const page table. */
/** The page shift to get the PT index. */
#define X86_PT_SHIFT 12
/** The PT index mask (apply to a shifted page address). */
#define X86_PT_MASK 0x3ff
/**
* Page directory.
*/
typedef struct X86PTPAE
{
/** PTE Array. */
} X86PTPAE;
/** Pointer to a page table. */
/** Pointer to a const page table. */
typedef const X86PTPAE *PCX86PTPAE;
/** The page shift to get the PA PTE index. */
#define X86_PT_PAE_SHIFT 12
/** The PAE PT index mask (apply to a shifted page address). */
#define X86_PT_PAE_MASK 0x1ff
/** @name 4KB Page Directory Entry
* @{
*/
/** Bit 0 - P - Present bit. */
/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
/** Bit 3 - PWT - Page level write thru bit. */
/** Bit 4 - PCD - Page level cache disable bit. */
/** Bit 5 - A - Access bit. */
/** Bit 7 - PS - Page size attribute.
* Clear mean 4KB pages, set means large pages (2/4MB). */
/** Bits 9-11 - - Available for use to system software. */
/** Bits 12-31 - - Physical Page number of the next level. */
#define X86_PDE_PG_MASK ( 0xfffff000 )
/** Bits 12-51 - - PAE - Physical Page number of the next level. */
/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
/** Bit 7 - - LM - MBZ bits when NX is active. */
/** Bits 63, 7 - - LM - MBZ bits when no NX. */
/**
* Page directory entry.
*/
typedef struct X86PDEBITS
{
/** Flags whether(=1) or not the page is present. */
unsigned u1Present : 1;
/** Read(=0) / Write(=1) flag. */
unsigned u1Write : 1;
/** User(=1) / Supervisor (=0) flag. */
unsigned u1User : 1;
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
unsigned u1WriteThru : 1;
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
unsigned u1CacheDisable : 1;
/** Accessed flag.
* Indicates that the page has been read or written to. */
unsigned u1Accessed : 1;
/** Reserved / Ignored (dirty bit). */
unsigned u1Reserved0 : 1;
/** Size bit if PSE is enabled - in any event it's 0. */
unsigned u1Size : 1;
/** Reserved / Ignored (global bit). */
unsigned u1Reserved1 : 1;
/** Available for use to system software. */
unsigned u3Available : 3;
/** Physical Page number of the next level. */
unsigned u20PageNo : 20;
} X86PDEBITS;
/** Pointer to a page directory entry. */
typedef X86PDEBITS *PX86PDEBITS;
/** Pointer to a const page directory entry. */
typedef const X86PDEBITS *PCX86PDEBITS;
/**
* PAE page directory entry.
*/
typedef struct X86PDEPAEBITS
{
/** Flags whether(=1) or not the page is present. */
/** Read(=0) / Write(=1) flag. */
/** User(=1) / Supervisor (=0) flag. */
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
/** Accessed flag.
* Indicates that the page has been read or written to. */
/** Reserved / Ignored (dirty bit). */
/** Size bit if PSE is enabled - in any event it's 0. */
/** Reserved / Ignored (global bit). / */
/** Available for use to system software. */
/** Physical Page number of the next level - Low Part. Don't use! */
/** Physical Page number of the next level - High Part. Don't use! */
/** MBZ bits */
/** No Execute flag. */
/** Pointer to a page directory entry. */
typedef X86PDEPAEBITS *PX86PDEPAEBITS;
/** Pointer to a const page directory entry. */
typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
/** @} */
/** @name 2/4MB Page Directory Entry
* @{
*/
/** Bit 0 - P - Present bit. */
#define X86_PDE4M_P RT_BIT(0)
/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
/** Bit 3 - PWT - Page level write thru bit. */
/** Bit 4 - PCD - Page level cache disable bit. */
/** Bit 5 - A - Access bit. */
/** Bit 6 - D - Dirty bit. */
/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
/** Bit 8 - G - Global flag. */
/** Bits 9-11 - AVL - Available for use to system software. */
/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
/** Bits 22-31 - - Physical Page number. */
#define X86_PDE4M_PG_MASK ( 0xffc00000 )
/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
/** The number of bits to the high part of the page number. */
#define X86_PDE4M_PG_HIGH_SHIFT 19
/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
/** Bits 20-13 - - LM - MBZ bits when NX is active. */
/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
/**
* 4MB page directory entry.
*/
typedef struct X86PDE4MBITS
{
/** Flags whether(=1) or not the page is present. */
unsigned u1Present : 1;
/** Read(=0) / Write(=1) flag. */
unsigned u1Write : 1;
/** User(=1) / Supervisor (=0) flag. */
unsigned u1User : 1;
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
unsigned u1WriteThru : 1;
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
unsigned u1CacheDisable : 1;
/** Accessed flag.
* Indicates that the page have been read or written to. */
unsigned u1Accessed : 1;
/** Dirty flag.
* Indicates that the page has been written to. */
unsigned u1Dirty : 1;
/** Page size flag - always 1 for 4MB entries. */
unsigned u1Size : 1;
/** Global flag. */
unsigned u1Global : 1;
/** Available for use to system software. */
unsigned u3Available : 3;
/** Reserved / If PAT enabled, bit 2 of the index. */
unsigned u1PAT : 1;
/** Bits 32-39 of the page number on AMD64.
* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
unsigned u8PageNoHigh : 8;
/** Reserved. */
unsigned u1Reserved : 1;
/** Physical Page number of the page. */
unsigned u10PageNo : 10;
} X86PDE4MBITS;
/** Pointer to a page table entry. */
typedef X86PDE4MBITS *PX86PDE4MBITS;
/** Pointer to a const page table entry. */
typedef const X86PDE4MBITS *PCX86PDE4MBITS;
/**
* 2MB PAE page directory entry.
*/
typedef struct X86PDE2MPAEBITS
{
/** Flags whether(=1) or not the page is present. */
/** Read(=0) / Write(=1) flag. */
/** User(=1) / Supervisor(=0) flag. */
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
/** Accessed flag.
* Indicates that the page have been read or written to. */
/** Dirty flag.
* Indicates that the page has been written to. */
/** Page size flag - always 1 for 2MB entries. */
/** Global flag. */
/** Available for use to system software. */
/** Reserved / If PAT enabled, bit 2 of the index. */
/** Reserved. */
/** Physical Page number of the next level - Low part. Don't use! */
/** Physical Page number of the next level - High part. Don't use! */
/** MBZ bits */
/** No Execute flag. */
/** Pointer to a 2MB PAE page table entry. */
typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
/** Pointer to a 2MB PAE page table entry. */
typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
/** @} */
/**
* Page directory entry.
*/
typedef union X86PDE
{
/** Unsigned integer view. */
X86PGUINT u;
/** Normal view. */
X86PDEBITS n;
/** 4MB view (big). */
X86PDE4MBITS b;
/** 8 bit unsigned integer view. */
/** 16 bit unsigned integer view. */
/** 32 bit unsigned integer view. */
} X86PDE;
/** Pointer to a page directory entry. */
/** Pointer to a const page directory entry. */
/**
* PAE page directory entry.
*/
typedef union X86PDEPAE
{
/** Unsigned integer view. */
X86PGPAEUINT u;
/** Normal view. */
/** 2MB page view (big). */
/** 8 bit unsigned integer view. */
/** 16 bit unsigned integer view. */
/** 32 bit unsigned integer view. */
} X86PDEPAE;
/** Pointer to a page directory entry. */
typedef X86PDEPAE *PX86PDEPAE;
/** Pointer to a const page directory entry. */
typedef const X86PDEPAE *PCX86PDEPAE;
/**
* Page directory.
*/
typedef struct X86PD
{
/** PDE Array. */
X86PDE a[X86_PG_ENTRIES];
} X86PD;
/** Pointer to a page directory. */
/** Pointer to a const page directory. */
/** The page shift to get the PD index. */
#define X86_PD_SHIFT 22
/** The PD index mask (apply to a shifted page address). */
#define X86_PD_MASK 0x3ff
/**
* PAE page directory.
*/
typedef struct X86PDPAE
{
/** PDE Array. */
} X86PDPAE;
/** Pointer to a PAE page directory. */
/** Pointer to a const PAE page directory. */
typedef const X86PDPAE *PCX86PDPAE;
/** The page shift to get the PAE PD index. */
#define X86_PD_PAE_SHIFT 21
/** The PAE PD index mask (apply to a shifted page address). */
#define X86_PD_PAE_MASK 0x1ff
/** @name Page Directory Pointer Table Entry (PAE)
* @{
*/
/** Bit 0 - P - Present bit. */
#define X86_PDPE_P RT_BIT(0)
/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
/** Bit 3 - PWT - Page level write thru bit. */
/** Bit 4 - PCD - Page level cache disable bit. */
/** Bit 5 - A - Access bit. Long Mode only. */
/** Bit 7 - PS - Page size (1GB). Long Mode only. */
/** Bits 9-11 - - Available for use to system software. */
/** Bits 12-51 - - PAE - Physical Page number of the next level. */
/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
/**
* Page directory pointer table entry.
*/
typedef struct X86PDPEBITS
{
/** Flags whether(=1) or not the page is present. */
/** Chunk of reserved bits. */
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
/** Chunk of reserved bits. */
/** Available for use to system software. */
/** Physical Page number of the next level - Low Part. Don't use! */
/** Physical Page number of the next level - High Part. Don't use! */
/** MBZ bits */
} X86PDPEBITS;
/** Pointer to a page directory pointer table entry. */
typedef X86PDPEBITS *PX86PTPEBITS;
/** Pointer to a const page directory pointer table entry. */
typedef const X86PDPEBITS *PCX86PTPEBITS;
/**
* Page directory pointer table entry. AMD64 version
*/
typedef struct X86PDPEAMD64BITS
{
/** Flags whether(=1) or not the page is present. */
/** Read(=0) / Write(=1) flag. */
/** User(=1) / Supervisor (=0) flag. */
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
/** Accessed flag.
* Indicates that the page have been read or written to. */
/** Chunk of reserved bits. */
/** Available for use to system software. */
/** Physical Page number of the next level - Low Part. Don't use! */
/** Physical Page number of the next level - High Part. Don't use! */
/** MBZ bits */
/** No Execute flag. */
/** Pointer to a page directory pointer table entry. */
typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
/** Pointer to a const page directory pointer table entry. */
typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
/**
* Page directory pointer table entry.
*/
typedef union X86PDPE
{
/** Unsigned integer view. */
X86PGPAEUINT u;
/** Normal view. */
X86PDPEBITS n;
/** AMD64 view. */
/** 8 bit unsigned integer view. */
/** 16 bit unsigned integer view. */
/** 32 bit unsigned integer view. */
} X86PDPE;
/** Pointer to a page directory pointer table entry. */
/** Pointer to a const page directory pointer table entry. */
/**
* Page directory pointer table.
*/
typedef struct X86PDPT
{
/** PDE Array. */
} X86PDPT;
/** Pointer to a page directory pointer table. */
/** Pointer to a const page directory pointer table. */
/** The page shift to get the PDPT index. */
#define X86_PDPT_SHIFT 30
/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
#define X86_PDPT_MASK_PAE 0x3
/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
#define X86_PDPT_MASK_AMD64 0x1ff
/** @} */
/** @name Page Map Level-4 Entry (Long Mode PAE)
* @{
*/
/** Bit 0 - P - Present bit. */
#define X86_PML4E_P RT_BIT(0)
/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
/** Bit 3 - PWT - Page level write thru bit. */
/** Bit 4 - PCD - Page level cache disable bit. */
/** Bit 5 - A - Access bit. */
/** Bits 9-11 - - Available for use to system software. */
/** Bits 12-51 - - PAE - Physical Page number of the next level. */
/** Bits 8, 7 - - MBZ bits when NX is active. */
/** Bits 63, 7 - - MBZ bits when no NX. */
/** Bits 63 - NX - PAE - No execution flag. */
/**
* Page Map Level-4 Entry
*/
typedef struct X86PML4EBITS
{
/** Flags whether(=1) or not the page is present. */
/** Read(=0) / Write(=1) flag. */
/** User(=1) / Supervisor (=0) flag. */
/** Write Thru flag. If PAT enabled, bit 0 of the index. */
/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
/** Accessed flag.
* Indicates that the page have been read or written to. */
/** Chunk of reserved bits. */
/** Available for use to system software. */
/** Physical Page number of the next level - Low Part. Don't use! */
/** Physical Page number of the next level - High Part. Don't use! */
/** MBZ bits */
/** No Execute flag. */
} X86PML4EBITS;
/** Pointer to a page map level-4 entry. */
typedef X86PML4EBITS *PX86PML4EBITS;
/** Pointer to a const page map level-4 entry. */
typedef const X86PML4EBITS *PCX86PML4EBITS;
/**
* Page Map Level-4 Entry.
*/
typedef union X86PML4E
{
/** Unsigned integer view. */
X86PGPAEUINT u;
/** Normal view. */
X86PML4EBITS n;
/** 8 bit unsigned integer view. */
/** 16 bit unsigned integer view. */
/** 32 bit unsigned integer view. */
} X86PML4E;
/** Pointer to a page map level-4 entry. */
/** Pointer to a const page map level-4 entry. */
typedef const X86PML4E *PCX86PML4E;
/**
* Page Map Level-4.
*/
typedef struct X86PML4
{
/** PDE Array. */
} X86PML4;
/** Pointer to a page map level-4. */
/** Pointer to a const page map level-4. */
/** The page shift to get the PML4 index. */
#define X86_PML4_SHIFT 39
/** The PML4 index mask (apply to a shifted page address). */
#define X86_PML4_MASK 0x1ff
/** @} */
/** @} */
/**
* 32-bit protected mode FSTENV image.
*/
typedef struct X86FSTENV32P
{
} X86FSTENV32P;
/** Pointer to a 32-bit protected mode FSTENV image. */
typedef X86FSTENV32P *PX86FSTENV32P;
/** Pointer to a const 32-bit protected mode FSTENV image. */
typedef X86FSTENV32P const *PCX86FSTENV32P;
/**
*/
typedef struct X86FPUMMX
{
} X86FPUMMX;
#ifndef VBOX_FOR_DTRACE_LIB
#endif
typedef X86FPUMMX *PX86FPUMMX;
typedef const X86FPUMMX *PCX86FPUMMX;
/** FPU (x87) register. */
typedef union X86FPUREG
{
/** MMX view. */
/** FPU view - todo. */
/** Extended precision floating point view. */
/** Extended precision floating point view v2 */
/** 8-bit view. */
/** 16-bit view. */
/** 32-bit view. */
/** 64-bit view. */
/** 128-bit view. (yeah, very helpful) */
} X86FPUREG;
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** Pointer to a FPU register. */
typedef X86FPUREG *PX86FPUREG;
/** Pointer to a const FPU register. */
typedef X86FPUREG const *PCX86FPUREG;
/**
* XMM register union.
*/
typedef union X86XMMREG
{
/** XMM Register view *. */
/** 8-bit view. */
/** 16-bit view. */
/** 32-bit view. */
/** 64-bit view. */
/** 128-bit view. (yeah, very helpful) */
} X86XMMREG;
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** Pointer to an XMM register state. */
typedef X86XMMREG *PX86XMMREG;
/** Pointer to a const XMM register state. */
typedef X86XMMREG const *PCX86XMMREG;
/**
* YMM register union.
*/
typedef union X86YMMREG
{
/** 8-bit view. */
/** 16-bit view. */
/** 32-bit view. */
/** 64-bit view. */
/** 128-bit view. (yeah, very helpful) */
/** XMM sub register view. */
} X86YMMREG;
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** Pointer to an YMM register state. */
typedef X86YMMREG *PX86YMMREG;
/** Pointer to a const YMM register state. */
typedef X86YMMREG const *PCX86YMMREG;
/**
* ZMM register union.
*/
typedef union X86ZMMREG
{
/** 8-bit view. */
/** 16-bit view. */
/** 32-bit view. */
/** 64-bit view. */
/** 128-bit view. (yeah, very helpful) */
/** XMM sub register view. */
/** YMM sub register view. */
} X86ZMMREG;
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** Pointer to an ZMM register state. */
typedef X86ZMMREG *PX86ZMMREG;
/** Pointer to a const ZMM register state. */
typedef X86ZMMREG const *PCX86ZMMREG;
/**
* @todo verify this...
*/
#pragma pack(1)
typedef struct X86FPUSTATE
{
/** 0x00 - Control word. */
/** 0x02 - Alignment word */
/** 0x04 - Status word. */
/** 0x06 - Alignment word */
/** 0x08 - Tag word */
/** 0x0a - Alignment word */
/** 0x0c - Instruction pointer. */
/** 0x10 - Code selector. */
/** 0x12 - Opcode. */
/** 0x14 - FOO. */
/** 0x18 - FOS. */
/** 0x1c - FPU register. */
} X86FPUSTATE;
#pragma pack()
/** Pointer to a FPU state. */
typedef X86FPUSTATE *PX86FPUSTATE;
/** Pointer to a const FPU state. */
typedef const X86FPUSTATE *PCX86FPUSTATE;
/**
*/
#pragma pack(1)
typedef struct X86FXSTATE
{
/** 0x00 - Control word. */
/** 0x02 - Status word. */
/** 0x04 - Tag word. (The upper byte is always zero.) */
/** 0x06 - Opcode. */
/** 0x08 - Instruction pointer. */
/** 0x0c - Code selector. */
/** 0x10 - Data pointer. */
/** 0x14 - Data segment */
/** 0x16 */
/** 0x18 */
/** 0x1c */
/** 0x20 - FPU registers. */
/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
/* - offset 416 - */
/* - offset 464 - Software usable reserved bits. */
} X86FXSTATE;
#pragma pack()
/** Pointer to a FPU Extended state. */
typedef X86FXSTATE *PX86FXSTATE;
/** Pointer to a const FPU Extended state. */
typedef const X86FXSTATE *PCX86FXSTATE;
/** Offset for software usable reserved bits (464:511) where we store a 32-bit
* magic. Don't forget to update x86.mac if you change this! */
#define X86_OFF_FXSTATE_RSVD 0x1d0
/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
* forget to update x86.mac if you change this!
* @todo r=bird: This has nothing what-so-ever to do here.... */
#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** @name FPU status word flags.
* @{ */
/** Exception Flag: Invalid operation. */
#define X86_FSW_IE RT_BIT(0)
/** Exception Flag: Denormalized operand. */
/** Exception Flag: Zero divide. */
/** Exception Flag: Overflow. */
/** Exception Flag: Underflow. */
/** Exception Flag: Precision. */
/** Stack fault. */
/** Error summary status. */
/** Mask of exceptions flags, excluding the summary bit. */
/** Mask of exceptions flags, including the summary bit. */
/** Condition code 0. */
/** Condition code 1. */
/** Condition code 2. */
/** Top of the stack mask. */
/** TOP shift value. */
#define X86_FSW_TOP_SHIFT 11
/** Mask for getting TOP value after shifting it right. */
/** Get the TOP value. */
/** Condition code 3. */
/** Mask of exceptions flags, including the summary bit. */
/** FPU busy. */
/** @} */
/** @name FPU control word flags.
* @{ */
/** Exception Mask: Invalid operation. */
#define X86_FCW_IM RT_BIT(0)
/** Exception Mask: Denormalized operand. */
/** Exception Mask: Zero divide. */
/** Exception Mask: Overflow. */
/** Exception Mask: Underflow. */
/** Exception Mask: Precision. */
/** Mask all exceptions, the value typically loaded (by for instance fninit).
* @remarks This includes reserved bit 6. */
/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
/** Precision control mask. */
/** Precision control: 24-bit. */
/** Precision control: Reserved. */
/** Precision control: 53-bit. */
/** Precision control: 64-bit. */
/** Rounding control mask. */
/** Rounding control: To nearest. */
/** Rounding control: Down. */
/** Rounding control: Up. */
/** Rounding control: Towards zero. */
/** Bits which should be zero, apparently. */
/** @} */
/** @name SSE MXCSR
* @{ */
/** Exception Flag: Invalid operation. */
#define X86_MXSCR_IE RT_BIT(0)
/** Exception Flag: Denormalized operand. */
/** Exception Flag: Zero divide. */
/** Exception Flag: Overflow. */
/** Exception Flag: Underflow. */
/** Exception Flag: Precision. */
/** Denormals are zero. */
/** Exception Mask: Invalid operation. */
/** Exception Mask: Denormalized operand. */
/** Exception Mask: Zero divide. */
/** Exception Mask: Overflow. */
/** Exception Mask: Underflow. */
/** Exception Mask: Precision. */
/** Rounding control mask. */
/** Rounding control: To nearest. */
/** Rounding control: Down. */
/** Rounding control: Up. */
/** Rounding control: Towards zero. */
/** Flush-to-zero for masked underflow. */
/** Misaligned Exception Mask (AMD MISALIGNSSE). */
/** @} */
/**
* XSAVE header.
*/
typedef struct X86XSAVEHDR
{
/** XTATE_BV - Bitmap indicating whether a component is in the state. */
/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
/** Reserved for furture extensions, probably MBZ. */
} X86XSAVEHDR;
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** Pointer to an XSAVE header. */
typedef X86XSAVEHDR *PX86XSAVEHDR;
/** Pointer to a const XSAVE header. */
typedef X86XSAVEHDR const *PCX86XSAVEHDR;
/**
* The high 128-bit YMM register state (XSAVE_C_YMM).
* (The lower 128-bits being in X86FXSTATE.)
*/
typedef struct X86XSAVEYMMHI
{
/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** Pointer to a high 128-bit YMM register state. */
typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
/** Pointer to a const high 128-bit YMM register state. */
typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
/**
* Intel MPX bound registers state (XSAVE_C_BNDREGS).
*/
typedef struct X86XSAVEBNDREGS
{
/** Array of registers (BND0...BND3). */
struct
{
/** Lower bound. */
/** Upper bound. */
} aRegs[4];
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** Pointer to a MPX bound register state. */
typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
/** Pointer to a const MPX bound register state. */
typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
/**
* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
*/
typedef struct X86XSAVEBNDCFG
{
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** Pointer to a MPX bound config and status register state. */
typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
/** Pointer to a const MPX bound config and status register state. */
typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
/**
* AVX-512 opmask state (XSAVE_C_OPMASK).
*/
typedef struct X86XSAVEOPMASK
{
/** The K0..K7 values. */
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** Pointer to a AVX-512 opmask state. */
typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
/** Pointer to a const AVX-512 opmask state. */
typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
/**
* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
*/
typedef struct X86XSAVEZMMHI256
{
/** Upper 256-bits of ZMM0-15. */
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
/**
* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
*/
typedef struct X86XSAVEZMM16HI
{
/** ZMM16 thru ZMM31. */
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** Pointer to a state comprising ZMM16-32. */
typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
/** Pointer to a const state comprising ZMM16-32. */
typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
/**
* AMD Light weight profiling state (XSAVE_C_LWP).
*
* We probably won't play with this as AMD seems to be dropping from their "zen"
* processor micro architecture.
*/
typedef struct X86XSAVELWP
{
/** Details when needed. */
} X86XSAVELWP;
#ifndef VBOX_FOR_DTRACE_LIB
#endif
typedef struct X86XSAVEAREA
{
/** The x87 and SSE region (or legacy region if you like). */
/** The XSAVE header. */
/** Beyond the header, there isn't really a fixed layout, but we can
generally assume the YMM (AVX) register extensions are present and
follows immediately. */
union
{
/** This is a typical layout on intel CPUs (good for debuggers). */
struct
{
} Intel;
/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
struct
{
} AmdBd;
/** To enbling static deployments that have a reasonable chance of working for
* the next 3-6 CPU generations without running short on space, we allocate a
* lot of extra space here, making the structure a round 8KB in size. This
* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
} u;
} X86XSAVEAREA;
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** Pointer to a XSAVE area. */
typedef X86XSAVEAREA *PX86XSAVEAREA;
/** Pointer to a const XSAVE area. */
typedef X86XSAVEAREA const *PCX86XSAVEAREA;
/** @name XSAVE_C_XXX - XSAVE State Components Bits.
* @{ */
/** Bit 0 - x87 - Legacy FPU state. */
#define XSAVE_C_X87 RT_BIT_64(0)
/** Bit 1 - SSE - 128-bit SSE state. */
/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
/** Bit 3 - BNDREGS - MPX bound register state. */
/** Bit 4 - BNDCSR - MPX bound config and status state. */
/** Bit 5 - Opmask - opmask state. */
/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
/** Bit 62 - LWP - Lightweight Profiling (AMD). */
/** @} */
/** @name Selector Descriptor
* @{
*/
#ifndef VBOX_FOR_DTRACE_LIB
/**
* Descriptor attributes (as seen by VT-x).
*/
typedef struct X86DESCATTRBITS
{
/** 00 - Segment Type. */
unsigned u4Type : 4;
unsigned u1DescType : 1;
/** 05 - Descriptor Privilege level. */
unsigned u2Dpl : 2;
/** 07 - Flags selector present(=1) or not. */
unsigned u1Present : 1;
/** 08 - Segment limit 16-19. */
unsigned u4LimitHigh : 4;
/** 0c - Available for system software. */
unsigned u1Available : 1;
/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
unsigned u1Long : 1;
/** 0e - This flags meaning depends on the segment type. Try make sense out
* of the intel manual yourself. */
unsigned u1DefBig : 1;
/** 0f - Granularity of the limit. If set 4KB granularity is used, if
* clear byte. */
unsigned u1Granularity : 1;
/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
unsigned u1Unusable : 1;
#endif /* !VBOX_FOR_DTRACE_LIB */
/** @name X86DESCATTR masks
* @{ */
/** @} */
#pragma pack(1)
typedef union X86DESCATTR
{
/** Unsigned integer view. */
uint32_t u;
#ifndef VBOX_FOR_DTRACE_LIB
/** Normal view. */
#endif
} X86DESCATTR;
#pragma pack()
/** Pointer to descriptor attributes. */
typedef X86DESCATTR *PX86DESCATTR;
/** Pointer to const descriptor attributes. */
typedef const X86DESCATTR *PCX86DESCATTR;
#ifndef VBOX_FOR_DTRACE_LIB
/**
* Generic descriptor table entry
*/
#pragma pack(1)
typedef struct X86DESCGENERIC
{
/** 00 - Limit - Low word. */
unsigned u16LimitLow : 16;
/** 10 - Base address - lowe word.
* Don't try set this to 24 because MSC is doing stupid things then. */
unsigned u16BaseLow : 16;
/** 20 - Base address - first 8 bits of high word. */
unsigned u8BaseHigh1 : 8;
/** 28 - Segment Type. */
unsigned u4Type : 4;
unsigned u1DescType : 1;
/** 2d - Descriptor Privilege level. */
unsigned u2Dpl : 2;
/** 2f - Flags selector present(=1) or not. */
unsigned u1Present : 1;
/** 30 - Segment limit 16-19. */
unsigned u4LimitHigh : 4;
/** 34 - Available for system software. */
unsigned u1Available : 1;
/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
unsigned u1Long : 1;
/** 36 - This flags meaning depends on the segment type. Try make sense out
* of the intel manual yourself. */
unsigned u1DefBig : 1;
/** 37 - Granularity of the limit. If set 4KB granularity is used, if
* clear byte. */
unsigned u1Granularity : 1;
/** 38 - Base address - highest 8 bits. */
unsigned u8BaseHigh2 : 8;
#pragma pack()
/** Pointer to a generic descriptor entry. */
typedef X86DESCGENERIC *PX86DESCGENERIC;
/** Pointer to a const generic descriptor entry. */
typedef const X86DESCGENERIC *PCX86DESCGENERIC;
/** @name Bit offsets of X86DESCGENERIC members.
* @{*/
#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
/** @} */
/**
* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
*/
typedef struct X86DESCGATE
{
/** 00 - Target code segment offset - Low word.
* Ignored if task-gate. */
unsigned u16OffsetLow : 16;
/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
* TSS selector if task-gate. */
unsigned u16Sel : 16;
/** 20 - Number of parameters for a call-gate.
* Ignored if interrupt-, trap- or task-gate. */
unsigned u4ParmCount : 4;
/** 24 - Reserved / ignored. */
unsigned u4Reserved : 4;
/** 28 - Segment Type. */
unsigned u4Type : 4;
/** 2c - Descriptor Type (0 = system). */
unsigned u1DescType : 1;
/** 2d - Descriptor Privilege level. */
unsigned u2Dpl : 2;
/** 2f - Flags selector present(=1) or not. */
unsigned u1Present : 1;
/** 30 - Target code segment offset - High word.
* Ignored if task-gate. */
unsigned u16OffsetHigh : 16;
} X86DESCGATE;
/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
typedef X86DESCGATE *PX86DESCGATE;
/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
typedef const X86DESCGATE *PCX86DESCGATE;
#endif /* VBOX_FOR_DTRACE_LIB */
/**
* Descriptor table entry.
*/
#pragma pack(1)
typedef union X86DESC
{
#ifndef VBOX_FOR_DTRACE_LIB
/** Generic descriptor view. */
/** Gate descriptor view. */
#endif
/** 8 bit unsigned integer view. */
/** 16 bit unsigned integer view. */
/** 32 bit unsigned integer view. */
/** 64 bit unsigned integer view. */
/** Unsigned integer view. */
uint64_t u;
} X86DESC;
#ifndef VBOX_FOR_DTRACE_LIB
#endif
#pragma pack()
/** Pointer to descriptor table entry. */
/** Pointer to const descriptor table entry. */
/** @def X86DESC_BASE
* Return the base address of a descriptor.
*/
/** @def X86DESC_LIMIT
* Return the limit of a descriptor.
*/
/** @def X86DESC_LIMIT_G
* Return the limit of a descriptor with the granularity bit taken into account.
* @returns Selector limit (uint32_t).
* @param a_pDesc Pointer to the descriptor.
*/
? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
)
/** @def X86DESC_GET_HID_ATTR
* Get the descriptor attributes for the hidden register.
*/
#ifndef VBOX_FOR_DTRACE_LIB
/**
* 64 bits generic descriptor table entry
* Note: most of these bits have no meaning in long mode.
*/
#pragma pack(1)
typedef struct X86DESC64GENERIC
{
/** Limit - Low word - *IGNORED*. */
unsigned u16LimitLow : 16;
/** Base address - low word. - *IGNORED*
* Don't try set this to 24 because MSC is doing stupid things then. */
unsigned u16BaseLow : 16;
/** Base address - first 8 bits of high word. - *IGNORED* */
unsigned u8BaseHigh1 : 8;
/** Segment Type. */
unsigned u4Type : 4;
unsigned u1DescType : 1;
/** Descriptor Privilege level. */
unsigned u2Dpl : 2;
/** Flags selector present(=1) or not. */
unsigned u1Present : 1;
/** Segment limit 16-19. - *IGNORED* */
unsigned u4LimitHigh : 4;
/** Available for system software. - *IGNORED* */
unsigned u1Available : 1;
/** Long mode flag. */
unsigned u1Long : 1;
/** This flags meaning depends on the segment type. Try make sense out
* of the intel manual yourself. */
unsigned u1DefBig : 1;
/** Granularity of the limit. If set 4KB granularity is used, if
* clear byte. - *IGNORED* */
unsigned u1Granularity : 1;
/** Base address - highest 8 bits. - *IGNORED* */
unsigned u8BaseHigh2 : 8;
/** Base address - bits 63-32. */
unsigned u32BaseHigh3 : 32;
unsigned u8Reserved : 8;
unsigned u5Zeros : 5;
unsigned u19Reserved : 19;
#pragma pack()
/** Pointer to a generic descriptor entry. */
typedef X86DESC64GENERIC *PX86DESC64GENERIC;
/** Pointer to a const generic descriptor entry. */
typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
/**
* System descriptor table entry (64 bits)
*
* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
*/
#pragma pack(1)
typedef struct X86DESC64SYSTEM
{
/** Limit - Low word. */
unsigned u16LimitLow : 16;
/** Base address - lowe word.
* Don't try set this to 24 because MSC is doing stupid things then. */
unsigned u16BaseLow : 16;
/** Base address - first 8 bits of high word. */
unsigned u8BaseHigh1 : 8;
/** Segment Type. */
unsigned u4Type : 4;
unsigned u1DescType : 1;
/** Descriptor Privilege level. */
unsigned u2Dpl : 2;
/** Flags selector present(=1) or not. */
unsigned u1Present : 1;
/** Segment limit 16-19. */
unsigned u4LimitHigh : 4;
/** Available for system software. */
unsigned u1Available : 1;
/** Reserved - 0. */
unsigned u1Reserved : 1;
/** This flags meaning depends on the segment type. Try make sense out
* of the intel manual yourself. */
unsigned u1DefBig : 1;
/** Granularity of the limit. If set 4KB granularity is used, if
* clear byte. */
unsigned u1Granularity : 1;
/** Base address - bits 31-24. */
unsigned u8BaseHigh2 : 8;
/** Base address - bits 63-32. */
unsigned u32BaseHigh3 : 32;
unsigned u8Reserved : 8;
unsigned u5Zeros : 5;
unsigned u19Reserved : 19;
#pragma pack()
/** Pointer to a system descriptor entry. */
typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
/** Pointer to a const system descriptor entry. */
typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
/**
* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
*/
typedef struct X86DESC64GATE
{
/** Target code segment offset - Low word. */
unsigned u16OffsetLow : 16;
/** Target code segment selector. */
unsigned u16Sel : 16;
/** Interrupt stack table for interrupt- and trap-gates.
* Ignored by call-gates. */
unsigned u3IST : 3;
/** Reserved / ignored. */
unsigned u5Reserved : 5;
/** Segment Type. */
unsigned u4Type : 4;
/** Descriptor Type (0 = system). */
unsigned u1DescType : 1;
/** Descriptor Privilege level. */
unsigned u2Dpl : 2;
/** Flags selector present(=1) or not. */
unsigned u1Present : 1;
/** Target code segment offset - High word.
* Ignored if task-gate. */
unsigned u16OffsetHigh : 16;
/** Target code segment offset - Top dword.
* Ignored if task-gate. */
unsigned u32OffsetTop : 32;
/** Reserved / ignored / must be zero.
* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
unsigned u32Reserved : 32;
/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
typedef X86DESC64GATE *PX86DESC64GATE;
/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
typedef const X86DESC64GATE *PCX86DESC64GATE;
#endif /* VBOX_FOR_DTRACE_LIB */
/**
* Descriptor table entry.
*/
#pragma pack(1)
typedef union X86DESC64
{
#ifndef VBOX_FOR_DTRACE_LIB
/** Generic descriptor view. */
/** System descriptor view. */
/** Gate descriptor view. */
#endif
/** 8 bit unsigned integer view. */
/** 16 bit unsigned integer view. */
/** 32 bit unsigned integer view. */
/** 64 bit unsigned integer view. */
} X86DESC64;
#ifndef VBOX_FOR_DTRACE_LIB
#endif
#pragma pack()
/** Pointer to descriptor table entry. */
typedef X86DESC64 *PX86DESC64;
/** Pointer to const descriptor table entry. */
typedef const X86DESC64 *PCX86DESC64;
/** @def X86DESC64_BASE
* Return the base of a 64-bit descriptor.
*/
/** @name Host system descriptor table entry - Use with care!
* @{ */
/** Host system descriptor table entry. */
#if HC_ARCH_BITS == 64
#else
#endif
/** Pointer to a host system descriptor table entry. */
#if HC_ARCH_BITS == 64
typedef PX86DESC64 PX86DESCHC;
#else
typedef PX86DESC PX86DESCHC;
#endif
/** Pointer to a const host system descriptor table entry. */
#if HC_ARCH_BITS == 64
typedef PCX86DESC64 PCX86DESCHC;
#else
typedef PCX86DESC PCX86DESCHC;
#endif
/** @} */
/** @name Selector Descriptor Types.
* @{
*/
/** @name Non-System Selector Types.
* @{ */
/** Code(=set)/Data(=clear) bit. */
#define X86_SEL_TYPE_CODE 8
/** Memory(=set)/System(=clear) bit. */
/** Accessed bit. */
#define X86_SEL_TYPE_ACCESSED 1
/** Expand down bit (for data selectors only). */
#define X86_SEL_TYPE_DOWN 4
/** Conforming bit (for code selectors only). */
#define X86_SEL_TYPE_CONF 4
/** Write bit (for data selectors only). */
#define X86_SEL_TYPE_WRITE 2
/** Read bit (for code selectors only). */
#define X86_SEL_TYPE_READ 2
/** The bit number of the code segment read bit (relative to u4Type). */
#define X86_SEL_TYPE_READ_BIT 1
/** Read only selector type. */
#define X86_SEL_TYPE_RO 0
/** Accessed read only selector type. */
#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
/** Read write selector type. */
#define X86_SEL_TYPE_RW 2
/** Accessed read write selector type. */
/** Expand down read only selector type. */
#define X86_SEL_TYPE_RO_DOWN 4
/** Accessed expand down read only selector type. */
/** Expand down read write selector type. */
#define X86_SEL_TYPE_RW_DOWN 6
/** Accessed expand down read write selector type. */
/** Execute only selector type. */
#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
/** Accessed execute only selector type. */
/** Execute and read selector type. */
/** Accessed execute and read selector type. */
/** Conforming execute only selector type. */
/** Accessed Conforming execute only selector type. */
/** Conforming execute and write selector type. */
/** Accessed Conforming execute and write selector type. */
/** @} */
/** @name System Selector Types.
* @{ */
/** The TSS busy bit mask. */
#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
/** Undefined system selector type. */
#define X86_SEL_TYPE_SYS_UNDEFINED 0
/** 286 TSS selector. */
#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
/** LDT selector. */
#define X86_SEL_TYPE_SYS_LDT 2
/** 286 TSS selector - Busy. */
#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
/** 286 Callgate selector. */
#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
/** Taskgate selector. */
#define X86_SEL_TYPE_SYS_TASK_GATE 5
/** 286 Interrupt gate selector. */
#define X86_SEL_TYPE_SYS_286_INT_GATE 6
/** 286 Trapgate selector. */
#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
/** Undefined system selector. */
#define X86_SEL_TYPE_SYS_UNDEFINED2 8
/** 386 TSS selector. */
#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
/** Undefined system selector. */
#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
/** 386 TSS selector - Busy. */
#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
/** 386 Callgate selector. */
#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
/** Undefined system selector. */
#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
/** 386 Interruptgate selector. */
#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
/** 386 Trapgate selector. */
#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
/** @} */
/** @name AMD64 System Selector Types.
* @{ */
/** LDT selector. */
#define AMD64_SEL_TYPE_SYS_LDT 2
/** TSS selector - Busy. */
#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
/** TSS selector - Busy. */
#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
/** Callgate selector. */
#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
/** Interruptgate selector. */
#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
/** Trapgate selector. */
#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
/** @} */
/** @} */
/** @name Descriptor Table Entry Flag Masks.
* These are for the 2nd 32-bit word of a descriptor.
* @{ */
/** Bits 8-11 - TYPE - Descriptor type mask. */
/** Bits 13-14 - DPL - Descriptor Privilege Level. */
/** Bit 15 - P - Present. */
/** Bit 20 - AVL - Available for system software. */
/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
* used, if clear byte. */
/** @} */
/** @} */
/** @name Task Segments.
* @{
*/
/**
* The minimum TSS descriptor limit for 286 tasks.
*/
#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
/**
* The minimum TSS descriptor segment limit for 386 tasks.
*/
#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
/**
* 16-bit Task Segment (TSS).
*/
#pragma pack(1)
typedef struct X86TSS16
{
/** Back link to previous task. (static) */
/** Ring-0 stack pointer. (static) */
/** Ring-0 stack segment. (static) */
/** Ring-1 stack pointer. (static) */
/** Ring-1 stack segment. (static) */
/** Ring-2 stack pointer. (static) */
/** Ring-2 stack segment. (static) */
/** IP before task switch. */
/** FLAGS before task switch. */
/** AX before task switch. */
/** CX before task switch. */
/** DX before task switch. */
/** BX before task switch. */
/** SP before task switch. */
/** BP before task switch. */
/** SI before task switch. */
/** DI before task switch. */
/** ES before task switch. */
/** CS before task switch. */
/** SS before task switch. */
/** DS before task switch. */
/** LDTR before task switch. */
} X86TSS16;
#ifndef VBOX_FOR_DTRACE_LIB
#endif
#pragma pack()
/** Pointer to a 16-bit task segment. */
/** Pointer to a const 16-bit task segment. */
typedef const X86TSS16 *PCX86TSS16;
/**
* 32-bit Task Segment (TSS).
*/
#pragma pack(1)
typedef struct X86TSS32
{
/** Back link to previous task. (static) */
/** Ring-0 stack pointer. (static) */
/** Ring-0 stack segment. (static) */
/** Ring-1 stack pointer. (static) */
/** Ring-1 stack segment. (static) */
/** Ring-2 stack pointer. (static) */
/** Ring-2 stack segment. (static) */
/** Page directory for the task. (static) */
/** EIP before task switch. */
/** EFLAGS before task switch. */
/** EAX before task switch. */
/** ECX before task switch. */
/** EDX before task switch. */
/** EBX before task switch. */
/** ESP before task switch. */
/** EBP before task switch. */
/** ESI before task switch. */
/** EDI before task switch. */
/** ES before task switch. */
/** CS before task switch. */
/** SS before task switch. */
/** DS before task switch. */
/** FS before task switch. */
/** GS before task switch. */
/** LDTR before task switch. */
/** Debug trap flag */
/** Offset relative to the TSS of the start of the I/O Bitmap
* and the end of the interrupt redirection bitmap. */
/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
} X86TSS32;
#pragma pack()
/** Pointer to task segment. */
/** Pointer to const task segment. */
typedef const X86TSS32 *PCX86TSS32;
/**
* 64-bit Task segment.
*/
#pragma pack(1)
typedef struct X86TSS64
{
/** Reserved. */
/** Ring-0 stack pointer. (static) */
/** Ring-1 stack pointer. (static) */
/** Ring-2 stack pointer. (static) */
/** Reserved. */
/* IST */
/* Reserved. */
/** Offset relative to the TSS of the start of the I/O Bitmap
* and the end of the interrupt redirection bitmap. */
/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
} X86TSS64;
#pragma pack()
/** Pointer to a 64-bit task segment. */
/** Pointer to a const 64-bit task segment. */
typedef const X86TSS64 *PCX86TSS64;
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** @} */
/** @name Selectors.
* @{
*/
/**
* The shift used to convert a selector from and to index an index (C).
*/
#define X86_SEL_SHIFT 3
/**
* The mask used to mask off the table indicator and RPL of an selector.
*/
#define X86_SEL_MASK 0xfff8U
/**
* The mask used to mask off the RPL of an selector.
* This is suitable for checking for NULL selectors.
*/
#define X86_SEL_MASK_OFF_RPL 0xfffcU
/**
* The bit indicating that a selector is in the LDT and not in the GDT.
*/
#define X86_SEL_LDT 0x0004U
/**
* The bit mask for getting the RPL of a selector.
*/
#define X86_SEL_RPL 0x0003U
/**
* The mask covering both RPL and LDT.
* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
* checks.
*/
#define X86_SEL_RPL_LDT 0x0007U
/** @} */
/**
* x86 Exceptions/Faults/Traps.
*/
typedef enum X86XCPT
{
/** \#DE - Divide error. */
X86_XCPT_DE = 0x00,
/** \#DB - Debug event (single step, DRx, ..) */
X86_XCPT_DB = 0x01,
/** NMI - Non-Maskable Interrupt */
X86_XCPT_NMI = 0x02,
/** \#BP - Breakpoint (INT3). */
X86_XCPT_BP = 0x03,
/** \#OF - Overflow (INTO). */
X86_XCPT_OF = 0x04,
/** \#BR - Bound range exceeded (BOUND). */
X86_XCPT_BR = 0x05,
/** \#UD - Undefined opcode. */
X86_XCPT_UD = 0x06,
/** \#NM - Device not available (math coprocessor device). */
X86_XCPT_NM = 0x07,
/** \#DF - Double fault. */
X86_XCPT_DF = 0x08,
/** ??? - Coprocessor segment overrun (obsolete). */
X86_XCPT_CO_SEG_OVERRUN = 0x09,
/** \#TS - Taskswitch (TSS). */
X86_XCPT_TS = 0x0a,
/** \#NP - Segment no present. */
X86_XCPT_NP = 0x0b,
/** \#SS - Stack segment fault. */
X86_XCPT_SS = 0x0c,
/** \#GP - General protection fault. */
X86_XCPT_GP = 0x0d,
/** \#PF - Page fault. */
X86_XCPT_PF = 0x0e,
/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
/** \#MF - Math fault (FPU). */
X86_XCPT_MF = 0x10,
/** \#AC - Alignment check. */
X86_XCPT_AC = 0x11,
/** \#MC - Machine check. */
X86_XCPT_MC = 0x12,
/** \#XF - SIMD Floating-Pointer Exception. */
X86_XCPT_XF = 0x13,
/** \#VE - Virtualization Exception. */
X86_XCPT_VE = 0x14,
/** \#SX - Security Exception. */
X86_XCPT_SX = 0x1f
} X86XCPT;
/** Pointer to a x86 exception code. */
/** Pointer to a const x86 exception code. */
/** The maximum exception value. */
#define X86_XCPT_MAX (X86_XCPT_SX)
/** @name Trap Error Codes
* @{
*/
/** External indicator. */
#define X86_TRAP_ERR_EXTERNAL 1
/** IDT indicator. */
#define X86_TRAP_ERR_IDT 2
/** Descriptor table indicator - If set LDT, if clear GDT. */
#define X86_TRAP_ERR_TI 4
/** Mask for getting the selector. */
#define X86_TRAP_ERR_SEL_MASK 0xfff8
/** Shift for getting the selector table index (C type index). */
#define X86_TRAP_ERR_SEL_SHIFT 3
/** @} */
/** @name \#PF Trap Error Codes
* @{
*/
/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
#define X86_TRAP_PF_P RT_BIT(0)
/** Bit 1 - R/W - Read (clear) or write (set) access. */
/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
/** @} */
#pragma pack(1)
/**
* 16-bit IDTR.
*/
typedef struct X86IDTR16
{
/** Offset. */
/** Selector. */
} X86IDTR16, *PX86IDTR16;
#pragma pack()
#pragma pack(1)
/**
*/
typedef struct X86XDTR32
{
/** Size of the descriptor table. */
/** Address of the descriptor table. */
#ifndef VBOX_FOR_DTRACE_LIB
#else
#endif
} X86XDTR32, *PX86XDTR32;
#pragma pack()
#pragma pack(1)
/**
*/
typedef struct X86XDTR64
{
/** Size of the descriptor table. */
/** Address of the descriptor table. */
#ifndef VBOX_FOR_DTRACE_LIB
#else
#endif
} X86XDTR64, *PX86XDTR64;
#pragma pack()
/** @name ModR/M
* @{ */
#define X86_MODRM_REG_SHIFT 3
#define X86_MODRM_MOD_SHIFT 6
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** @} */
/** @name SIB
* @{ */
#define X86_SIB_INDEX_SHIFT 3
#define X86_SIB_SCALE_SHIFT 6
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** @} */
/** @name General register indexes
* @{ */
#define X86_GREG_xAX 0
#define X86_GREG_xCX 1
#define X86_GREG_xDX 2
#define X86_GREG_xBX 3
#define X86_GREG_xSP 4
#define X86_GREG_xBP 5
#define X86_GREG_xSI 6
#define X86_GREG_xDI 7
#define X86_GREG_x8 8
#define X86_GREG_x9 9
#define X86_GREG_x10 10
#define X86_GREG_x11 11
#define X86_GREG_x12 12
#define X86_GREG_x13 13
#define X86_GREG_x14 14
#define X86_GREG_x15 15
/** @} */
/** @name X86_SREG_XXX - Segment register indexes.
* @{ */
#define X86_SREG_ES 0
#define X86_SREG_CS 1
#define X86_SREG_SS 2
#define X86_SREG_DS 3
#define X86_SREG_FS 4
#define X86_SREG_GS 5
/** @} */
/** Segment register count. */
#define X86_SREG_COUNT 6
/** @name X86_OP_XXX - Prefixes
* @{ */
/** @} */
/** @} */
#endif