CPUM.cpp revision b213616e0471f3407de0b025f3fac4727c4f10f4
/* $Id$ */
/** @file
* CPUM - CPU Monitor / Manager.
*/
/*
* Copyright (C) 2006-2015 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/** @page pg_cpum CPUM - CPU Monitor / Manager
*
* The CPU Monitor / Manager keeps track of all the CPU registers. It is
* also responsible for lazy FPU handling and some of the context loading
* in raw mode.
*
* There are three CPU contexts, the most important one is the guest one (GC).
* When running in raw-mode (RC) there is a special hyper context for the VMM
* part that floats around inside the guest address space. When running in
* raw-mode, CPUM also maintains a host context for saving and restoring
* registers across world switches. This latter is done in cooperation with the
* world switcher (@see pg_vmm).
*
* @see grp_cpum
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_CPUM
#include "CPUMInternal.h"
#include <iprt/asm-amd64-x86.h>
/*******************************************************************************
* Defined Constants And Macros *
*******************************************************************************/
/**
* This was used in the saved state up to the early life of version 14.
*
* It indicates that we may have some out-of-sync hidden segement registers.
* It is only relevant for raw-mode.
*/
/*******************************************************************************
* Structures and Typedefs *
*******************************************************************************/
/**
* What kind of cpu info dump to perform.
*/
typedef enum CPUMDUMPTYPE
{
} CPUMDUMPTYPE;
/** Pointer to a cpu info dump type. */
typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
/*******************************************************************************
* Global Variables *
*******************************************************************************/
/** Saved state field descriptors for CPUMCTX. */
static const SSMFIELD g_aCpumX87Fields[] =
{
};
/** Saved state field descriptors for CPUMCTX. */
static const SSMFIELD g_aCpumCtxFields[] =
{
/* msrApicBase is not included here, it resides in the APIC device state. */
};
/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
* registeres changed. */
static const SSMFIELD g_aCpumX87FieldsMem[] =
{
};
/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
* registeres changed. */
static const SSMFIELD g_aCpumCtxFieldsMem[] =
{
};
/** Saved state field descriptors for CPUMCTX_VER1_6. */
static const SSMFIELD g_aCpumX87FieldsV16[] =
{
};
/** Saved state field descriptors for CPUMCTX_VER1_6. */
static const SSMFIELD g_aCpumCtxFieldsV16[] =
{
};
/**
*
* (last instruction pointer, last data pointer, last opcode) except when the ES
* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
* clear these registers there is potential, local FPU leakage from a process
* using the FPU to another.
*
* See AMD Instruction Reference for FXSAVE, FXRSTOR.
*
* @param pVM Pointer to the VM.
*/
{
&& ASMIsAmdCpu())
{
if (ASMIsValidExtRange(cExt))
{
{
}
}
}
}
/**
* Initializes the CPUM.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
LogFlow(("CPUMR3Init\n"));
/*
* Assert alignment, sizes and tables.
*/
#ifdef VBOX_STRICT
int rc2 = cpumR3MsrStrictInitChecks();
#endif
/*
* Initialize offsets.
*/
/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
/* Calculate the offset from CPUMCPU to CPUM. */
{
}
/*
* Gather info about the host CPU.
*/
if (!ASMHasCpuId())
{
Log(("The CPU doesn't support CPUID!\n"));
return VERR_UNSUPPORTED_CPU;
}
/*
* Check that the CPU supports the minimum features we require.
*/
return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
/* Bogus on AMD? */
/*
* Setup the CR4 AND and OR masks used in the switcher
*/
/*
* Allocate memory for the extended CPU state.
*/
MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
{
pbXStates += cbMaxXState;
pbXStates += cbMaxXState;
pbXStates += cbMaxXState;
}
/*
* Setup hypervisor startup values.
*/
/*
* Register saved state data item.
*/
if (RT_FAILURE(rc))
return rc;
/*
* Register info handlers and registers with the debugger facility.
*/
DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
if (RT_FAILURE(rc))
return rc;
/*
*/
/*
* Initialize the Guest CPUID and MSR states.
*/
if (RT_FAILURE(rc))
return rc;
return VINF_SUCCESS;
}
/**
* Applies relocations to data and code managed by this
* component. This function will be called at init and
* whenever the VMM need to relocate it self inside the GC.
*
* The CPUM will update the addresses used by the switcher.
*
* @param pVM The VM.
*/
{
LogFlow(("CPUMR3Relocate\n"));
{
pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
/* Recheck the guest DRx values in raw-mode. */
}
}
/**
* Apply late CPUM property changes based on the fHWVirtEx setting
*
* @param pVM Pointer to the VM.
*/
{
/*
* Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
* of processors from (cpuid(4).eax >> 26) + 1.
*
* Note: this code is obsolete, but let's keep it here for reference.
* Purpose is valid when we artificially cap the max std id to less than 4.
*/
if (!fHWVirtExEnabled)
{
}
}
/**
* Terminates the CPUM.
*
* Termination means cleaning up and freeing all resources,
* the VM it self is at this point powered off or suspended.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
{
}
#else
#endif
return VINF_SUCCESS;
}
/**
* Resets a virtual CPU.
*
* Used by CPUMR3Reset and CPU hot plugging.
*
* @param pVM Pointer to the cross context VM structure.
* @param pVCpu Pointer to the cross context virtual CPU structure of
* the CPU that is being reset. This may differ from the
* current EMT.
*/
{
/** @todo anything different for VCPU > 0? */
/*
* Initialize everything to ZERO first.
*/
pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
IA-32 Processor States Following Power-up, Reset, or INIT */
pFpuCtx->MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
supports all bits, since a zero value here should be read as 0xffbf. */
/*
* MSRs.
*/
/* Init PAT MSR */
/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
* The Intel docs don't mention it. */
if (pRange)
{
}
/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
* called from each EMT while we're getting called by CPUMR3Reset()
* iteratively on the same thread. Fix later. */
#if 0 /** @todo r=bird: This we will do in TM, not here. */
/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
#endif
/* C-state control. Guesses. */
pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
/*
* Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
* continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
*/
}
/**
* Resets the CPU.
*
* @returns VINF_SUCCESS.
* @param pVM Pointer to the VM.
*/
{
{
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
/* Magic marker for searching in crash dumps. */
#endif
}
}
/**
* Pass 0 live exec callback.
*
* @returns VINF_SSM_DONT_CALL_AGAIN.
* @param pVM Pointer to the VM.
* @param pSSM The saved state handle.
* @param uPass The pass (0).
*/
{
return VINF_SSM_DONT_CALL_AGAIN;
}
/**
* Execute state save operation.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pSSM SSM operation handle.
*/
{
/*
* Save.
*/
{
SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
}
{
SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), 0, g_aCpumCtxFields, NULL);
}
return VINF_SUCCESS;
}
/**
* @copydoc FNSSMINTLOADPREP
*/
{
return VINF_SUCCESS;
}
/**
* @copydoc FNSSMINTLOADEXEC
*/
static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
{
/*
* Validate version.
*/
if ( uVersion != CPUM_SAVED_STATE_VERSION
{
}
if (uPass == SSM_PASS_FINAL)
{
/*
* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
* really old SSM file versions.)
*/
else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
{
}
else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
{
}
/*
* Restore.
*/
{
/** @todo drop the FPU bits here! */
SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper.pXStateR3->x87, sizeof(pVCpu->cpum.s.Hyper.pXStateR3->x87),
}
{
AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
}
{
AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
}
{
SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest.pXStateR3->x87, sizeof(pVCpu->cpum.s.Guest.pXStateR3->x87),
else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
{
}
/* REM and other may have cleared must-be-one fields in DR6 and
DR7, fix these. */
}
/* Older states does not have the internal selector register flags
and valid selector value. Supply those. */
if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
{
{
if (fValid)
{
{
}
}
else
{
{
}
/* This might not be 104% correct, but I think it's close
enough for all practical purposes... (REM always loaded
LDTR registers.) */
}
}
}
/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
/*
* A quick sanity check.
*/
{
AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
}
}
/*
* Guest CPUIDs.
*/
/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
* actually required. */
/*
* Restore the CPUID leaves.
*
* Note that we support restoring less than the current amount of standard
* leaves because we've been allowed more is newer version of VBox.
*/
SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
/*
* Check that the basic cpuid id information is unchanged.
*/
/** @todo we should check the 64 bits capabilities too! */
if (RT_SUCCESS(rc))
{
/* Ignore CPU stepping. */
/* Ignore APIC ID (AMD specs). */
/* Ignore the number of Logical CPUs (AMD specs). */
/* Ignore some advanced capability bits, that we don't expose to the guest. */
);
);
/* Make sure we don't forget to update the masks when enabling
* features in the future.
*/
)));
/* do the compare */
{
LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
"Saved=%.*Rhxs\n"
"Real =%.*Rhxs\n",
sizeof(au32CpuIdSaved), au32CpuIdSaved,
else
{
LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
"Saved=%.*Rhxs\n"
"Real =%.*Rhxs\n",
sizeof(au32CpuIdSaved), au32CpuIdSaved,
}
}
}
return rc;
}
/**
* @copydoc FNSSMINTLOADPREP
*/
{
return VINF_SUCCESS;
/* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
{
LogRel(("CPUM: Missing state!\n"));
return VERR_INTERNAL_ERROR_2;
}
{
/* Notify PGM of the NXE states in case they've changed. */
/* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
/* During init. this is done in CPUMR3InitCompleted(). */
if (fSupportsLongMode)
}
return VINF_SUCCESS;
}
/**
* Checks if the CPUM state restore is still pending.
*
* @returns true / false.
* @param pVM Pointer to the VM.
*/
{
}
/**
* Formats the EFLAGS value into mnemonics.
*
* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
* @param efl The EFLAGS value.
*/
{
/*
* Format the flags.
*/
static const struct
{
} s_aFlags[] =
{
};
for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
{
if (pszAdd)
{
*psz++ = ' ';
}
}
}
/**
* Formats a full register dump.
*
* @param pVM Pointer to the VM.
* @param pCtx The context to format.
* @param pCtxCore The context core to format.
* @param pHlp Output functions.
* @param enmType The dump type.
* @param pszPrefix Register name prefix.
*/
static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
const char *pszPrefix)
{
/*
* Format the EFLAGS.
*/
char szEFlags[80];
/*
* Format the registers.
*/
switch (enmType)
{
case CPUMDUMPTYPE_TERSE:
if (CPUMIsGuestIn64BitCodeEx(pCtx))
"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
"%sr14=%016RX64 %sr15=%016RX64\n"
"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
else
"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
break;
case CPUMDUMPTYPE_DEFAULT:
if (CPUMIsGuestIn64BitCodeEx(pCtx))
"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
"%sr14=%016RX64 %sr15=%016RX64\n"
"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
,
pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
else
"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
,
pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
break;
case CPUMDUMPTYPE_VERBOSE:
if (CPUMIsGuestIn64BitCodeEx(pCtx))
"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
"%sr14=%016RX64 %sr15=%016RX64\n"
"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
,
pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
else
"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
,
pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
,
);
{
/** @todo This isn't entirenly correct and needs more work! */
"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
else
}
iXMM & 1
? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
if (pFpuCtx->au32RsrvdRest[i])
"%sEFER =%016RX64\n"
"%sPAT =%016RX64\n"
"%sSTAR =%016RX64\n"
"%sCSTAR =%016RX64\n"
"%sLSTAR =%016RX64\n"
"%sSFMASK =%016RX64\n"
"%sKERNELGSBASE =%016RX64\n",
break;
}
}
/**
* Display all cpu states and any other cpum info.
*
* @param pVM Pointer to the VM.
* @param pHlp The info helper functions.
* @param pszArgs Arguments, ignored.
*/
{
}
/**
* Parses the info argument.
*
* The argument starts with 'verbose', 'terse' or 'default' and then
* continues with the comment string.
*
* @param pszArgs The pointer to the argument string.
* @param penmType Where to store the dump type request.
* @param ppszComment Where to store the pointer to the comment string.
*/
static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
{
if (!pszArgs)
{
*ppszComment = "";
}
else
{
{
pszArgs += 7;
}
{
pszArgs += 5;
}
{
pszArgs += 7;
}
else
}
}
/**
* Display the guest cpu state.
*
* @param pVM Pointer to the VM.
* @param pHlp The info helper functions.
* @param pszArgs Arguments, ignored.
*/
{
const char *pszComment;
/* @todo SMP support! */
if (!pVCpu)
}
/**
* Display the current guest instruction
*
* @param pVM Pointer to the VM.
* @param pHlp The info helper functions.
* @param pszArgs Arguments, ignored.
*/
{
/** @todo SMP support! */
if (!pVCpu)
char szInstruction[256];
szInstruction[0] = '\0';
}
/**
* Display the hypervisor cpu state.
*
* @param pVM Pointer to the VM.
* @param pHlp The info helper functions.
* @param pszArgs Arguments, ignored.
*/
{
const char *pszComment;
/* @todo SMP */
pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
}
/**
* Display the host cpu state.
*
* @param pVM Pointer to the VM.
* @param pHlp The info helper functions.
* @param pszArgs Arguments, ignored.
*/
{
const char *pszComment;
/*
* Format the EFLAGS.
*/
/* @todo SMP */
#if HC_ARCH_BITS == 32
#else
#endif
char szEFlags[80];
/*
* Format the registers.
*/
#if HC_ARCH_BITS == 32
# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
# endif
{
"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
,
}
# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
else
# endif
#endif
{
"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
"r14=%016RX64 r15=%016RX64\n"
"iopl=%d %31s\n"
"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
"cr4=%016RX64 ldtr=%04x tr=%04x\n"
"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
,
}
#endif
}
/**
* Structure used when disassembling and instructions in DBGF.
* This is used so the reader function can get the stuff it needs.
*/
typedef struct CPUMDISASSTATE
{
/** Pointer to the CPU structure. */
/** Pointer to the VM. */
/** Pointer to the VMCPU. */
/** Pointer to the first byte in the segment. */
/** Pointer to the byte after the end of the segment. (might have wrapped!) */
/** The size of the segment minus 1. */
/** Pointer to the current page - R3 Ptr. */
void const *pvPageR3;
/** Pointer to the current page - GC Ptr. */
/** The lock information that PGMPhysReleasePageMappingLock needs. */
/** Whether the PageMapLock is valid or not. */
bool fLocked;
/** 64 bits mode or not. */
bool f64Bits;
/**
* @callback_method_impl{FNDISREADBYTES}
*/
static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
{
for (;;)
{
/*
* Need to update the page translation?
*/
{
int rc = VINF_SUCCESS;
/* translate the address */
{
}
else
{
/* Release mapping lock previously acquired. */
rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
}
if (RT_FAILURE(rc))
{
return rc;
}
}
/*
* Check the segment limit.
*/
return VERR_OUT_OF_SELECTOR_BOUNDS;
/*
* Calc how much we can read.
*/
{
}
/*
* Read and advance or exit.
*/
{
return VINF_SUCCESS;
}
}
}
/**
* Disassemble an instruction and return the information in the provided structure.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the guest CPU context.
* @param GCPtrPC Program counter (relative to CS) to disassemble from.
* @param pCpu Disassembly state.
* @param pszPrefix String prefix for logging (debug only).
*
*/
VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
{
int rc;
/*
* Get selector information.
*/
{
{
# ifdef VBOX_WITH_RAW_MODE_NOT_R0
# endif
return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
}
}
else
{
/* real or V86 mode */
}
/*
* Disassemble the instruction.
*/
#ifndef LOG_ENABLED
if (RT_SUCCESS(rc))
{
#else
char szOutput[160];
if (RT_SUCCESS(rc))
{
/* log it */
if (pszPrefix)
else
#endif
rc = VINF_SUCCESS;
}
else
/* Release mapping lock acquired in cpumR3DisasInstrRead. */
return rc;
}
/**
* API for controlling a few of the CPU features found in CR4.
*
* Currently only X86_CR4_TSD is accepted as input.
*
* @returns VBox status code.
*
* @param pVM Pointer to the VM.
* @param fOr The CR4 OR mask.
* @param fAnd The CR4 AND mask.
*/
{
AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
return VINF_SUCCESS;
}
/**
* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
*
* Only REM should ever call this function!
*
* @returns The changed flags.
* @param pVCpu Pointer to the VMCPU.
* @param puCpl Where to return the current privilege level (CPL).
*/
{
/*
* Get the CPL first.
*/
/*
* Get and reset the flags.
*/
/** @todo change the switcher to use the fChanged flags. */
{
}
return fFlags;
}
/**
* Leaves REM.
*
* @param pVCpu Pointer to the VMCPU.
* @param fNoOutOfSyncSels This is @c false if there are out of sync
* registers.
*/
{
}
/**
* Called when the ring-3 init phase completes.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
/*
* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
*/
{
/* Cache the APIC base (from the APIC device) once it has been initialized. */
Log(("CPUMR3InitCompleted pVM=%p APIC base[%u]=%RX64\n", pVM, (unsigned)i, pVCpu->cpum.s.Guest.msrApicBase));
/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
if (fSupportsLongMode)
}
return VINF_SUCCESS;
}
/**
* Called when the ring-0 init phases comleted.
*
* @param pVM Pointer to the VM.
*/
{
/*
* Log the cpuid.
*/
LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
if (cCores)
LogRel(("************************* CPUID dump ************************\n"));
LogRel(("\n"));
LogRel(("******************** End of CPUID dump **********************\n"));
}