CPUMR3CpuId.cpp revision 41d680dd6eb0287afc200adc5b0d61b07a32b72d
/* $Id$ */
/** @file
* CPUM - CPU ID part.
*/
/*
* Copyright (C) 2013 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_CPUM
#include "CPUMInternal.h"
#include <iprt/asm-amd64-x86.h>
/*******************************************************************************
* Global Variables *
*******************************************************************************/
/**
* The intel pentium family.
*/
static const CPUMMICROARCH g_aenmIntelFamily06[] =
{
/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
/* [31(0x1f)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
/* [45(0x2d)] = */ kCpumMicroarch_Intel_Core7_SandyBridge, /* SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
/* [71(0x47)] = */ kCpumMicroarch_Intel_Unknown,
/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
/* [76(0x4c)] = */ kCpumMicroarch_Intel_Unknown,
/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
/* [78(0x4e)] = */ kCpumMicroarch_Intel_Unknown,
/* [79(0x4f)] = */ kCpumMicroarch_Intel_Unknown,
};
/**
* Figures out the (sub-)micro architecture given a bit of CPUID info.
*
* @returns Micro architecture.
* @param enmVendor The CPU vendor .
* @param bFamily The CPU family.
* @param bModel The CPU model.
* @param bStepping The CPU stepping.
*/
{
if (enmVendor == CPUMCPUVENDOR_AMD)
{
switch (bFamily)
{
case 0x03: return kCpumMicroarch_AMD_Am386;
case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
case 0x06:
switch (bModel)
{
case 0: kCpumMicroarch_AMD_K7_Palomino;
case 1: kCpumMicroarch_AMD_K7_Palomino;
case 2: kCpumMicroarch_AMD_K7_Palomino;
case 3: kCpumMicroarch_AMD_K7_Spitfire;
case 4: kCpumMicroarch_AMD_K7_Thunderbird;
case 6: kCpumMicroarch_AMD_K7_Palomino;
case 7: kCpumMicroarch_AMD_K7_Morgan;
case 8: kCpumMicroarch_AMD_K7_Thoroughbred;
}
return kCpumMicroarch_AMD_K7_Unknown;
case 0x0f:
/*
* This family is a friggin mess. Trying my best to make some
* sense out of it. Too much happened in the 0x0f family to
* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
*
* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
* cpu-world.com, and other places:
* - 130nm:
* - 90nm:
* - 90nm introducing Dual core:
* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheeper models):
*
* - 65nm:
*/
if (bModel < 0x10)
return kCpumMicroarch_AMD_K8_130nm;
return kCpumMicroarch_AMD_K8_65nm;
if (bModel >= 0x40)
return kCpumMicroarch_AMD_K8_90nm_AMDV;
switch (bModel)
{
case 0x21:
case 0x23:
case 0x2b:
case 0x2f:
case 0x37:
case 0x3f:
}
return kCpumMicroarch_AMD_K8_90nm;
case 0x10:
return kCpumMicroarch_AMD_K10;
case 0x11:
return kCpumMicroarch_AMD_K10_Lion;
case 0x12:
return kCpumMicroarch_AMD_K10_Llano;
case 0x14:
return kCpumMicroarch_AMD_Bobcat;
case 0x15:
switch (bModel)
{
case 0x11: /* ?? */
case 0x12: /* ?? */
}
return kCpumMicroarch_AMD_15h_Unknown;
case 0x16:
return kCpumMicroarch_AMD_Jaguar;
}
return kCpumMicroarch_AMD_Unknown;
}
if (enmVendor == CPUMCPUVENDOR_INTEL)
{
switch (bFamily)
{
case 3:
return kCpumMicroarch_Intel_80386;
case 4:
return kCpumMicroarch_Intel_80486;
case 5:
return kCpumMicroarch_Intel_P5;
case 6:
return g_aenmIntelFamily06[bModel];
case 15:
switch (bModel)
{
case 0: return kCpumMicroarch_Intel_NB_Willamette;
case 1: return kCpumMicroarch_Intel_NB_Willamette;
case 2: return kCpumMicroarch_Intel_NB_Northwood;
case 3: return kCpumMicroarch_Intel_NB_Prescott;
case 6: return kCpumMicroarch_Intel_NB_CedarMill;
case 7: return kCpumMicroarch_Intel_NB_Gallatin;
default: return kCpumMicroarch_Intel_NB_Unknown;
}
break;
/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
case 1:
return kCpumMicroarch_Intel_8086;
case 2:
return kCpumMicroarch_Intel_80286;
}
return kCpumMicroarch_Intel_Unknown;
}
if (enmVendor == CPUMCPUVENDOR_VIA)
{
switch (bFamily)
{
case 5:
switch (bModel)
{
case 1: return kCpumMicroarch_Centaur_C6;
case 4: return kCpumMicroarch_Centaur_C6;
case 8: return kCpumMicroarch_Centaur_C2;
case 9: return kCpumMicroarch_Centaur_C3;
}
break;
case 6:
switch (bModel)
{
case 5: return kCpumMicroarch_VIA_C3_M2;
case 6: return kCpumMicroarch_VIA_C3_C5A;
case 8: return kCpumMicroarch_VIA_C3_C5N;
case 10: return kCpumMicroarch_VIA_C7_C5J;
case 15: return kCpumMicroarch_VIA_Isaiah;
}
break;
}
return kCpumMicroarch_VIA_Unknown;
}
if (enmVendor == CPUMCPUVENDOR_CYRIX)
{
switch (bFamily)
{
case 4:
switch (bModel)
{
case 9: return kCpumMicroarch_Cyrix_5x86;
}
break;
case 5:
switch (bModel)
{
case 2: return kCpumMicroarch_Cyrix_M1;
case 4: return kCpumMicroarch_Cyrix_MediaGX;
case 5: return kCpumMicroarch_Cyrix_MediaGXm;
}
break;
case 6:
switch (bModel)
{
case 0: return kCpumMicroarch_Cyrix_M2;
}
break;
}
return kCpumMicroarch_Cyrix_Unknown;
}
return kCpumMicroarch_Unknown;
}
/**
* Translates a microarchitecture enum value to the corresponding string
* constant.
*
* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
* NULL if the value is invalid.
*
* @param enmMicroarch The enum value to convert.
*/
{
switch (enmMicroarch)
{
case kCpumMicroarch_Invalid:
case kCpumMicroarch_Intel_End:
case kCpumMicroarch_AMD_End:
case kCpumMicroarch_VIA_End:
case kCpumMicroarch_Cyrix_End:
case kCpumMicroarch_32BitHack:
break;
/* no default! */
}
return NULL;
}
/**
* Gets a matching leaf in the CPUID leaf array.
*
* @returns Pointer to the matching leaf, or NULL if not found.
* @param paLeaves The CPUID leaves to search. This is sorted.
* @param cLeaves The number of leaves in the array.
* @param uLeaf The leaf to locate.
* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
*/
PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
{
/* Lazy bird does linear lookup here since this is only used for the
occational CPUID overrides. */
return &paLeaves[i];
return NULL;
}
/**
* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
*
* @returns true if found, false it not.
* @param paLeaves The CPUID leaves to search. This is sorted.
* @param cLeaves The number of leaves in the array.
* @param uLeaf The leaf to locate.
* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
* @param pLegacy The legacy output leaf.
*/
bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf, PCPUMCPUID pLeagcy)
{
if (pLeaf)
{
return true;
}
return false;
}
/**
* Ensures that the CPUID leaf array can hold one more leaf.
*
* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
* failure.
* @param ppaLeaves Pointer to the variable holding the array
* @param cLeaves The current array size.
*/
{
{
if (!pvNew)
{
return NULL;
}
}
return *ppaLeaves;
}
/**
* Append a CPUID leaf or sub-leaf.
*
* ASSUMES linear insertion order, so we'll won't need to do any searching or
* replace anything. Use cpumR3CpuIdInsert for those cases.
*
* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
* the caller need do no more work.
* @param ppaLeaves Pointer to the the pointer to the array of sorted
* CPUID leaves and sub-leaves.
* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
* @param uLeaf The leaf we're adding.
* @param uSubLeaf The sub-leaf number.
* @param fSubLeafMask The sub-leaf mask.
* @param uEax The EAX value.
* @param uEbx The EBX value.
* @param uEcx The ECX value.
* @param uEdx The EDX value.
* @param fFlags The flags.
*/
{
return VERR_NO_MEMORY;
*pcLeaves += 1;
return VINF_SUCCESS;
}
/**
* Inserts a CPU ID leaf, replacing any existing ones.
*
* When inserting a simple leaf where we already got a series of subleaves with
* the same leaf number (eax), the simple leaf will replace the whole series.
*
* This ASSUMES that the leave array is still on the normal heap and has only
* been allocated/reallocated by the cpumR3CpuIdEnsureSpace function.
*
* @returns VBox status code.
* @param ppaLeaves Pointer to the the pointer to the array of sorted
* CPUID leaves and sub-leaves.
* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
* @param pNewLeaf Pointer to the data of the new leaf we're about to
* insert.
*/
{
/*
* Validate the new leaf a little.
*/
AssertReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf, VERR_INVALID_PARAMETER);
/*
* Find insertion point. The lazy bird uses the same excuse as in
* cpumR3CpuIdGetLeaf().
*/
uint32_t i = 0;
while ( i < cLeaves
i++;
if ( i < cLeaves
{
{
/*
* The subleaf mask differs, replace all existing leaves with the
* same leaf number.
*/
uint32_t c = 1;
while ( i + c < cLeaves
c++;
if (c > 1 && i + c < cLeaves)
{
}
return VINF_SUCCESS;
}
/* Find subleaf insertion point. */
while ( i < cLeaves
i++;
/*
* If we've got an exactly matching leaf, replace it.
*/
{
return VINF_SUCCESS;
}
}
/*
* Adding a new leaf at 'i'.
*/
if (!paLeaves)
return VERR_NO_MEMORY;
if (i < cLeaves)
*pcLeaves += 1;
return VINF_SUCCESS;
}
/**
* Removes a range of CPUID leaves.
*
* This will not reallocate the array.
*
* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
* @param pcLeaves Where we keep the leaf count for @a paLeaves.
* @param uFirst The first leaf.
* @param uLast The last leaf.
*/
void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
{
/*
* Find the first one.
*/
iFirst++;
/*
* Find the end (last + 1).
*/
iEnd++;
/*
* Adjust the array if anything needs removing.
*/
{
}
}
/**
* Checks if ECX make a difference when reading a given CPUID leaf.
*
* @returns @c true if it does, @c false if it doesn't.
* @param uLeaf The leaf we're reading.
* @param pcSubLeaves Number of sub-leaves accessible via ECX.
* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
* final sub-leaf.
*/
static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t *pcSubLeaves, bool *pfFinalEcxUnchanged)
{
*pfFinalEcxUnchanged = false;
/* Look for sub-leaves. */
for (;;)
{
break;
/* Advance / give up. */
uSubLeaf++;
if (uSubLeaf >= 64)
{
*pcSubLeaves = 1;
return false;
}
}
/* Count sub-leaves. */
uSubLeaf = 0;
for (;;)
{
/* Exactly when this terminates isn't quite consistent. When working
0xb, we should probably only check if ebx == 0... */
if ( auCur[0] == 0
&& auCur[1] == 0
{
*pfFinalEcxUnchanged = true;
return true;
}
/* Advance / give up. */
uSubLeaf++;
if (uSubLeaf >= 128)
{
return true;
}
}
}
/**
* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
*
* @returns VBox status code.
* @param ppaLeaves Where to return the array pointer on success.
* Use RTMemFree to release.
* @param pcLeaves Where to return the size of the array on
* success.
*/
{
*pcLeaves = 0;
/*
* Try out various candidates. This must be sorted!
*/
{
{ UINT32_C(0x00000000), false },
{ UINT32_C(0x10000000), false },
{ UINT32_C(0x20000000), false },
{ UINT32_C(0x30000000), false },
{ UINT32_C(0x40000000), false },
{ UINT32_C(0x50000000), false },
{ UINT32_C(0x60000000), false },
{ UINT32_C(0x70000000), false },
{ UINT32_C(0x80000000), false },
{ UINT32_C(0x80860000), false },
{ UINT32_C(0x8ffffffe), true },
{ UINT32_C(0x8fffffff), true },
{ UINT32_C(0x90000000), false },
{ UINT32_C(0xa0000000), false },
{ UINT32_C(0xb0000000), false },
{ UINT32_C(0xc0000000), false },
{ UINT32_C(0xd0000000), false },
{ UINT32_C(0xe0000000), false },
{ UINT32_C(0xf0000000), false },
};
{
/*
* Does EAX look like a typical leaf count value?
*/
{
/* Yes, dump them. */
while (cLeaves-- > 0)
{
/* Check three times here to reduce the chance of CPU migration
resulting in false positives with things like the APIC ID. */
bool fFinalEcxUnchanged;
{
if (cSubLeaves > 16)
{
if (RT_FAILURE(rc))
return rc;
}
}
else
{
if (RT_FAILURE(rc))
return rc;
}
/* next */
uLeaf++;
}
}
/*
* Special CPUIDs needs special handling as they don't follow the
* leaf count principle used above.
*/
{
bool fKeep = false;
fKeep = true;
else if ( uLeaf == 0x8fffffff
fKeep = true;
if (fKeep)
{
if (RT_FAILURE(rc))
return rc;
}
}
}
return VINF_SUCCESS;
}
/**
* Determines the method the CPU uses to handle unknown CPUID leaves.
*
* @returns VBox status code.
* @param penmUnknownMethod Where to return the method.
* @param pDefUnknown Where to return default unknown values. This
* will be set, even if the resulting method
* doesn't actually needs it.
*/
VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
{
if (!ASMIsValidExtRange(uLastExt))
uLastExt = 0x80000000;
{
uLastStd + 1,
uLastStd + 5,
uLastStd + 8,
uLastStd + 32,
uLastStd + 251,
uLastExt + 1,
uLastExt + 8,
uLastExt + 15,
uLastExt + 63,
uLastExt + 255,
0x7fbbffcc,
0x833f7872,
0xefff2353,
0x35779456,
0x1ef6d33e,
};
static const uint32_t s_auValues[] =
{
0xa95d2156,
0x00000001,
0x00000002,
0x00000008,
0x00000000,
0x55773399,
0x93401769,
0x12039587,
};
/*
* Simple method, all zeros.
*/
pDefUnknown->eax = 0;
pDefUnknown->ebx = 0;
pDefUnknown->ecx = 0;
pDefUnknown->edx = 0;
/*
* Intel has been observed returning the last standard leaf.
*/
while (cChecks > 0)
{
break;
cChecks--;
}
if (cChecks == 0)
{
/* Now, what happens when the input changes? Esp. ECX. */
uint32_t cLastWithEcx = 0;
while (cValues > 0)
{
while (cChecks > 0)
{
ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
{
cSame++;
cLastWithEcx++;
}
cLastWithEcx++;
else
cNeither++;
cTotal++;
cChecks--;
}
cValues--;
}
RTStrmPrintf(g_pStdErr, "cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal);
else if (cLastWithEcx == cTotal)
else
return VINF_SUCCESS;
}
/*
* Unchanged register values?
*/
while (cChecks > 0)
{
while (cValues > 0)
{
break;
cValues--;
}
if (cValues != 0)
break;
cChecks--;
}
if (cChecks == 0)
{
return VINF_SUCCESS;
}
/*
* Just go with the simple method.
*/
return VINF_SUCCESS;
}
/**
* Translates a unknow CPUID leaf method into the constant name (sans prefix).
*
* @returns Read only name string.
* @param enmUnknownMethod The method to translate.
*/
{
switch (enmUnknownMethod)
{
case CPUMUKNOWNCPUID_DEFAULTS: return "DEFAULTS";
case CPUMUKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
case CPUMUKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
case CPUMUKNOWNCPUID_PASSTHRU: return "PASSTHRU";
case CPUMUKNOWNCPUID_INVALID:
case CPUMUKNOWNCPUID_END:
break;
}
return "Invalid-unknown-CPUID-method";
}
/**
* Detect the CPU vendor give n the
*
* @returns The vendor.
* @param uEAX EAX from CPUID(0).
* @param uEBX EBX from CPUID(0).
* @param uECX ECX from CPUID(0).
* @param uEDX EDX from CPUID(0).
*/
VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
{
if (ASMIsValidStdRange(uEAX))
{
return CPUMCPUVENDOR_AMD;
return CPUMCPUVENDOR_INTEL;
return CPUMCPUVENDOR_VIA;
return CPUMCPUVENDOR_CYRIX;
/* "Geode by NSC", example: family 5, model 9. */
/** @todo detect the other buggers... */
}
return CPUMCPUVENDOR_UNKNOWN;
}
/**
* Translates a CPU vendor enum value into the corresponding string constant.
*
* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
* value name. This can be useful when generating code.
*
* @returns Read only name string.
* @param enmVendor The CPU vendor value.
*/
{
switch (enmVendor)
{
case CPUMCPUVENDOR_INTEL: return "INTEL";
case CPUMCPUVENDOR_AMD: return "AMD";
case CPUMCPUVENDOR_VIA: return "VIA";
case CPUMCPUVENDOR_CYRIX: return "CYRIX";
case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
case CPUMCPUVENDOR_INVALID:
case CPUMCPUVENDOR_32BIT_HACK:
break;
}
return "Invalid-cpu-vendor";
}
static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
{
/* Could do binary search, doing linear now because I'm lazy. */
while (cLeaves-- > 0)
{
return pLeaf;
pLeaf++;
}
return NULL;
}
{
if (cLeaves >= 2)
{
pFeatures->uModel = ASMGetCpuModel(paLeaves[1].uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
if (pLeaf)
else
/* Standard features. */
/* Extended features. */
if (pExtLeaf)
{
}
if ( pExtLeaf
{
/* AMD features. */
}
/*
* Quirks.
*/
}
else
return VINF_SUCCESS;
}