PGMAllBth.h revision 7a896688c49bde3fa1490e7ebb321ac51b6ad29d
/* $Id$ */
/** @file
* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
*
* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
* set to PGM_TYPE_PROT. Half of the code in this file is not
* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
*
* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
*
* @remarks This file is one big \#ifdef-orgy!
*
*/
/*
* Copyright (C) 2006-2010 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
#ifdef _MSC_VER
* real/prot-guest+RC mode. */
#endif
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
# else
static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
#endif
#ifdef VBOX_STRICT
PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
#endif
/*
* Filter out some illegal combinations of guest and shadow paging, so we can
* remove redundant checks inside functions.
*/
#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
# error "Invalid combination; PAE guest implies PAE shadow"
#endif
&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT)
# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
#endif
&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT)
# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
#endif
#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
|| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
#endif
#ifndef IN_RING3
/**
* Deal with a guest page fault.
*
* @returns Strict VBox status code.
* @retval VINF_EM_RAW_GUEST_TRAP
* @retval VINF_EM_RAW_EMULATE_INSTR
*
* @param pVCpu The current CPU.
* @param pGstWalk The guest page table walk result.
* @param uErr The error code.
*/
PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
{
# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE)
/*
* Check for write conflicts with our hypervisor mapping.
*
* If the guest happens to access a non-present page, where our hypervisor
* is currently mapped, then we'll create a #PF storm in the guest.
*/
{
/* Force a CR3 sync to check for conflicts and emulate the instruction. */
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
return VINF_EM_RAW_EMULATE_INSTR;
}
# endif
/*
* Calc the error code for the guest trap.
*/
{
}
uNewErr |= X86_TRAP_PF_P;
LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
return VINF_EM_RAW_GUEST_TRAP;
}
# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
/**
* Deal with a guest page fault.
*
* The caller has taken the PGM lock.
*
* @returns Strict VBox status code.
*
* @param pVCpu The current CPU.
* @param uErr The error code.
* @param pRegFrame The register frame.
* @param pvFault The fault address.
* @param pPage The guest page at @a pvFault.
* @param pGstWalk The guest page table walk result.
* @param pfLockTaken PGM lock taken here or not (out). This is true
* when we're called.
*/
static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
# endif
)
{
#endif
int rc;
{
/*
* Physical page access handler.
*/
# else
# endif
if (pCur)
{
# ifdef PGM_SYNC_N_PAGES
/*
* If the region is write protected and we got a page not present fault, then sync
* the pages. If the fault was caused by a read, then restart the instruction.
* In case of write access continue to the GC write handler.
*
* ASSUMES that there is only one handler per page or that they have similar write properties.
*/
if ( !(uErr & X86_TRAP_PF_P)
{
# else
# endif
if ( RT_FAILURE(rc)
|| !(uErr & X86_TRAP_PF_RW)
|| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
{
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
return rc;
}
}
# endif
# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
/*
* If the access was not thru a #PF(RSVD|...) resync the page.
*/
if ( !(uErr & X86_TRAP_PF_RSVD)
&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
# endif
)
{
# else
# endif
if ( RT_FAILURE(rc)
|| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
{
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
return rc;
}
}
# endif
("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
else
{
if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
}
{
# ifdef IN_RING0
# else
# endif
{
*pfLockTaken = false;
}
# ifdef VBOX_WITH_STATISTICS
if (pCur)
# endif
}
else
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
return rc;
}
}
else
{
# ifdef PGM_SYNC_N_PAGES
/*
* If the region is write protected and we got a page not present fault, then sync
* the pages. If the fault was caused by a read, then restart the instruction.
* In case of write access continue to the GC write handler.
*/
&& !(uErr & X86_TRAP_PF_P))
{
if ( RT_FAILURE(rc)
|| !(uErr & X86_TRAP_PF_RW))
{
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
return rc;
}
}
# endif
/*
* Ok, it's an virtual page access handler.
*
* Since it's faster to search by address, we'll do that first
* and then retry by GCPhys if that fails.
*/
/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
* out of sync, because the page was changed without us noticing it (not-present -> present
* without invlpg or mov cr3, xxx).
*/
PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
if (pCur)
{
|| !(uErr & X86_TRAP_PF_P)
("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
&& ( uErr & X86_TRAP_PF_RW
{
# ifdef IN_RC
*pfLockTaken = false;
# ifdef VBOX_WITH_STATISTICS
if (pCur)
# endif
# else
# endif
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
return rc;
}
/* Unhandled part of a monitored page */
}
else
{
/* Check by physical address. */
unsigned iPage;
if ( pCur
&& ( uErr & X86_TRAP_PF_RW
{
Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
# ifdef IN_RC
*pfLockTaken = false;
+ (pvFault & PAGE_OFFSET_MASK)
- (GCPtrStart & PAGE_OFFSET_MASK);
# ifdef VBOX_WITH_STATISTICS
pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
if (pCur)
# endif
# else
# endif
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
return rc;
}
}
}
# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
/*
* There is a handled area of the page, but this fault doesn't belong to it.
* We must emulate the instruction.
*
* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
* we first check if this was a page-not-present fault for a page with only
* write access handlers. Restart the instruction if it wasn't a write access.
*/
&& !(uErr & X86_TRAP_PF_P))
{
# else
# endif
if ( RT_FAILURE(rc)
|| !(uErr & X86_TRAP_PF_RW))
{
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
return rc;
}
}
/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
* It's writing to an unhandled part of the LDT page several million times.
*/
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
return rc;
} /* if any kind of handler */
/**
* #PF Handler for raw-mode guest execution.
*
* @returns VBox status code (appropriate for trap handling and GC return).
*
* @param pVCpu Pointer to the VMCPU.
* @param uErr The trap error code.
* @param pRegFrame Trap register frame.
* @param pvFault The fault address.
* @param pfLockTaken PGM lock taken here or not (out)
*/
PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
{
*pfLockTaken = false;
# if ( PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT \
&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
int rc;
/*
* Walk the guest page translation tables and check if it's a guest fault.
*/
if (RT_FAILURE_NP(rc))
/* assert some GstWalk sanity. */
# if PGM_GST_TYPE == PGM_TYPE_AMD64
/*AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. */
# endif
/*AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto */
# endif
/*AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto */
/*AssertMsg(GstWalk.Core.fBigPage || GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto */
{
if ( ( (uErr & X86_TRAP_PF_RW)
&& ( (uErr & X86_TRAP_PF_US)
)
}
/*
* Set the accessed and dirty flags.
*/
# if PGM_GST_TYPE == PGM_TYPE_AMD64
# endif
{
if (uErr & X86_TRAP_PF_RW)
{
}
else
{
}
}
else
{
if (uErr & X86_TRAP_PF_RW)
{
# ifdef VBOX_WITH_STATISTICS
else
# endif
}
else
{
}
}
("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
GSTPDE const PdeSrcDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A}; /** @todo eliminate this */
# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
/* Take the big lock now. */
*pfLockTaken = true;
# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
/*
* If it is a reserved bit fault we know that it is an MMIO (access
* handler) related fault and can skip some 200 lines of code.
*/
if (uErr & X86_TRAP_PF_RSVD)
{
return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
pfLockTaken, &GstWalk));
# else
return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
pfLockTaken));
# endif
return rc; /* Restart with the corrected entry. */
}
# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
/*
* Fetch the guest PDE, PDPE and PML4E.
*/
# if PGM_SHW_TYPE == PGM_TYPE_32BIT
const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
# if PGM_GST_TYPE == PGM_TYPE_PAE
# else
rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
# endif
AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A,
# else
# endif
AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
# endif
/*
* Dirty page handling.
*
* If we successfully correct the write protection fault due to dirty bit
* tracking, then return immediately.
*/
{
if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
{
LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
return VINF_SUCCESS;
}
//AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u || GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - triggers with smp w7 guests.
//AssertMsg(GstWalk.Core.fBigPage || GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto.
}
# if 0 /* rarely useful; leave for debugging. */
# endif
# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
/*
* A common case is the not-present error caused by lazy page table syncing.
*
* It is IMPORTANT that we weed out any access to non-present shadow PDEs
* here so we can safely assume that the shadow PT is present when calling
* SyncPage later.
*
* On failure, we ASSUME that SyncPT is out of memory or detected some kind
* of mapping conflict and defer to SyncCR3 in R3.
* (Again, we do NOT support access handlers for non-present guest pages.)
*
*/
# endif
if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
{
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
# else
# endif
if (RT_SUCCESS(rc))
return rc;
return VINF_PGM_SYNC_CR3;
}
/*
* Check if this address is within any of our mappings.
*
* This is *very* fast and it's gonna save us a bit of effort below and prevent
* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
* (BTW, it's impossible to have physical access handlers in a mapping.)
*/
if (pgmMapAreMappingsEnabled(pVM))
{
{
break;
{
/*
* The first thing we check is if we've got an undetected conflict.
*/
if (pgmMapAreMappingsFloating(pVM))
{
while (iPT-- > 0)
{
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
return VINF_PGM_SYNC_CR3;
}
}
/*
* Check if the fault address is in a virtual page access handler range.
*/
PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
if ( pCur
&& uErr & X86_TRAP_PF_RW)
{
# ifdef IN_RC
rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
# else
AssertFailed();
# endif
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
return rc;
}
/*
* Pretend we're not here and let the guest handle the trap.
*/
LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
return VINF_EM_RAW_GUEST_TRAP;
}
}
} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
/*
* Check if this fault address is flagged for special treatment,
* which means we'll have to figure out the physical address and
* check flags associated with it.
*
* ASSUME that we can limit any special access handling to pages
* in page tables which the guest believes to be present.
*/
# else
# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
if (RT_FAILURE(rc))
{
/*
* When the guest accesses invalid physical memory (e.g. probing
* of RAM or accessing a remapped MMIO range), then we'll fall
* back to the recompiler to emulate the instruction.
*/
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
return VINF_EM_RAW_EMULATE_INSTR;
}
/*
* Any handlers for this page?
*/
return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
&GstWalk));
# else
return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
# endif
if (uErr & X86_TRAP_PF_P)
{
/*
* The page isn't marked, but it might still be monitored by a virtual page access handler.
* (ASSUMES no temporary disabling of virtual handlers.)
*/
/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
* we should correct both the shadow page table and physical memory flags, and not only check for
* accesses within the handler region but for access to pages with virtual handlers. */
PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
if (pCur)
{
|| !(uErr & X86_TRAP_PF_P)
("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
&& ( uErr & X86_TRAP_PF_RW
{
# ifdef IN_RC
rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
# else
# endif
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
return rc;
}
}
}
# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
/*
* We are here only if page is present in Guest page tables and
* trap is not handled by our handlers.
*
* Check it for page out-of-sync situation.
*/
if (!(uErr & X86_TRAP_PF_P))
{
/*
* Page is not present in our page tables. Try to sync it!
*/
if (uErr & X86_TRAP_PF_US)
else /* supervisor */
if (PGM_PAGE_IS_BALLOONED(pPage))
{
/* Emulate reads from ballooned pages as they are not present in
our shadow page tables. (Required for e.g. Solaris guests; soft
ecc, random nr generator.) */
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
return rc;
}
# if defined(LOG_ENABLED) && !defined(IN_RING0)
Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
# else
Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
# endif
# endif /* LOG_ENABLED */
&& CPUMGetGuestCPL(pVCpu) == 0)
{
/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
# ifdef CSAM_DETECT_NEW_CODE_PAGES
# endif /* CSAM_DETECT_NEW_CODE_PAGES */
)
{
if (rc != VINF_SUCCESS)
{
/*
* CSAM needs to perform a job in ring 3.
*
* Sync the page before going to the host context; otherwise we'll end up in a loop if
* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
*/
LogFlow(("CSAM ring 3 job\n"));
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
return rc;
}
}
# ifdef CSAM_DETECT_NEW_CODE_PAGES
else if ( uErr == X86_TRAP_PF_RW
{
/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
* to detect loading of new code pages.
*/
/*
* Decode the instruction.
*/
/* For now we'll restrict this to rep movsw/d instructions */
if ( rc == VINF_SUCCESS
{
}
}
# endif /* CSAM_DETECT_NEW_CODE_PAGES */
/*
* Mark this page as safe.
*/
/** @todo not correct for pages that contain both code and data!! */
}
# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
# else
# endif
if (RT_SUCCESS(rc))
{
/* The page was successfully synced, return to the guest. */
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
return VINF_SUCCESS;
}
}
else /* uErr & X86_TRAP_PF_P: */
{
/*
* Write protected pages are made writable when the guest makes the
* first write to it. This happens for pages that are shared, write
* monitored or not yet allocated.
*
* We may also end up here when CR0.WP=0 in the guest.
*
* Also, a side effect of not flushing global PDEs are out of sync
* pages due to physical monitored regions, that are no longer valid.
*/
if (uErr & X86_TRAP_PF_RW)
{
/*
* Check if it is a read-only page.
*/
{
Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
if (rc != VINF_SUCCESS)
{
return rc;
}
return VINF_EM_NO_MEMORY;
}
/*
* Check to see if we need to emulate the instruction if CR0.WP=0.
*/
&& CPUMGetGuestCPL(pVCpu) == 0)
{
if (RT_SUCCESS(rc))
else
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
return rc;
}
# endif
/// @todo count the above case; else
if (uErr & X86_TRAP_PF_US)
else /* supervisor */
/*
* Sync the page.
*
* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
* page is not present, which is not true in this case.
*/
# else
# endif
if (RT_SUCCESS(rc))
{
/*
* Page was successfully synced, return to guest but invalidate
* the TLB first as the page is very likely to be in it.
*/
# if PGM_SHW_TYPE == PGM_TYPE_EPT
# else
# endif
# ifdef VBOX_STRICT
{
LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
}
AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) || pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
# endif /* VBOX_STRICT */
STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
return VINF_SUCCESS;
}
}
/** @todo else: why are we here? */
/*
* Check for VMM page flags vs. Guest page flags consistency.
* Currently only for debug purposes.
*/
if (RT_SUCCESS(rc))
{
/* Get guest page flags. */
if (RT_SUCCESS(rc))
{
/*
* Compare page flags.
* Note: we have AVL, A, D bits desynced.
*/
("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
}
else
}
else
# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
}
/*
* If we get here it is because something failed above, i.e. most like guru
* meditiation time.
*/
LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
return rc;
# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
return VERR_PGM_NOT_USED_IN_MODE;
# endif
}
#endif /* !IN_RING3 */
/**
* Emulation of the invlpg instruction.
*
*
* @returns VBox status code.
*
* @param pVCpu Pointer to the VMCPU.
* @param GCPtrPage Page to invalidate.
*
* @remark ASSUMES that the guest is updating before invalidating. This order
* isn't required by the CPU, so this is speculative and could cause
* trouble.
* @remark No TLB shootdown is done on any other VCPU as we assume that
* invlpg emulation is the *only* reason for calling this function.
* (The guest has to shoot down TLB entries on other CPUs itself)
* Currently true, but keep in mind!
*
* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
*/
{
&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
&& PGM_SHW_TYPE != PGM_TYPE_EPT
int rc;
/*
* Get the shadow PD entry and skip out if this PD isn't present.
* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
*/
# if PGM_SHW_TYPE == PGM_TYPE_32BIT
/* Fetch the pgm pool shadow descriptor. */
/* If the shadow PDPE isn't present, then skip the invalidate. */
{
return VINF_SUCCESS;
}
/* Fetch the pgm pool shadow descriptor. */
# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
/* PML4 */
/*const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;*/
if (rc != VINF_SUCCESS)
{
AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
/* Fetch the pgm pool shadow descriptor. */
# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
{
return VINF_SUCCESS;
}
/*
* Get the guest PD entry and calc big page.
*/
# if PGM_GST_TYPE == PGM_TYPE_32BIT
# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
unsigned iPDSrc = 0;
# if PGM_GST_TYPE == PGM_TYPE_PAE
# else /* AMD64 */
# endif
if (pPDSrc)
else
PdeSrc.u = 0;
# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
# ifdef IN_RING3
/*
* If a CR3 Sync is pending we may ignore the invalidate page operation
* depending on the kind of sync and if it's a global page or not.
*/
&& fIsBigPage
)
)
# else
# endif
{
return VINF_SUCCESS;
}
# endif /* IN_RING3 */
/*
* Deal with the Guest PDE.
*/
rc = VINF_SUCCESS;
{
# ifndef PGM_WITHOUT_MAPPING
if (PdeDst.u & PGM_PDFLAGS_MAPPING)
{
/*
* Conflict - Let SyncPT deal with it to avoid duplicate code.
*/
}
else
# endif /* !PGM_WITHOUT_MAPPING */
if (!fIsBigPage)
{
/*
* 4KB - page.
*/
/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
# endif
{
/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
if (RT_SUCCESS(rc))
{
Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
}
}
else
{
/*
* The page table address changed.
*/
LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
}
}
else
{
/*
* 2/4MB - page.
*/
/* Before freeing the page, check if anything really changed. */
/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
# endif
{
/* ASSUMES a the given bits are identical for 4M and normal PDEs */
/** @todo This test is wrong as it cannot check the G bit!
* FIXME */
&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
|| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
{
LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
return VINF_SUCCESS;
}
}
/*
* Ok, the page table is present and it's been changed in the guest.
* If we're in host context, we'll just mark it as not present taking the lazy approach.
* We could do this for some flushes in GC too, but we need an algorithm for
* deciding which 4MB pages containing code likely to be executed very soon.
*/
LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
}
}
else
{
/*
* Page directory is not present, mark shadow PDE not present.
*/
if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
{
}
else
{
}
}
return rc;
#else /* guest real and protected mode */
/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
return VINF_SUCCESS;
#endif
}
/**
* Update the tracking of shadowed pages.
*
* @param pVCpu Pointer to the VMCPU.
* @param pShwPage The shadow page.
* @param HCPhys The physical page we is being dereferenced.
* @param iPte Shadow PTE index
* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
*/
DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
{
# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
&& (PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
/* Use the hint we retrieved from the cached guest PT. */
{
return;
}
# else
# endif
LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
/** @todo If this turns out to be a bottle neck (*very* likely) two things can be done:
* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
* 2. write protect all shadowed pages. I.e. implement caching.
*/
/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
/*
* Find the guest address.
*/
pRam;
{
while (iPage-- > 0)
{
{
return;
}
}
}
for (;;)
}
/**
* Update the tracking of shadowed pages.
*
* @param pVCpu Pointer to the VMCPU.
* @param pShwPage The shadow page.
* @param u16 The top 16-bit of the pPage->HCPhys.
* @param pPage Pointer to the guest page. this will be modified.
* @param iPTDst The index into the shadow table.
*/
DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
{
/*
* Just deal with the simple first time here.
*/
if (!u16)
{
/* Save the page table index. */
}
else
/* write back */
Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
/* update statistics. */
}
/**
* Modifies a shadow PTE to account for access handlers.
*
* @param pVM Pointer to the VM.
* @param pPage The page in question.
* @param fPteSrc The shadowed flags of the source PTE. Must include the
* A (accessed) bit so it can be emulated correctly.
* @param pPteDst The shadow PTE (output). This is temporary storage and
* does not need to be set atomically.
*/
DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
{
/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
{
#if PGM_SHW_TYPE == PGM_TYPE_EPT
/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
#else
{
}
else
SHW_PTE_SET(*pPteDst, 0);
#endif
}
#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
&& ( BTH_IS_NP_ACTIVE(pVM)
|| (fPteSrc & (X86_PTE_RW | X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
# if PGM_SHW_TYPE == PGM_TYPE_AMD64
# endif
)
{
LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
# if PGM_SHW_TYPE == PGM_TYPE_EPT
/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
# else
/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
# endif
}
# endif
#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
else
{
SHW_PTE_SET(*pPteDst, 0);
}
/** @todo count these kinds of entries. */
}
/**
* Creates a 4K shadow page for a guest page.
*
* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
* physical address. The PdeSrc argument only the flags are used. No page
* structured will be mapped in this function.
*
* @param pVCpu Pointer to the VMCPU.
* @param pPteDst Destination page table entry.
* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
* Can safely assume that only the flags are being used.
* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
* @param pShwPage Pointer to the shadow page.
* @param iPTDst The index into the shadow table.
*
* @remark Not used for 2/4MB pages!
*/
static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
#else
static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
#endif
{
#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
&& (PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
{
/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
}
#else
#endif
#endif
{
# endif
/*
* Find the ram range.
*/
if (RT_SUCCESS(rc))
{
/* Ignore ballooned pages.
Don't return errors or use a fatal assert here as part of a
shadow sync range might included ballooned pages. */
if (PGM_PAGE_IS_BALLOONED(pPage))
{
return;
}
#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
/* Make the page writable if necessary. */
&& ( PGM_PAGE_IS_ZERO(pPage)
# else
|| ( 1
# endif
# endif
# ifdef VBOX_WITH_PAGE_SHARING
# endif
)
)
)
{
}
#endif
/*
* Make page table entry.
*/
# else
# endif
else
{
/*
* If the page or page directory entry is not marked accessed,
* we mark the page not present.
*/
{
LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
SHW_PTE_SET(PteDst, 0);
}
/*
* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
* when the page is modified.
*/
{
}
else
#endif
{
#if PGM_SHW_TYPE == PGM_TYPE_EPT
/* PteDst.n.u1Size = 0 */
#else
#endif
}
/*
* Make sure only allocated pages are mapped writable.
*/
if ( SHW_PTE_IS_P_RW(PteDst)
{
/* Still applies to shared pages. */
Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
}
}
/*
* Keep user track up to date.
*/
if (SHW_PTE_IS_P(PteDst))
{
if (!SHW_PTE_IS_P(*pPteDst))
PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
{
Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(*pPteDst), SHW_PTE_LOG64(PteDst)));
PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
}
}
else if (SHW_PTE_IS_P(*pPteDst))
{
PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
}
/*
* Update statistics and commit the entry.
*/
pShwPage->fSeenNonGlobal = true;
#endif
return;
}
/** @todo count these three different kinds. */
Log2(("SyncPageWorker: invalid address in Pte\n"));
}
Log2(("SyncPageWorker: page not present in Pte\n"));
else
Log2(("SyncPageWorker: invalid Pte\n"));
#endif
/*
* The page is not present or the PTE is bad. Replace the shadow PTE by
* an empty entry, making sure to keep the user tracking up to date.
*/
if (SHW_PTE_IS_P(*pPteDst))
{
PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
}
SHW_PTE_ATOMIC_SET(*pPteDst, 0);
}
/**
* Syncs a guest OS page.
*
* There are no conflicts at this point, neither is there any need for
* page table allocations.
*
* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
* When called in AMD64 guest mode, the guest PML4E shall be valid.
*
* @returns VBox status code.
* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
* @param pVCpu Pointer to the VMCPU.
* @param PdeSrc Page directory entry of the guest.
* @param GCPtrPage Guest context page address.
* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
* @param uErr Fault error (X86_TRAP_PF_*).
*/
static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
{
#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
|| PGM_GST_TYPE == PGM_TYPE_PAE \
|| PGM_GST_TYPE == PGM_TYPE_AMD64) \
&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
&& PGM_SHW_TYPE != PGM_TYPE_EPT
/*
* Assert preconditions.
*/
# if 0 /* rarely useful; leave for debugging. */
# endif
/*
* Get the shadow PDE, find the shadow page table in the pool.
*/
# if PGM_SHW_TYPE == PGM_TYPE_32BIT
/* Fetch the pgm pool shadow descriptor. */
/* Fetch the pgm pool shadow descriptor. */
# endif
/*
* - In the guest SMP case we could have blocked while another VCPU reused
* this page table.
* - With W7-64 we may also take this path when the A bit is cleared on
* relevant TLB entries. If we're write monitoring any page mapped by
* the modified entry, we may end up here with a "stale" TLB entry.
*/
{
Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
AssertMsg(pVM->cCpus > 1 || (uErr & (X86_TRAP_PF_P | X86_TRAP_PF_RW)) == (X86_TRAP_PF_P | X86_TRAP_PF_RW),
if (uErr & X86_TRAP_PF_P)
return VINF_SUCCESS; /* force the instruction to be executed again. */
}
# if PGM_GST_TYPE == PGM_TYPE_AMD64
/* Fetch the pgm pool shadow descriptor. */
# endif
/*
* Check that the page is present and that the shadow PDE isn't out of sync.
*/
const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
if (!fBigPage)
{
/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
# endif
}
else
{
/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
# endif
}
/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
if ( fPdeValid
# endif
)
{
/*
* Check that the PDE is marked accessed already.
* Since we set the accessed bit *before* getting here on a #PF, this
* check is only meant for dealing with non-#PF'ing paths.
*/
if (PdeSrc.n.u1Accessed)
{
if (!fBigPage)
{
/*
* 4KB Page - Map the guest page table.
*/
if (RT_SUCCESS(rc))
{
# ifdef PGM_SYNC_N_PAGES
if ( cPages > 1
&& !(uErr & X86_TRAP_PF_P)
{
/*
* This code path is currently only taken when the caller is PGMTrap0eHandler
* for non-present pages!
*
* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
* deal with locality.
*/
/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
# else
const unsigned offPTSrc = 0;
# endif
iPTDst = 0;
else
{
{
RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) | ((offPTSrc + iPTDst) << PAGE_SHIFT);
#ifndef IN_RING0
/*
* Assuming kernel code will be marked as supervisor - and not as user level
* and executed using a conforming code selector - And marked as readonly.
* Also assume that if we're monitoring a page, it's of no interest to CSAM.
*/
)
#endif /* else: CSAM not active */
Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
}
}
}
else
# endif /* PGM_SYNC_N_PAGES */
{
Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
}
}
else /* MMIO or invalid page: emulated in #PF handler. */
{
}
}
else
{
/*
* 4/2MB page - lazy syncing shadow 4K pages.
* (There are many causes of getting here, it's no longer only CSAM.)
*/
/* Calculate the GC physical address of this 4KB shadow page. */
GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) | (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
/* Find ram range. */
if (RT_SUCCESS(rc))
{
# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
/* Try to make the page writable if necessary. */
&& ( PGM_PAGE_IS_ZERO(pPage)
# endif
# ifdef VBOX_WITH_PAGE_SHARING
# endif
)
)
)
{
}
# endif
/*
* Make shadow PTE entry.
*/
else
if ( SHW_PTE_IS_P(PteDst)
PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
/* Make sure only allocated pages are mapped writable. */
if ( SHW_PTE_IS_P_RW(PteDst)
{
/* Still applies to shared pages. */
}
/*
* If the page is not flagged as dirty and is writable, then make it read-only
* at PD level, so we can set the dirty bit when the page is modified.
*
* ASSUMES that page access handlers are implemented on page table entry level.
* Thus we will first catch the dirty access and set PDE.D and restart. If
* there is an access handler, we'll trap again and let it work on the problem.
*/
/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
* As for invlpg, it simply frees the whole shadow PT.
* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
{
}
else
{
}
Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
}
else
{
/** @todo must wipe the shadow page table entry in this
* case. */
}
}
return VINF_SUCCESS;
}
}
else if (fPdeValid)
{
Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
}
else
{
/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
}
/*
* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
* Yea, I'm lazy.
*/
return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
&& !defined(IN_RC)
# ifdef PGM_SYNC_N_PAGES
/*
* Get the shadow PDE, find the shadow page table in the pool.
*/
# if PGM_SHW_TYPE == PGM_TYPE_32BIT
if (rc != VINF_SUCCESS)
{
return rc;
}
# endif
/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
{
return VINF_SUCCESS; /* force the instruction to be executed again. */
}
/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
{
Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
return VINF_SUCCESS;
}
/* Mask away the page offset. */
if ( cPages > 1
&& !(uErr & X86_TRAP_PF_P)
{
/*
* This code path is currently only taken when the caller is PGMTrap0eHandler
* for non-present pages!
*
* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
* deal with locality.
*/
iPTDst = 0;
else
{
{
| (iPTDst << PAGE_SHIFT));
Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
break;
}
else
Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) | (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
}
}
else
# endif /* PGM_SYNC_N_PAGES */
{
| (iPTDst << PAGE_SHIFT));
Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
}
return VINF_SUCCESS;
#else
return VERR_PGM_NOT_USED_IN_MODE;
#endif
}
/**
* CheckPageFault helper for returning a page fault indicating a non-present
* (NP) entry in the page translation structures.
*
* @returns VINF_EM_RAW_GUEST_TRAP.
* @param pVCpu Pointer to the VMCPU.
* @param uErr The error code of the shadow fault. Corrections to
* TRPM's copy will be made if necessary.
* @param GCPtrPage For logging.
* @param uPageFaultLevel For logging.
*/
DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
{
return VINF_EM_RAW_GUEST_TRAP;
}
/**
* CheckPageFault helper for returning a page fault indicating a reserved bit
* (RSVD) error in the page translation structures.
*
* @returns VINF_EM_RAW_GUEST_TRAP.
* @param pVCpu Pointer to the VMCPU.
* @param uErr The error code of the shadow fault. Corrections to
* TRPM's copy will be made if necessary.
* @param GCPtrPage For logging.
* @param uPageFaultLevel For logging.
*/
DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
{
return VINF_EM_RAW_GUEST_TRAP;
}
/**
* CheckPageFault helper for returning a page protection fault (P).
*
* @returns VINF_EM_RAW_GUEST_TRAP.
* @param pVCpu Pointer to the VMCPU.
* @param uErr The error code of the shadow fault. Corrections to
* TRPM's copy will be made if necessary.
* @param GCPtrPage For logging.
* @param uPageFaultLevel For logging.
*/
DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
{
return VINF_EM_RAW_GUEST_TRAP;
}
/**
* Handle dirty bit tracking faults.
*
* @returns VBox status code.
* @param pVCpu Pointer to the VMCPU.
* @param uErr Page fault error code.
* @param pPdeSrc Guest page directory entry.
* @param pPdeDst Shadow page directory entry.
* @param GCPtrPage Guest context page address.
*/
static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
{
/*
* Handle big page.
*/
{
&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
{
/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
* fault again and take this path to only invalidate the entry (see below).
*/
return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
}
# ifdef IN_RING0
/* Check for stale TLB entry; only applies to the SMP guest case. */
&& pPdeDst->n.u1Accessed)
{
if (pShwPage)
{
if (SHW_PTE_IS_P_RW(*pPteDst))
{
/* Stale TLB entry. */
return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
}
}
}
# endif /* IN_RING0 */
return VINF_PGM_NO_DIRTY_BIT_TRACKING;
}
/*
* Map the guest page table.
*/
if (RT_FAILURE(rc))
{
return rc;
}
{
#ifndef IN_RING0
/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
* Our individual shadow handlers will provide more information and force a fatal exit.
*/
{
return VINF_PGM_NO_DIRTY_BIT_TRACKING;
}
#endif
/*
* Map shadow page table.
*/
if (pShwPage)
{
{
if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
{
/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
* entry will not harm; write access will simply fault again and
* take this path to only invalidate the entry.
*/
{
{
//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
}
else
{
{
}
else
{
/* Still applies to shared pages. */
}
}
}
else
SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) | X86_PTE_D | X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
}
# ifdef IN_RING0
/* Check for stale TLB entry; only applies to the SMP guest case. */
&& SHW_PTE_IS_RW(*pPteDst)
&& SHW_PTE_IS_A(*pPteDst))
{
/* Stale TLB entry. */
return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
}
# endif
}
}
else
}
return VINF_PGM_NO_DIRTY_BIT_TRACKING;
}
#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
/**
* Sync a shadow page table.
*
* The shadow page table is not present in the shadow PDE.
*
* Handles mapping conflicts.
*
* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
* conflict), and Trap0eHandler.
*
* A precondition for this method is that the shadow PDE is not present. The
* caller must take the PGM lock before checking this and continue to hold it
* when calling this method.
*
* @returns VBox status code.
* @param pVCpu Pointer to the VMCPU.
* @param iPD Page directory index.
* @param pPDSrc Source page directory (i.e. Guest OS page directory).
* Assume this is a temporary mapping.
* @param GCPtrPage GC Pointer of the page that caused the fault
*/
{
#if 0 /* rarely useful; leave for debugging. */
#endif
#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
|| PGM_GST_TYPE == PGM_TYPE_PAE \
|| PGM_GST_TYPE == PGM_TYPE_AMD64) \
&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
&& PGM_SHW_TYPE != PGM_TYPE_EPT
int rc = VINF_SUCCESS;
/*
* Some input validation first.
*/
AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
/*
* Get the relevant shadow PDE entry.
*/
# if PGM_SHW_TYPE == PGM_TYPE_32BIT
/* Fetch the pgm pool shadow descriptor. */
/* Fetch the pgm pool shadow descriptor. */
# endif
# if PGM_GST_TYPE == PGM_TYPE_AMD64
/* Fetch the pgm pool shadow descriptor. */
# endif
# ifndef PGM_WITHOUT_MAPPINGS
/*
* Check for conflicts.
* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
* R3: Simply resolve the conflict.
*/
if (PdeDst.u & PGM_PDFLAGS_MAPPING)
{
# ifndef IN_RING3
return VERR_ADDRESS_CONFLICT;
# else /* IN_RING3 */
# if PGM_GST_TYPE == PGM_TYPE_32BIT
# else
# endif
if (RT_FAILURE(rc))
{
return rc;
}
# endif /* IN_RING3 */
}
# endif /* !PGM_WITHOUT_MAPPINGS */
/*
* Sync the page directory entry.
*/
{
/*
* Allocate & map the page table.
*/
if (fPageTable)
{
/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
# endif
rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
&pShwPage);
}
else
{
# else
const bool fNoExecute = false;
# endif
/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
# endif
/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
{
else
}
else
{
else
}
&pShwPage);
}
if (rc == VINF_SUCCESS)
else if (rc == VINF_PGM_CACHED_PAGE)
{
/*
* The PT was cached, just hook it up.
*/
if (fPageTable)
else
{
/* (see explanation and assumptions further down.) */
{
}
}
return VINF_SUCCESS;
}
else if (rc == VERR_PGM_POOL_FLUSHED)
{
return VINF_PGM_SYNC_CR3;
}
else
/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
* irrelevant at this point. */
PdeDst.u &= X86_PDE_AVL_MASK;
/*
* Page directory has been accessed (this is a fault situation, remember).
*/
/** @todo
* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
* fault situation. What's more, the Trap0eHandler has already set the
* accessed bit. So, it's actually just VerifyAccessSyncPage which
* might need setting the accessed flag.
*
* The best idea is to leave this change to the caller and add an
* assertion that it's set already. */
if (fPageTable)
{
/*
* Page table - 4KB.
*
* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
*/
Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
if (RT_SUCCESS(rc))
{
/*
* Start by syncing the page directory entry so CSAM's TLB trick works.
*/
/*
*
* Directory Page Combined
* U/S U/S U/S
* 0 0 0
* 0 1 0
* 1 0 0
* 1 1 1
*
* Simple AND operation. Table listed for completeness.
*
*/
# ifdef PGM_SYNC_N_PAGES
iPTDst = 0;
else
# else /* !PGM_SYNC_N_PAGES */
unsigned iPTDst = 0;
# endif /* !PGM_SYNC_N_PAGES */
/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
# else
const unsigned offPTSrc = 0;
# endif
{
{
# ifndef IN_RING0
/*
* Assuming kernel code will be marked as supervisor - and not as user level
* and executed using a conforming code selector - And marked as readonly.
* Also assume that if we're monitoring a page, it's of no interest to CSAM.
*/
)
# endif
Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
}
/* else: the page table was cleared by the pool */
} /* for PTEs */
}
}
else
{
/*
* Big page - 2/4MB.
*
* We'll walk the ram range list in parallel and optimize lookups.
* We will only sync one shadow page table at a time.
*/
/**
* @todo It might be more efficient to sync only a part of the 4MB
* page (similar to what we do for 4KB PDs).
*/
/*
* Start by syncing the page directory entry.
*/
/*
* If the page is not flagged as dirty and is writable, then make it read-only
* at PD level, so we can set the dirty bit when the page is modified.
*
* ASSUMES that page access handlers are implemented on page table entry level.
* Thus we will first catch the dirty access and set PDE.D and restart. If
* there is an access handler, we'll trap again and let it work on the problem.
*/
/** @todo move the above stuff to a section in the PGM documentation. */
{
}
/*
* Fill the shadow page table.
*/
/* Get address and flags from the source PDE. */
/* Loop thru the entries in the shadow PT. */
Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
unsigned iPTDst = 0;
{
{
# ifndef PGM_WITH_A20
# endif
do
{
/* Make shadow PTE. */
# ifdef PGM_WITH_A20
# else
# endif
# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
/* Try to make the page writable if necessary. */
&& ( PGM_PAGE_IS_ZERO(pPage)
|| ( SHW_PTE_IS_RW(PteDstBase)
# endif
# ifdef VBOX_WITH_PAGE_SHARING
# endif
&& !PGM_PAGE_IS_BALLOONED(pPage))
)
)
{
break;
}
# endif
else if (PGM_PAGE_IS_BALLOONED(pPage))
# ifndef IN_RING0
/*
* Assuming kernel code will be marked as supervisor and not as user level and executed
* using a conforming code selector. Don't check for readonly, as that implies the whole
* 4MB can be code or readonly data. Linux enables write access for its large pages.
*/
SHW_PTE_SET(PteDst, 0);
# endif
else
/* Only map writable pages writable. */
if ( SHW_PTE_IS_P_RW(PteDst)
{
/* Still applies to shared pages. */
Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT))));
}
if (SHW_PTE_IS_P(PteDst))
PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
/* commit it (not atomic, new table) */
Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
(RTGCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
/* advance */
# ifndef PGM_WITH_A20
iHCPage++;
# endif
iPTDst++;
/* Advance ram range list. */
}
else if (pRam)
{
do
{
iPTDst++;
}
else
{
}
} /* while more PTEs */
} /* 4KB / 4MB */
}
else
if (RT_FAILURE(rc))
return rc;
&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
&& !defined(IN_RC)
/*
* Validate input a little bit.
*/
int rc = VINF_SUCCESS;
# if PGM_SHW_TYPE == PGM_TYPE_32BIT
/* Fetch the pgm pool shadow descriptor. */
/* Fetch the pgm pool shadow descriptor. */
/* Fetch the pgm pool shadow descriptor. */
if (rc != VINF_SUCCESS)
{
return rc;
}
/* Fetch the pgm pool shadow descriptor. */
# endif
# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
if (BTH_IS_NP_ACTIVE(pVM))
{
/* Check if we allocated a big page before for this 2 MB range. */
if (RT_SUCCESS(rc))
{
{
if (PGM_A20_IS_ENABLED(pVCpu))
{
}
else
{
}
}
&& PGM_A20_IS_ENABLED(pVCpu))
{
/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
if (RT_SUCCESS(rc))
{
}
}
else if ( PGMIsUsingLargePages(pVM)
&& PGM_A20_IS_ENABLED(pVCpu))
{
if (RT_SUCCESS(rc))
{
}
else
}
if (HCPhys != NIL_RTHCPHYS)
{
PdeDst.u &= X86_PDE_AVL_MASK;
# if PGM_SHW_TYPE == PGM_TYPE_EPT
# else
# endif
/* Add a reference to the first page only. */
PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
return VINF_SUCCESS;
}
}
}
# endif /* HC_ARCH_BITS == 64 */
/*
* Allocate & map the page table.
*/
/* Virtual address = physical address */
rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
&pShwPage);
if ( rc == VINF_SUCCESS
|| rc == VINF_PGM_CACHED_PAGE)
else
{
}
if (rc == VINF_SUCCESS)
{
/* New page table; fully set it up. */
/* Mask away the page offset. */
{
| (iPTDst << PAGE_SHIFT));
Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
break;
}
}
else
/* Save the new PDE. */
PdeDst.u &= X86_PDE_AVL_MASK;
# if PGM_SHW_TYPE == PGM_TYPE_EPT
# else
# endif
if (RT_FAILURE(rc))
return rc;
#else
return VERR_PGM_NOT_USED_IN_MODE;
#endif
}
/**
*
* Typically used to sync commonly used pages before entering raw mode
* after a CR3 reload.
*
* @returns VBox status code.
* @param pVCpu Pointer to the VMCPU.
* @param GCPtrPage Page to invalidate.
*/
{
#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
|| PGM_GST_TYPE == PGM_TYPE_REAL \
|| PGM_GST_TYPE == PGM_TYPE_PROT \
|| PGM_GST_TYPE == PGM_TYPE_PAE \
|| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
&& PGM_SHW_TYPE != PGM_TYPE_EPT
/*
* Check that all Guest levels thru the PDE are present, getting the
* PD and PDE in the processes.
*/
int rc = VINF_SUCCESS;
# if PGM_GST_TYPE == PGM_TYPE_32BIT
unsigned iPDSrc;
if (!pPDSrc)
return VINF_SUCCESS; /* not present */
unsigned iPDSrc;
if (!pPDSrc)
return VINF_SUCCESS; /* not present */
# endif
# else
const unsigned iPDSrc = 0;
PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
# endif
{
# if PGM_SHW_TYPE == PGM_TYPE_32BIT
# if PGM_GST_TYPE != PGM_TYPE_PAE
/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
# endif
if (rc != VINF_SUCCESS)
{
return rc;
}
# if PGM_GST_TYPE == PGM_TYPE_PROT
/* AMD-V nested paging */
/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
# endif
if (rc != VINF_SUCCESS)
{
return rc;
}
# endif
if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
{
{
/** @todo r=bird: This guy will set the A bit on the PDE,
* probably harmless. */
}
else
{
/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
* makes no sense to prefetch more than one page.
*/
if (RT_SUCCESS(rc))
rc = VINF_SUCCESS;
}
}
}
return rc;
return VINF_SUCCESS; /* ignore */
#else
AssertCompile(0);
#endif
}
/**
* Syncs a page during a PGMVerifyAccess() call.
*
* @returns VBox status code (informational included).
* @param pVCpu Pointer to the VMCPU.
* @param GCPtrPage The address of the page to sync.
* @param fPage The effective guest page flags.
* @param uErr The trap error code.
* @remarks This will normally never be called on invalid guest page
* translation entries.
*/
PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
{
#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
|| PGM_GST_TYPE == PGM_TYPE_REAL \
|| PGM_GST_TYPE == PGM_TYPE_PROT \
|| PGM_GST_TYPE == PGM_TYPE_PAE \
|| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
&& PGM_SHW_TYPE != PGM_TYPE_EPT
# ifndef IN_RING0
if (!(fPage & X86_PTE_US))
{
/*
* Mark this page as safe.
*/
/** @todo not correct for pages that contain both code and data!! */
}
# endif
/*
* Get guest PD and index.
*/
/** @todo Performance: We've done all this a jiffy ago in the
* PGMGstGetPage call. */
# if PGM_GST_TYPE == PGM_TYPE_32BIT
unsigned iPDSrc = 0;
if (RT_UNLIKELY(!pPDSrc))
{
return VINF_EM_RAW_GUEST_TRAP;
}
unsigned iPDSrc = 0; /* shut up gcc */
if (RT_UNLIKELY(!pPDSrc))
{
return VINF_EM_RAW_GUEST_TRAP;
}
# endif
# else /* !PGM_WITH_PAGING */
const unsigned iPDSrc = 0;
# endif /* !PGM_WITH_PAGING */
int rc = VINF_SUCCESS;
/*
* First check if the shadow pd is present.
*/
# if PGM_SHW_TYPE == PGM_TYPE_32BIT
# if PGM_GST_TYPE != PGM_TYPE_PAE
/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
# endif
if (rc != VINF_SUCCESS)
{
return rc;
}
# if PGM_GST_TYPE == PGM_TYPE_PROT
/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
# endif
if (rc != VINF_SUCCESS)
{
return rc;
}
# endif
{
if (rc != VINF_SUCCESS)
{
return rc;
}
}
/* Check for dirty bit fault */
if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
Log(("PGMVerifyAccess: success (dirty)\n"));
else
# endif
{
# else
PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
# endif
if (uErr & X86_TRAP_PF_US)
else /* supervisor */
if (RT_SUCCESS(rc))
{
/* Page was successfully synced */
Log2(("PGMVerifyAccess: success (sync)\n"));
rc = VINF_SUCCESS;
}
else
{
}
}
return rc;
#else /* PGM_SHW_TYPE == PGM_TYPE_EPT || PGM_SHW_TYPE == PGM_TYPE_NESTED */
return VERR_PGM_NOT_USED_IN_MODE;
#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT || PGM_SHW_TYPE == PGM_TYPE_NESTED */
}
/**
* Syncs the paging hierarchy starting at CR3.
*
* @returns VBox status code, no specials.
* @param pVCpu Pointer to the VMCPU.
* @param cr0 Guest context CR0 register.
* @param cr3 Guest context CR3 register. Not subjected to the A20
* mask.
* @param cr4 Guest context CR4 register.
* @param fGlobal Including global page directories or not
*/
{
# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
if (pPool->cDirtyPages)
# endif
/*
* Update page access handlers.
* The virtual are always flushed, while the physical are only on demand.
* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
* have to look into that later because it will have a bad influence on the performance.
* @note SvL: There's no need for that. Just invalidate the virtual range(s).
* bird: Yes, but that won't work for aliases.
*/
/** @todo this MUST go away. See @bugref{1557}. */
#endif /* !NESTED && !EPT */
/*
* Nested / EPT - almost no work.
*/
return VINF_SUCCESS;
/*
* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
* out the shadow parts when the guest modifies its tables.
*/
return VINF_SUCCESS;
#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
# ifndef PGM_WITHOUT_MAPPINGS
/*
* Check for and resolve conflicts with our guest mappings if they
* are enabled and not fixed.
*/
if (pgmMapAreMappingsFloating(pVM))
{
if (rc == VINF_PGM_SYNC_CR3)
{
LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
return VINF_PGM_SYNC_CR3;
}
}
# else
# endif
return VINF_SUCCESS;
#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
}
#ifdef VBOX_STRICT
# ifdef IN_RC
# define AssertMsgFailed Log
# endif
/**
* Checks that the shadow page table is in sync with the guest one.
*
* @returns The number of errors.
* @param pVM The virtual machine.
* @param pVCpu Pointer to the VMCPU.
* @param cr3 Guest context CR3 register.
* @param cr4 Guest context CR4 register.
* @param GCPtr Where to start. Defaults to 0.
* @param cb How much to check. Defaults to everything.
*/
PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
{
return 0;
#else
unsigned cErrors = 0;
# if PGM_GST_TYPE == PGM_TYPE_PAE
/** @todo currently broken; crashes below somewhere */
AssertFailed();
# endif
# if PGM_GST_TYPE == PGM_TYPE_32BIT \
|| PGM_GST_TYPE == PGM_TYPE_PAE \
|| PGM_GST_TYPE == PGM_TYPE_AMD64
# ifndef IN_RING0
# endif
int rc;
/*
* Check that the Guest CR3 and all its mappings are correct.
*/
false);
# if PGM_GST_TYPE == PGM_TYPE_32BIT
# else
# endif
AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
# endif
# endif /* !IN_RING0 */
/*
* Get and check the Shadow CR3.
*/
# if PGM_SHW_TYPE == PGM_TYPE_32BIT
unsigned cPDEs = X86_PG_ENTRIES;
# if PGM_GST_TYPE == PGM_TYPE_32BIT
# else
unsigned cPDEs = X86_PG_PAE_ENTRIES;
# endif
unsigned cPDEs = X86_PG_PAE_ENTRIES;
# endif
/** @todo call the other two PGMAssert*() functions. */
# if PGM_GST_TYPE == PGM_TYPE_AMD64
{
/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
{
continue;
}
{
AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
cErrors++;
continue;
}
{
AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
cErrors++;
continue;
}
{
AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
cErrors++;
continue;
}
# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
{
# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
/*
* Check the PDPTEs too.
*/
{
unsigned iPDSrc = 0; /* initialized to shut up gcc */
PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
# if PGM_GST_TYPE == PGM_TYPE_PAE
# else
if (rc != VINF_SUCCESS)
{
continue; /* next PDPTE */
}
# endif
{
continue; /* next PDPTE */
}
{
AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
cErrors++;
continue;
}
{
# if PGM_GST_TYPE == PGM_TYPE_AMD64
AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
# else
AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
# endif
cErrors++;
continue;
}
# if PGM_GST_TYPE == PGM_TYPE_AMD64
{
AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
cErrors++;
continue;
}
# endif
# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
{
# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
# if PGM_GST_TYPE == PGM_TYPE_32BIT
# if PGM_SHW_TYPE == PGM_TYPE_32BIT
# endif
# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
/*
* Iterate the shadow page directory.
*/
for (;
{
# if PGM_SHW_TYPE == PGM_TYPE_PAE
# else
# endif
if (PdeDst.u & PGM_PDFLAGS_MAPPING)
{
{
AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
cErrors++;
continue;
}
}
)
{
if (!pPoolPage)
{
AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
cErrors++;
continue;
}
{
AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
cErrors++;
}
{
AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
cErrors++;
}
{
AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
cErrors++;
continue;
}
|| !fBigPagesSupported)
{
# endif
}
else
{
# if PGM_GST_TYPE == PGM_TYPE_32BIT
if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
{
AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
cErrors++;
continue;
}
# endif
# endif
}
!= (!PdeSrc.b.u1Size || !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
{
AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
cErrors++;
}
if (!pPhysPage)
{
AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
cErrors++;
continue;
}
{
AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
cErrors++;
continue;
}
|| !fBigPagesSupported)
{
/*
* Page Table.
*/
&pPTSrc);
if (RT_FAILURE(rc))
{
AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
cErrors++;
continue;
}
{
/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
cErrors++;
continue;
}
if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
{
AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
cErrors++;
continue;
}
/* iterate the page table. */
/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
# else
const unsigned offPTSrc = 0;
# endif
{
/* skip not-present and dirty tracked entries. */
if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P | PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
continue;
{
# ifdef IN_RING3
# endif
AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
cErrors++;
continue;
}
uint64_t fIgnoreFlags = GST_PTE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_G | X86_PTE_D | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT;
# if 1 /** @todo sync accessed bit properly... */
# endif
/* match the physical addresses */
# ifdef IN_RING3
if (RT_FAILURE(rc))
{
{
AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
continue;
}
}
{
AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
continue;
}
# endif
if (!pPhysPage)
{
# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
{
AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
continue;
}
# endif
if (SHW_PTE_IS_RW(PteDst))
{
AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
}
}
{
AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
continue;
}
/* flags */
{
{
if (SHW_PTE_IS_RW(PteDst))
{
AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
continue;
}
}
else
{
if ( SHW_PTE_IS_P(PteDst)
# endif
)
{
AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
continue;
}
}
}
else
{
{
if (SHW_PTE_IS_RW(PteDst))
{
AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
continue;
}
if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
{
AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
continue;
}
if (SHW_PTE_IS_D(PteDst))
{
AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
}
# if 0 /** @todo sync access bit properly... */
{
AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
}
# else
# endif
}
else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
{
/* access bit emulation (not implemented). */
{
AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
continue;
}
if (!SHW_PTE_IS_A(PteDst))
{
AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
}
}
# ifdef DEBUG_sandervl
# endif
}
)
{
AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
continue;
}
} /* foreach PTE */
}
else
{
/*
* Big Page.
*/
uint64_t fIgnoreFlags = X86_PDE_AVL_MASK | GST_PDE_PG_MASK | X86_PDE4M_G | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_PWT | X86_PDE4M_PCD;
{
{
AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
cErrors++;
continue;
}
if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
{
AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
continue;
}
# if 0 /** @todo sync access bit properly... */
{
AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
}
# else
# endif
}
else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
{
/* access bit emulation (not implemented). */
{
AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
cErrors++;
continue;
}
if (!PdeDst.n.u1Accessed)
{
AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
cErrors++;
}
}
{
AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
cErrors++;
}
/* iterate the page table. */
{
if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
{
AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
}
/* skip not-present entries. */
continue;
fIgnoreFlags = X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT | X86_PTE_D | X86_PTE_A | X86_PTE_G | X86_PTE_PAE_NX;
/* match the physical addresses */
# ifdef IN_RING3
if (RT_FAILURE(rc))
{
{
AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
}
}
{
AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
continue;
}
# endif
if (!pPhysPage)
{
# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
{
AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
continue;
}
# endif
if (SHW_PTE_IS_RW(PteDst))
{
AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
}
}
{
AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
continue;
}
/* flags */
{
{
{
if (SHW_PTE_IS_RW(PteDst))
{
AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
continue;
}
}
}
else
{
if ( SHW_PTE_IS_P(PteDst)
# endif
)
{
AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
continue;
}
}
}
&& (PdeSrc.u & ~(fIgnoreFlags | X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
)
{
AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
cErrors++;
continue;
}
} /* for each PTE */
}
}
/* not present */
} /* for each PDE */
} /* for each PDPTE */
} /* for each PML4E */
# ifdef DEBUG
if (cErrors)
# endif
# endif /* GST is in {32BIT, PAE, AMD64} */
return cErrors;
#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
}
#endif /* VBOX_STRICT */
/**
* Sets up the CR3 for shadow paging
*
* @returns Strict VBox status code.
* @retval VINF_SUCCESS.
*
* @param pVCpu Pointer to the VMCPU.
* @param GCPhysCR3 The physical address in the CR3 register. (A20
* mask already applied.)
*/
{
/* Update guest paging info. */
#if PGM_GST_TYPE == PGM_TYPE_32BIT \
|| PGM_GST_TYPE == PGM_TYPE_PAE \
|| PGM_GST_TYPE == PGM_TYPE_AMD64
/*
* Map the page CR3 points at.
*/
/** @todo this needs some reworking wrt. locking? */
# if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
int rc = VINF_SUCCESS;
# else
int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3); /** @todo r=bird: This GCPhysCR3 masking isn't necessary. */
# endif
if (RT_SUCCESS(rc))
{
if (RT_SUCCESS(rc))
{
# ifdef IN_RC
# endif
# if PGM_GST_TYPE == PGM_TYPE_32BIT
# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
# endif
# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
# endif
/*
* Map the 4 PDs too.
*/
{
if (pGuestPDPT->a[i].n.u1Present)
{
# if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
HCPtr = NIL_RTHCPTR;
int rc2 = VINF_SUCCESS;
# else
# endif
if (RT_SUCCESS(rc2))
{
# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
# endif
# ifdef IN_RC
# endif
continue;
}
}
# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
# endif
# ifdef IN_RC
# endif
}
# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
# endif
# endif
}
else
}
else
int rc = VINF_SUCCESS;
#endif
/* Update shadow paging info for guest modes with paging (32, pae, 64). */
# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
|| PGM_SHW_TYPE == PGM_TYPE_PAE \
|| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
&& PGM_GST_TYPE != PGM_TYPE_PROT))
/*
* Update the shadow root page as well since that's not fixed.
*/
# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
if (pPool->cDirtyPages)
# endif
rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
rc = VINF_SUCCESS;
# ifdef IN_RC
/*
* WARNING! We can't deal with jumps to ring 3 in the code below as the
* state will be inconsistent! Flush important things now while
* we still can and then make sure there are no ring-3 calls.
*/
# ifdef VBOX_WITH_REM
# endif
# endif
# ifdef IN_RING0
# else
# endif
# ifndef PGM_WITHOUT_MAPPINGS
/*
* Apply all hypervisor mappings to the new CR3.
* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
* make sure we check for conflicts in the new CR3 root.
*/
Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
# endif
# endif
/* Set the current hypervisor CR3. */
# ifdef IN_RC
/* NOTE: The state is consistent again. */
# endif
/* Clean up the old CR3 root. */
if ( pOldShwPageCR3
&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
{
# ifndef PGM_WITHOUT_MAPPINGS
/* Remove the hypervisor mappings from the shadow page table. */
# endif
/* Mark the page as unlocked; allow flushing again. */
}
# else
# endif
return rc;
}
/**
* Unmaps the shadow CR3.
*
* @returns VBox status, no specials.
* @param pVCpu Pointer to the VMCPU.
*/
{
LogFlow(("UnmapCR3\n"));
int rc = VINF_SUCCESS;
/*
* Update guest paging info.
*/
#if PGM_GST_TYPE == PGM_TYPE_32BIT
# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
# endif
# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
# endif
for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
{
# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
# endif
}
# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
# endif
/* nothing to do */
#endif
#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
/*
* Update shadow paging info.
*/
# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
|| PGM_SHW_TYPE == PGM_TYPE_PAE \
|| PGM_SHW_TYPE == PGM_TYPE_AMD64))
# if PGM_GST_TYPE != PGM_TYPE_REAL
# endif
# ifndef PGM_WITHOUT_MAPPINGS
/* Remove the hypervisor mappings from the shadow page table. */
# endif
{
# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
if (pPool->cDirtyPages)
# endif
/* Mark the page as unlocked; allow flushing again. */
pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
}
# endif
#endif /* !IN_RC*/
return rc;
}