cpum.h revision 41d680dd6eb0287afc200adc5b0d61b07a32b72d
/** @file
* CPUM - CPU Monitor(/ Manager).
*/
/*
* Copyright (C) 2006-2013 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* The contents of this file may alternatively be used under the terms
* of the Common Development and Distribution License Version 1.0
* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
* VirtualBox OSE distribution, in which case the provisions of the
* CDDL are applicable instead of those of the GPL.
*
* You may elect to license modified versions of this file under the
* terms and conditions of either the GPL or the CDDL or both.
*/
#ifndef ___VBox_vmm_cpum_h
#define ___VBox_vmm_cpum_h
/** @defgroup grp_cpum The CPU Monitor / Manager API
* @{
*/
/**
* CPUID feature to set or clear.
*/
typedef enum CPUMCPUIDFEATURE
{
/** The APIC feature bit. (Std+Ext) */
/** The PAE feature bit. (Std+Ext) */
/** The NX feature bit. (Ext) */
/** The LONG MODE feature bit. (Ext) */
/** The PAT feature bit. (Std+Ext) */
/** The x2APIC feature bit. (Std) */
/** The RDTSCP feature bit. (Ext) */
/** The Hypervisor Present bit. (Std) */
/** 32bit hackishness. */
CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
/**
* CPU Vendor.
*/
typedef enum CPUMCPUVENDOR
{
/** 32bit hackishness. */
CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
/**
* X86 and AMD64 CPU microarchitectures and in processor generations.
*
* @remarks The separation here is sometimes a little bit too finely grained,
* and the differences is more like processor generation than micro
* arch. This can be useful, so we'll provide functions for getting at
* more coarse grained info.
*/
typedef enum CPUMMICROARCH
{
kCpumMicroarch_Intel_Core_Yonah, /**< Core, also known as Enhanced Pentium M. */
kCpumMicroarch_Intel_Atom_Lincroft, /**< Second generation bonnell (44nm). */
kCpumMicroarch_Intel_Atom_Saltwell, /**< 32nm shrink of Bonnell. */
kCpumMicroarch_Intel_Atom_Silvermont, /**< 22nm */
kCpumMicroarch_Intel_Atom_Airmount, /**< 14nm */
kCpumMicroarch_Intel_Atom_Goldmont, /**< 14nm */
kCpumMicroarch_Intel_NB_Northwood, /**< 130nm */
kCpumMicroarch_Intel_NB_Prescott, /**< 90nm */
kCpumMicroarch_Intel_NB_Prescott2M, /**< 90nm */
kCpumMicroarch_Intel_NB_CedarMill, /**< 65nm */
kCpumMicroarch_Intel_NB_Gallatin, /**< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). */
kCpumMicroarch_AMD_Am486Enh, /**< Covers Am5x86 as well. */
kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /**< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin */
kCpumMicroarch_AMD_K8_90nm, /**< 90nm shrink */
kCpumMicroarch_AMD_K8_90nm_DualCore, /**< 90nm with two cores. */
kCpumMicroarch_AMD_K8_90nm_AMDV, /**< 90nm with AMD-V (usually) and two cores (usually). */
kCpumMicroarch_AMD_K8_65nm, /**< 65nm shrink. */
kCpumMicroarch_AMD_15h_Steamroller, /**< Yet to be released, might have different family. */
kCpumMicroarch_AMD_15h_Excavator, /**< Yet to be released, might have different family. */
kCpumMicroarch_VIA_C3_C5A, /**< 180nm Samuel - Cyrix III, C3, 1GigaPro. */
kCpumMicroarch_VIA_C3_C5B, /**< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. */
kCpumMicroarch_VIA_C3_C5C, /**< 130nm Ezra - C3, Eden ESP. */
kCpumMicroarch_VIA_C3_C5N, /**< 130nm Ezra-T - C3. */
kCpumMicroarch_VIA_C3_C5XL, /**< 130nm Nehemiah - C3, Eden ESP, Eden-N. */
kCpumMicroarch_VIA_C3_C5P, /**< 130nm Nehemiah+ - C3. */
kCpumMicroarch_VIA_C7_C5J, /**< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. */
kCpumMicroarch_32BitHack = 0x7fffffff
/** Predicate macro for catching netburst CPUs. */
#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
/** Predicate macro for catching Core7 CPUs. */
#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
/** Predicate macro for catching AMD Family 8H CPUs (aka K8). */
#define CPUMMICROARCH_IS_AMD_FAM_8H(a_enmMicroarch) \
/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
* decendants). */
#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
/** Predicate macro for catching AMD Family 16H CPUs. */
#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
/**
* CPUID leaf.
*/
typedef struct CPUMCPUIDLEAF
{
/** The leaf number. */
/** The sub-leaf number. */
/** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
/** The EAX value. */
/** The EBX value. */
/** The ECX value. */
/** The EDX value. */
/** Flags. */
/** Pointer to a CPUID leaf. */
typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
/** Pointer to a const CPUID leaf. */
typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF;
/** @name CPUMCPUIDLEAF::fFlags
* @{ */
/** Indicates that ECX (the sub-leaf indicator) doesn't change when
* requesting the final leaf and all undefined leaves that follows it.
* Observed for 0x0000000b on Intel. */
#define CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED RT_BIT_32(0)
/** @} */
/**
* Method used to deal with unknown CPUID leafs.
*/
typedef enum CPUMUKNOWNCPUID
{
/** Invalid zero value. */
/** Use given default values (DefCpuId). */
/** Return the last standard leaf.
* Intel Sandy Bridge has been observed doing this. */
/** Return the last standard leaf, with ecx observed.
* Intel Sandy Bridge has been observed doing this. */
/** The register values are passed thru unmodified. */
/** End of valid value. */
/** Ensure 32-bit type. */
CPUMUKNOWNCPUID_32BIT_HACK = 0x7fffffff
/** Pointer to unknown CPUID leaf method. */
typedef CPUMUKNOWNCPUID *PCPUMUKNOWNCPUID;
/** @name Guest Register Getters.
* @{ */
VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
/** @} */
/** @name Guest Register Setters.
* @{ */
/** @} */
/** @name Misc Guest Predicate Functions.
* @{ */
#ifndef VBOX_WITHOUT_UNNAMED_UNIONS
/**
* Tests if the guest is running in real mode or not.
*
* @returns true if in real mode, otherwise false.
* @param pCtx Current CPU context
*/
{
}
/**
* Tests if the guest is running in real or virtual 8086 mode.
*
* @returns @c true if it is, @c false if not.
* @param pCtx Current CPU context
*/
{
|| pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
}
/**
* Tests if the guest is running in virtual 8086 mode.
*
* @returns @c true if it is, @c false if not.
* @param pCtx Current CPU context
*/
{
}
/**
* Tests if the guest is running in paged protected or not.
*
* @returns true if in paged protected mode, otherwise false.
* @param pVM The VM handle.
*/
{
}
/**
* Tests if the guest is running in long mode or not.
*
* @returns true if in long mode, otherwise false.
* @param pCtx Current CPU context
*/
{
}
/**
* Tests if the guest is running in 64 bits mode or not.
*
* @returns true if in 64 bits protected mode, otherwise false.
* @param pVCpu The current virtual CPU.
* @param pCtx Current CPU context
*/
{
return false;
return CPUMIsGuestIn64BitCodeSlow(pCtx);
}
/**
* Tests if the guest has paging enabled or not.
*
* @returns true if paging is enabled, otherwise false.
* @param pCtx Current CPU context
*/
{
}
/**
* Tests if the guest is running in PAE mode or not.
*
* @returns true if in PAE mode, otherwise false.
* @param pCtx Current CPU context
*/
{
/* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
}
#endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
/** @} */
/** @name Hypervisor Register Getters.
* @{ */
#if 0 /* these are not correct. */
#endif
/** This register is only saved on fatal traps. */
/** This register is only saved on fatal traps. */
/** This register is only saved on fatal traps. */
/** @} */
/** @name Hypervisor Register Setters.
* @{ */
VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX);
/** @} */
/** @name Changed flags.
* These flags are used to keep track of which important register that
* have been changed since last they were reset. The only one allowed
* to clear them is REM!
* @{
*/
#define CPUM_CHANGED_FPU_REM RT_BIT(0)
#define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
| CPUM_CHANGED_CR0 \
| CPUM_CHANGED_CR4 \
| CPUM_CHANGED_CR3 \
| CPUM_CHANGED_TR \
/** @} */
#ifdef IN_RING3
/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
* @ingroup grp_cpum
* @{
*/
VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
/** @} */
#endif /* IN_RING3 */
#ifdef IN_RC
/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
* @ingroup grp_cpum
* @{
*/
/**
*
* Assumes a trap stack frame has already been setup on the guest's stack!
* This function does not return!
*
* @param selCS Code selector of handler
* @param pHandler GC virtual address of handler
* @param eflags Callee's EFLAGS
* @param selSS Stack selector for handler
* @param pEsp Stack address for handler
*/
/**
* Call guest V86 code directly.
*
* This function does not return!
*
*/
#ifdef VBOX_WITH_RAW_RING1
#endif
/** @} */
#endif /* IN_RC */
#ifdef IN_RING0
/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
* @ingroup grp_cpum
* @{
*/
VMMR0_INT_DECL(int) CPUMR0ModuleInit(void);
VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void);
#endif
/** @} */
#endif /* IN_RING0 */
/** @} */
#endif