CPUMInternal.h revision 9f22c692723a5d3cb78b91896c48cf681c4fb608
/* $Id$ */
/** @file
* CPUM - Internal header file.
*/
/*
* Copyright (C) 2006-2012 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
#ifndef ___CPUMInternal_h
#define ___CPUMInternal_h
#ifndef VBOX_FOR_DTRACE_LIB
#else
#endif
/** @defgroup grp_cpum_int Internals
* @ingroup grp_cpum
* @internal
* @{
*/
/** Flags and types for CPUM fault handlers
* @{ */
/** Type: Load DS */
#define CPUM_HANDLER_DS 1
/** Type: Load ES */
#define CPUM_HANDLER_ES 2
/** Type: Load FS */
#define CPUM_HANDLER_FS 3
/** Type: Load GS */
#define CPUM_HANDLER_GS 4
/** Type: IRET */
#define CPUM_HANDLER_IRET 5
/** Type mask. */
#define CPUM_HANDLER_TYPEMASK 0xff
/** If set EBP points to the CPUMCTXCORE that's being used. */
/** @} */
/** Use flags (CPUM::fUseFlags).
* (Don't forget to sync this with CPUMInternal.mac !)
* @{ */
/** Used the FPU, SSE or such stuff. */
#define CPUM_USED_FPU RT_BIT(0)
/** Used the FPU, SSE or such stuff since last we were in REM.
* REM syncing is clearing this, lazy FPU is setting it. */
/** The XMM state was manually restored. (AMD only) */
/** Host OS is using SYSENTER and we must NULL the CS. */
/** Host OS is using SYSENTER and we must NULL the CS. */
/** Debug registers are used by host and that DR7 and DR6 must be saved and
* disabled when switching to raw-mode. */
/** Records that we've saved the host DRx registers.
* In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
* since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
* registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
/** Used in ring-0 to indicate that we have loaded the hypervisor debug
* registers. */
/** Used in ring-0 to indicate that we have loaded the guest debug
* registers (DR0-3 and maybe DR6) for direct use by the guest.
* DR7 (and AMD-V DR6) are handled via the VMCB. */
/** Sync the FPU state on next entry (32->64 switcher only). */
/** Sync the debug state on next entry (32->64 switcher only). */
/** Sync the debug state on next entry (32->64 switcher only).
* Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
/** @} */
/* Sanity check. */
#ifndef VBOX_FOR_DTRACE_LIB
# error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
#endif
#endif
/**
* MSR read functions.
*/
typedef enum CPUMMSRRDFN
{
/** Invalid zero value. */
kCpumMsrRdFn_Invalid = 0,
/** Return the CPUMMSRRANGE::uInitOrReadValue. */
/** Alias to the MSR range starting at the MSR given by
* CPUMMSRRANGE::uInitOrReadValue. Must be used in pair with
* kCpumMsrWrFn_MsrAlias. */
/** Write only register, GP all read attempts. */
kCpumMsrRdFn_Ia32MtrrCap, /**< Takes real CPU value for reference. */
kCpumMsrRdFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
kCpumMsrRdFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
kCpumMsrRdFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
kCpumMsrRdFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
kCpumMsrRdFn_Ia32PerfStatus, /**< Range value returned. */
kCpumMsrRdFn_Ia32PerfCtl, /**< Range value returned. */
kCpumMsrRdFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
kCpumMsrRdFn_Ia32PerfCapabilities, /**< Takes reference value. */
kCpumMsrRdFn_Ia32PerfGlobalStatus, /**< Takes reference value. */
kCpumMsrRdFn_Ia32ClockModulation, /**< Range value returned. */
kCpumMsrRdFn_Ia32ThermInterrupt, /**< Range value returned. */
kCpumMsrRdFn_Ia32ThermStatus, /**< Range value returned. */
kCpumMsrRdFn_Ia32Therm2Ctl, /**< Range value returned. */
kCpumMsrRdFn_Ia32MiscEnable, /**< Range value returned. */
kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
kCpumMsrRdFn_Ia32McNCtl2, /**< Takes register number of start of range. */
kCpumMsrRdFn_Ia32VmxBase, /**< Takes real value as reference. */
kCpumMsrRdFn_Ia32VmxPinbasedCtls, /**< Takes real value as reference. */
kCpumMsrRdFn_Ia32VmxProcbasedCtls, /**< Takes real value as reference. */
kCpumMsrRdFn_Ia32VmxExitCtls, /**< Takes real value as reference. */
kCpumMsrRdFn_Ia32VmxEntryCtls, /**< Takes real value as reference. */
kCpumMsrRdFn_Ia32VmxMisc, /**< Takes real value as reference. */
kCpumMsrRdFn_Ia32VmxCr0Fixed0, /**< Takes real value as reference. */
kCpumMsrRdFn_Ia32VmxCr0Fixed1, /**< Takes real value as reference. */
kCpumMsrRdFn_Ia32VmxCr4Fixed0, /**< Takes real value as reference. */
kCpumMsrRdFn_Ia32VmxCr4Fixed1, /**< Takes real value as reference. */
kCpumMsrRdFn_Ia32VmxVmcsEnum, /**< Takes real value as reference. */
kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /**< Takes real value as reference. */
kCpumMsrRdFn_Ia32VmxEptVpidCap, /**< Takes real value as reference. */
kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /**< Takes real value as reference. */
kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /**< Takes real value as reference. */
kCpumMsrRdFn_Ia32VmxTrueExitCtls, /**< Takes real value as reference. */
kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7TemperatureTarget, /**< Range value returned. */
kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/**< Takes register number. */
kCpumMsrRdFn_IntelI7TurboRatioLimit, /**< Returns range value. */
kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/**< Returns range value. */
kCpumMsrRdFn_IntelI7PkgCnResidencyN, /**< Takes C-state number. */
kCpumMsrRdFn_IntelI7CoreCnResidencyN, /**< Takes C-state number. */
kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7RaplPp0Policy, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7RaplPp1Policy, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /**< Takes real value as reference. */
kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /**< Range value returned. */
kCpumMsrRdFn_AmdK8SysCfg, /**< Range value returned. */
kCpumMsrRdFn_AmdK8HwThermalCtrl, /**< Range value returned. */
kCpumMsrRdFn_AmdFam10hPStateCurLimit, /**< Returns range value. */
kCpumMsrRdFn_AmdFam10hPStateControl, /**< Returns range value. */
kCpumMsrRdFn_AmdFam10hPStateStatus, /**< Returns range value. */
kCpumMsrRdFn_AmdFam10hPStateN, /**< Returns range value. This isn't an register index! */
kCpumMsrRdFn_AmdFam10hCofVidControl, /**< Returns range value. */
kCpumMsrRdFn_AmdFam10hCofVidStatus, /**< Returns range value. */
kCpumMsrRdFn_AmdK7MicrocodeCtl, /**< Returns range value. */
kCpumMsrRdFn_AmdK7ClusterIdMaybe, /**< Returns range value. */
kCpumMsrRdFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
/** End of valid MSR read function indexes. */
} CPUMMSRRDFN;
/**
* MSR write functions.
*/
typedef enum CPUMMSRWRFN
{
/** Invalid zero value. */
kCpumMsrWrFn_Invalid = 0,
/** Writes are ignored, the fWrGpMask is observed though. */
/** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
/** Alias to the MSR range starting at the MSR given by
* CPUMMSRRANGE::uInitOrReadValue. Must be used in pair with
* kCpumMsrRdFn_MsrAlias. */
kCpumMsrWrFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
kCpumMsrWrFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
kCpumMsrWrFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
kCpumMsrWrFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
kCpumMsrWrFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
kCpumMsrWrFn_Ia32McNCtl2, /**< Takes register number of start of range. */
kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /**< Takes register number. */
kCpumMsrWrFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
/** End of valid MSR write function indexes. */
} CPUMMSRWRFN;
/**
* MSR range.
*/
typedef struct CPUMMSRRANGE
{
/** The first MSR. [0] */
/** The last MSR. [4] */
/** The read function (CPUMMSRRDFN). [8] */
/** The write function (CPUMMSRWRFN). [10] */
/** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
* UINT16_MAX if not used by the read and write functions. [12] */
/** Reserved for future hacks. [14] */
* When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
* offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
* offset into CPUM. */
/** The bits to ignore when writing. [24] */
/** The bits that will cause a GP(0) when writing. [32]
* This is always checked prior to calling the write function. Using
* UINT64_MAX effectively marks the MSR as read-only. */
/** The register name, if applicable. [40] */
char szName[56];
#ifdef VBOX_WITH_STATISTICS
/** The number of reads. */
/** The number of writes. */
/** The number of times ignored bits were written. */
/** The number of GPs generated. */
#endif
} CPUMMSRRANGE;
#ifdef VBOX_WITH_STATISTICS
#else
#endif
/** Pointer to an MSR range. */
typedef CPUMMSRRANGE *PCPUMMSRRANGE;
/** Pointer to a const MSR range. */
typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
/**
* CPU features and quirks.
* This is mostly exploded CPUID info.
*/
typedef struct CPUMFEATURES
{
/** The CPU vendor (CPUMCPUVENDOR). */
/** The CPU family. */
/** The CPU model. */
/** The CPU stepping. */
/** The microarchitecture. */
/** The maximum physical address with of the CPU. */
/** Alignment padding. */
/** Supports MSRs. */
/** Supports the page size extension (4/2 MB pages). */
/** Supports 36-bit page size extension (4 MB pages can map memory above
* 4GB). */
/** Supports physical address extension (PAE). */
/** Page attribute table (PAT) support (page level cache control). */
/** Supports the FXSAVE and FXRSTOR instructions. */
/** First generation APIC. */
/** Second generation APIC. */
/** Hypervisor present. */
/** MWAIT & MONITOR instructions supported. */
/** AMD64: Supports long mode. */
/** AMD64: No-execute page table bit. */
/** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
/** AMD64: Supports RDTSCP. */
/** Indicates that FPU instruction and data pointers may leak.
* This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
* is only saved and restored if an exception is pending. */
/** Alignment padding. */
} CPUMFEATURES;
/** Pointer to a CPU feature structure. */
typedef CPUMFEATURES *PCPUMFEATURES;
/** Pointer to a const CPU feature structure. */
typedef CPUMFEATURES const *PCCPUMFEATURES;
/**
* CPU info
*/
typedef struct CPUMINFO
{
/** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
* instruction. Older hardware has been observed to ignore higher bits. */
/** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
/** The index of the first extended CPUID leaf in the array.
* Set to cCpuIdLeaves if none present. */
/** How to handle unknown CPUID leaves. */
/** For use with CPUMUKNOWNCPUID_DEFAULTS. */
/** Alignment padding. */
/** Pointer to the MSR ranges (ring-0 pointer). */
/** Pointer to the CPUID leaves (ring-0 pointer). */
/** Pointer to the MSR ranges (ring-3 pointer). */
/** Pointer to the CPUID leaves (ring-3 pointer). */
/** Pointer to the MSR ranges (raw-mode context pointer). */
/** Pointer to the CPUID leaves (raw-mode context pointer). */
} CPUMINFO;
/** Pointer to a CPU info structure. */
/** Pointer to a const CPU info structure. */
typedef CPUMINFO const *CPCPUMINFO;
/**
* The saved host CPU state.
*
* @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
* of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
*/
typedef struct CPUMHOSTCTX
{
/** FPU state. (16-byte alignment)
* @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
/** General purpose register, selectors, flags and more
* @{ */
/** General purpose register ++
* { */
/*uint64_t rax; - scratch*/
/*uint64_t rcx; - scratch*/
/*uint64_t rdx; - scratch*/
/*uint64_t r8; - scratch*/
/*uint64_t r9; - scratch*/
/*uint64_t rip; - scratch*/
#endif
#if HC_ARCH_BITS == 32
/*uint32_t eax; - scratch*/
/*uint32_t ecx; - scratch*/
/*uint32_t edx; - scratch*/
/*uint32_t eip; - scratch*/
/* lss pair! */
#endif
/** @} */
/** Selector registers
* @{ */
/** @} */
/** Control registers.
* @{ */
/*uint32_t cr2; - scratch*/
/** @} */
/** Debug registers.
* @{ */
/** @} */
/** Global Descriptor Table register. */
/** Interrupt Descriptor Table register. */
/** The task register. */
/** The task register. */
/** The sysenter msr registers.
* This member is not used by the hypervisor context. */
/** MSRs
* @{ */
/** @} */
/* padding to get 64byte aligned size */
/** Control registers.
* @{ */
/*uint64_t cr2; - scratch*/
/** @} */
/** Debug registers.
* @{ */
/** @} */
/** Global Descriptor Table register. */
/** Interrupt Descriptor Table register. */
/** The task register. */
/** The task register. */
/** MSRs
* @{ */
/** @} */
/* padding to get 32byte aligned size */
# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
# else
# endif
#else
#endif
} CPUMHOSTCTX;
/** Pointer to the saved host CPU state. */
typedef CPUMHOSTCTX *PCPUMHOSTCTX;
/**
* CPUM Data (part of VM)
*/
typedef struct CPUM
{
/** Offset from CPUM to CPUMCPU for the first CPU. */
/** Use flags.
* These flags indicates which CPU features the host uses.
*/
/** Host CPU Features - ECX */
struct
{
/** edx part */
/** ecx part */
} CPUFeatures;
/** Host extended CPU features. */
struct
{
/** edx part */
/** ecx part */
/** CR4 mask */
struct
{
uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
} CR4;
/** The (more) portable CPUID level. */
/** Indicates that a state restore is pending.
* This is used to verify load order dependencies (PGM). */
bool fPendingRestore;
/** The standard set of CpuId leaves. */
/** The extended set of CpuId leaves. */
/** The centaur set of CpuId leaves. */
/** The hypervisor specific set of CpuId leaves. */
/** The default set of CpuId leaves. */
#if HC_ARCH_BITS == 32
#endif
/** Guest CPU info. */
/** Guest CPU feature information. */
/** Host CPU feature information. */
/** @name MSR statistics.
* @{ */
/** @} */
} CPUM;
/** Pointer to the CPUM instance data residing in the shared VM structure. */
/**
* CPUM Data (part of VMCPU)
*/
typedef struct CPUMCPU
{
/**
* Hypervisor context.
* Aligned on a 64-byte boundary.
*/
/**
* Saved host context. Only valid while inside GC.
* Aligned on a 64-byte boundary.
*/
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
#endif
/**
* Guest context.
* Aligned on a 64-byte boundary.
*/
/**
* Guest context - misc MSRs
* Aligned on a 64-byte boundary.
*/
/** Use flags.
* These flags indicates both what is to be used and what has been used.
*/
/** Changed flags.
* These flags indicates to REM (and others) which important guest
* registers which has been changed since last time the flags were cleared.
* See the CPUM_CHANGED_* defines for what we keep track of.
*/
/** Offset from CPUM to CPUMCPU. */
/** Temporary storage for the return code of the function called in the
* 32-64 switcher. */
/** The address of the APIC mapping, NULL if no APIC.
* Call CPUMR0SetLApic to update this before doing a world switch. */
/** Used by the world switcher code to store which vectors needs restoring on
* the way back. */
/** Set if the CPU has the X2APIC mode enabled.
* Call CPUMR0SetLApic to update this before doing a world switch. */
bool fX2Apic;
#else
#endif
/** Have we entered raw-mode? */
bool fRawEntered;
/** Have we entered the recompiler? */
bool fRemEntered;
/** Align the structure on a 64-byte boundary. */
} CPUMCPU;
/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
#ifndef VBOX_FOR_DTRACE_LIB
#ifdef IN_RING3
PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf);
bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast);
int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures);
int cpumR3MsrRangesInsert(PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
int cpumR3MsrStrictInitChecks(void);
#endif
#ifdef IN_RC
#endif
#ifdef IN_RING0
#endif
#endif /* !VBOX_FOR_DTRACE_LIB */
/** @} */
#endif