Searched defs:enable (Results 1 - 18 of 18) sorted by relevance

/solaris-x11-s11/open-src/app/accessx/sun-src/
H A DAccessXcomm.c236 BYTE enable)
238 void XAccessXSelectInput(dpy,accessXClient,enable)
241 BYTE enable;
247 req->enable = enable;
234 XAccessXSelectInput(Display *dpy, AccessXClientContextRec *accessXClient, BYTE enable) argument
H A DAccessXproto.h119 BYTE enable; /* True = send events. */ member in struct:__anon5
/solaris-x11-s11/open-src/kernel/i915/src/
H A Ddvo_ns2501.c107 DRM_DEBUG_KMS("%s: Trying to re-enable the DVO\n", __FUNCTION__);
144 ** If it returns false, it might be wise to enable the
189 ** If it returns false, it might be wise to enable the
518 static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable) argument
526 __FUNCTION__, enable);
530 if (enable)
544 enable ? 0x03 : 0x00);
547 enable ? 0xff : 0x00);
H A Ddvo_sil164.c222 static void sil164_dpms(struct intel_dvo_device *dvo, bool enable) argument
231 if (enable)
H A Ddvo_ivch.c297 static void ivch_dpms(struct intel_dvo_device *dvo, bool enable) argument
306 if (enable)
312 if (enable)
324 if (((vr30 & VR30_PANEL_ON) != 0) == enable)
H A Ddvo_tfp410.c250 static void tfp410_dpms(struct intel_dvo_device *dvo, bool enable) argument
257 if (enable)
H A Dintel_i2c.c72 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) argument
81 if (enable)
456 * We will re-enable it at the start of the next xfer,
H A Ddvo_ch7xxx.c324 static void ch7xxx_dpms(struct intel_dvo_device *dvo, bool enable) argument
326 if (enable)
H A Ddvo_ch7017.c170 static void ch7017_dpms(struct intel_dvo_device *dvo, bool enable);
342 static void ch7017_dpms(struct intel_dvo_device *dvo, bool enable) argument
356 if (enable) {
H A Di915_gem.c56 bool enable);
2183 * and only enable the fence as the last step.
2335 bool enable)
2340 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2342 if (enable) {
2442 bool enable = obj->tiling_mode != I915_TILING_NONE; local
2463 } else if (enable) {
2480 i915_gem_object_update_fence(obj, reg, enable);
3270 /* Don't enable buffer catch */
3579 ret = dev_priv->mm.aliasing_ppgtt->enable(de
2333 i915_gem_object_update_fence(struct drm_i915_gem_object *obj, struct drm_i915_fence_reg *fence, bool enable) argument
[all...]
H A Di915_irq.c143 enum pipe pipe, bool enable)
149 if (enable)
156 bool enable)
160 if (enable) {
175 bool enable)
182 if (enable)
192 bool enable)
196 if (enable) {
213 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
216 * @enable
142 ironlake_set_fifo_underrun_reporting(struct drm_device *dev, enum pipe pipe, bool enable) argument
155 ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, bool enable) argument
174 ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc, bool enable) argument
190 cpt_set_fifo_underrun_reporting(struct drm_device *dev, enum transcoder pch_transcoder, bool enable) argument
226 intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, enum pipe pipe, bool enable) argument
268 intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, enum transcoder pch_transcoder, bool enable) argument
[all...]
H A Dintel_drv.h115 void (*enable)(struct intel_encoder *); member in struct:intel_encoder
336 bool enable; member in struct:intel_plane::__anon163
746 int pixel_size, bool enable);
774 extern void intel_set_power_well(struct drm_device *dev, bool enable);
801 bool enable);
804 bool enable);
H A Dintel_pm.c110 /* enable it... */
151 /* enable it... */
224 /* enable it... */
364 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
411 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
421 * and indeed performing the enable as a co-routine and not
441 * intel_update_fbc - enable/disable FBC as needed
445 * enable it if possible:
457 * We need to enable/disable FBC on a global basis.
1715 /* enable FB
2182 bool enable; member in struct:hsw_lp_wm_result
2635 haswell_update_sprite_wm(struct drm_device *dev, int pipe, uint32_t sprite_width, int pixel_size, bool enable) argument
2731 sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, uint32_t sprite_width, int pixel_size, bool enable) argument
2854 intel_update_sprite_watermarks(struct drm_device *dev, int pipe, uint32_t sprite_width, int pixel_size, bool enable) argument
4553 __intel_set_power_well(struct drm_device *dev, bool enable) argument
4646 intel_set_power_well(struct drm_device *dev, bool enable) argument
[all...]
H A Dintel_sdvo_regs.h618 unsigned int enable:1; member in struct:sdvo_set_ambient_light_reply
H A Dintel_display.c1305 * intel_enable_pll - enable a PLL
1307 * @pipe: pipe PLL to enable
1390 * ironlake_enable_pch_pll - enable PCH PLL
1392 * @pipe: pipe PLL to enable
1413 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1425 pll->enable(dev_priv, pll);
1518 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1549 DRM_ERROR("Failed to enable PCH transcoder\n");
1600 * intel_enable_pipe - enable a pipe, asserting requirements
1602 * @pipe: pipe to enable
3528 intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) argument
3784 bool enable = false; local
5932 bool enable = false; local
[all...]
H A Di915_drv.h157 void (*enable)(struct drm_i915_private *dev_priv, member in struct:intel_shared_dpll
370 bool enable);
512 int (*enable)(struct drm_device *dev); member in struct:i915_hw_ppgtt
799 /* power well enable/disable usage count */
/solaris-x11-s11/open-src/kernel/drm/src/
H A Ddrm_fb_helper.c510 bool enable; local
513 enable = connector->status == connector_status_connected;
515 enable = connector->status != connector_status_disconnected;
517 return enable;
613 DRM_INFO("kms: can't enable cloning when we probably wanted to.\n");
/solaris-x11-s11/open-src/lib/DPS/sun-src/libdpstk/
H A DXDPSshare.c587 int XDPSChainTextContext(DPSContext context, Bool enable) argument
595 if (c->enableText == enable) return dps_status_success;
597 if (enable) {

Completed in 89 milliseconds