Lines Matching defs:enable
1305 * intel_enable_pll - enable a PLL
1307 * @pipe: pipe PLL to enable
1390 * ironlake_enable_pch_pll - enable PCH PLL
1392 * @pipe: pipe PLL to enable
1413 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1425 pll->enable(dev_priv, pll);
1518 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1549 DRM_ERROR("Failed to enable PCH transcoder\n");
1600 * intel_enable_pipe - enable a pipe, asserting requirements
1602 * @pipe: pipe to enable
1710 * intel_enable_plane - enable a display plane on a given pipe
1712 * @plane: plane to enable
2231 /* enable normal train */
2279 * When everything is off disable fdi C so that we could enable fdi B
2319 /* enable CPU FDI TX and PCH FDI RX */
2337 /* Ironlake workaround, enable clock pointer after FDI enable*/
2417 /* enable CPU FDI TX and PCH FDI RX */
2552 /* enable CPU FDI TX and PCH FDI RX */
2654 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2943 /* XXX: pch pll's can be enabled any time before we enable the PCH
2949 * enable sequence. */
2971 /* For PCH DP, enable TRANS_DP_CTL */
3214 /* Note: FDI PLL enabling _must_ be done before we enable the
3249 encoder->enable(encoder);
3278 /* We can only enable IPS after we enable a plane and wait for a vblank.
3281 * for a vblank, so all we need to do here is to enable the IPS bit. */
3359 encoder->enable(encoder);
3528 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3530 if (!enable && intel_crtc->overlay) {
3625 encoder->enable(encoder);
3676 /* Give the overlay scaler a chance to enable if it's on this pipe */
3682 encoder->enable(encoder);
3784 bool enable = false;
3787 enable |= intel_encoder->connectors_active;
3789 if (enable)
3794 intel_crtc_update_sarea(crtc, enable);
3994 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4340 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5071 /* As we must carefully and slowly disable/enable each source in turn,
5107 /* Always enable nonspread source */
5174 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5932 bool enable = false;
5941 enable = true;
5944 intel_set_power_well(dev, enable);
6192 /* Audio output enable */
6193 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
8460 /* mode_set/enable/disable functions rely on a correct pipe
8482 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8920 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9686 * proper mode and output configuration. As a gross hack, enable pipe A
9769 /* BIOS forgot to enable pipe A, this mostly happens after
9770 * resume. Force-enable the pipe to fix this, the update_dpms
10082 * set vga decode state - true == enable VGA decode