Searched refs:channel (Results 1 - 25 of 263) sorted by relevance

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/illumos-gate/usr/src/uts/common/io/xge/hal/xgehal/
H A Dxgehal-channel.c24 #include "xgehal-channel.h"
39 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
41 if (channel->reserve_top >= channel->reserve_length) {
45 *dtrh = channel->reserve_arr[channel->reserve_top++];
58 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
60 if (channel->reserve_initial == channel->free_length) {
64 *dtrh = channel
100 xge_hal_channel_t *channel; local
139 __hal_channel_free(xge_hal_channel_t *channel) argument
171 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
226 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
303 xge_hal_channel_t *channel = NULL; local
429 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
522 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
[all...]
H A Dxgehal-channel-fp.c25 #include "xgehal-channel.h"
32 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
36 if (channel->terminating) {
40 if (channel->reserve_length - channel->reserve_top >
41 channel->reserve_threshold) {
44 *dtrh = channel->reserve_arr[--channel->reserve_length];
47 "channel %d:%d:%d, reserve_idx %d",
49 channel
114 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
140 xge_hal_channel_t *channel = (xge_hal_channel_t*)channelh; local
154 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
165 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
179 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
200 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
220 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
236 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
[all...]
H A Dxgehal-ring.c105 xge_os_dma_sync(ring->channel.pdev,
209 __hal_ring_initial_replenish(xge_hal_channel_t *channel, argument
214 while (xge_hal_channel_dtr_count(channel) > 0) {
217 status = xge_hal_ring_dtr_reserve(channel, &dtr);
220 if (channel->dtr_init) {
221 status = channel->dtr_init(channel,
222 dtr, channel->reserve_length,
223 channel->userdata,
226 xge_hal_ring_dtr_free(channel, dt
606 xge_hal_channel_t *channel = NULL; local
[all...]
/illumos-gate/usr/src/uts/common/sys/fibre-channel/
H A Dfc.h33 #include <sys/fibre-channel/fc_types.h>
H A Dfc_types.h162 #include <sys/fibre-channel/impl/fcph.h>
163 #include <sys/fibre-channel/fc_appif.h>
164 #include <sys/fibre-channel/impl/fc_linkapp.h>
165 #include <sys/fibre-channel/impl/fcgs2.h>
166 #include <sys/fibre-channel/impl/fc_fla.h>
167 #include <sys/fibre-channel/impl/fcal.h>
168 #include <sys/fibre-channel/impl/fctl.h>
169 #include <sys/fibre-channel/impl/fc_error.h>
170 #include <sys/fibre-channel/fcio.h>
171 #include <sys/fibre-channel/ul
[all...]
/illumos-gate/usr/src/uts/common/sys/
H A Dbscbus.h42 * Register spaces (as lombus.h but spaces now have a channel
52 * * xx is the channel number.
57 #define LOMBUS_SPACE(regset, channel) ((regset) | ((channel) << 8))
/illumos-gate/usr/src/uts/common/io/
H A Ddcopy.c45 /* Number of entries per channel to allocate */
86 /* DMA channel state */
88 /* DMA driver channel private pointer */
95 * number of outstanding allocs for this channel. used to track when
96 * it's safe to free up this channel so the DMA device driver can
101 /* state for if channel needs to be removed when ch_ref_cnt gets to 0 */
108 * per channel list of commands actively blocking waiting for
158 static int dcopy_stats_init(dcopy_handle_t channel);
159 static void dcopy_stats_fini(dcopy_handle_t channel);
285 dcopy_handle_t channel; local
326 dcopy_free(dcopy_handle_t *channel) argument
376 dcopy_query_channel(dcopy_handle_t channel, dcopy_query_channel_t *query) argument
388 dcopy_handle_t channel; local
418 dcopy_handle_t channel; local
443 dcopy_handle_t channel; local
469 dcopy_handle_t channel; local
604 struct dcopy_channel_s *channel; local
723 struct dcopy_channel_s *channel; local
779 struct dcopy_channel_s *channel; local
823 struct dcopy_channel_s *channel; local
876 dcopy_stats_init(dcopy_handle_t channel) argument
931 dcopy_stats_fini(dcopy_handle_t channel) argument
[all...]
/illumos-gate/usr/src/uts/common/io/hxge/
H A Dhpi_txdma.c35 uint8_t channel);
38 hpi_txdma_log_page_handle_set(hpi_handle_t handle, uint8_t channel, argument
43 if (!TXDMA_CHANNEL_VALID(channel)) {
46 " Invalid Input: channel <0x%x>", channel));
47 return (HPI_FAILURE | HPI_TXDMA_CHANNEL_INVALID(channel));
50 TXDMA_REG_WRITE64(handle, TDC_PAGE_HANDLE, channel, hdl_p->value);
56 hpi_txdma_channel_reset(hpi_handle_t handle, uint8_t channel) argument
59 " hpi_txdma_channel_reset" " RESETTING", channel));
60 return (hpi_txdma_channel_control(handle, TXDMA_RESET, channel));
64 hpi_txdma_channel_init_enable(hpi_handle_t handle, uint8_t channel) argument
70 hpi_txdma_channel_enable(hpi_handle_t handle, uint8_t channel) argument
76 hpi_txdma_channel_disable(hpi_handle_t handle, uint8_t channel) argument
82 hpi_txdma_channel_mbox_enable(hpi_handle_t handle, uint8_t channel) argument
88 hpi_txdma_channel_control(hpi_handle_t handle, txdma_cs_cntl_t control, uint8_t channel) argument
167 hpi_txdma_control_status(hpi_handle_t handle, io_op_t op_mode, uint8_t channel, tdc_stat_t *cs_p) argument
205 hpi_txdma_event_mask(hpi_handle_t handle, io_op_t op_mode, uint8_t channel, tdc_int_mask_t *mask_p) argument
243 hpi_txdma_ring_config(hpi_handle_t handle, io_op_t op_mode, uint8_t channel, uint64_t *reg_data) argument
274 hpi_txdma_mbox_config(hpi_handle_t handle, io_op_t op_mode, uint8_t channel, uint64_t *mbox_addr) argument
383 hpi_txdma_ring_head_get(hpi_handle_t handle, uint8_t channel, tdc_tdr_head_t *hdl_p) argument
437 hpi_txdma_control_reset_wait(hpi_handle_t handle, uint8_t channel) argument
466 hpi_txdma_control_stop_wait(hpi_handle_t handle, uint8_t channel) argument
[all...]
H A Dhxge_defs.h79 * Locate the DMA channel start offset (PIO_VADDR)
84 #define TDMC_PIOVADDR_OFFSET(channel) (2 * DMA_CSR_SIZE * channel)
85 #define RDMC_PIOVADDR_OFFSET(channel) (TDMC_OFFSET(channel) + DMA_CSR_SIZE)
90 #define DMC_OFFSET(channel) (DMA_CSR_SIZE * channel)
91 #define TDMC_OFFSET(channel) (TX_RNG_CFIG + DMA_CSR_SIZE * channel)
H A Dhpi_txdma.h48 #define HXGE_TXDMA_OFFSET(x, v, channel) (x + \
49 (!v ? DMC_OFFSET(channel) : TDMC_PIOVADDR_OFFSET(channel)))
53 #define TXDMA_REG_READ64(handle, reg, channel, val_p) \
55 (HXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel)), val_p)
57 #define TXDMA_REG_WRITE64(handle, reg, channel, data) \
59 HXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel), data)
104 uint8_t channel, tdc_page_handle_t *hdl_p);
105 hpi_status_t hpi_txdma_channel_reset(hpi_handle_t handle, uint8_t channel);
107 uint8_t channel);
[all...]
H A Dhxge_fzc.h42 hxge_status_t hxge_init_fzc_txdma_channel(p_hxge_t hxgep, uint16_t channel,
45 hxge_status_t hxge_init_fzc_rxdma_channel(p_hxge_t hxgep, uint16_t channel,
51 uint16_t channel, p_rx_rbr_ring_t rbr_p);
54 uint16_t channel, p_tx_ring_t tx_ring_p);
H A Dhxge_txdma.c59 static hxge_status_t hxge_map_txdma_channel(p_hxge_t hxgep, uint16_t channel,
63 static void hxge_unmap_txdma_channel(p_hxge_t hxgep, uint16_t channel,
73 static hxge_status_t hxge_txdma_start_channel(p_hxge_t hxgep, uint16_t channel,
75 static hxge_status_t hxge_txdma_stop_channel(p_hxge_t hxgep, uint16_t channel,
77 static p_tx_ring_t hxge_txdma_get_ring(p_hxge_t hxgep, uint16_t channel);
80 static p_tx_mbox_t hxge_txdma_get_mbox(p_hxge_t hxgep, uint16_t channel);
82 uint16_t channel, p_tx_ring_t tx_ring_p);
152 hxge_reset_txdma_channel(p_hxge_t hxgep, uint16_t channel, uint64_t reg_data) argument
162 rs = hpi_txdma_channel_reset(handle, channel);
164 rs = hpi_txdma_channel_control(handle, TXDMA_RESET, channel);
183 hxge_init_txdma_channel_event_mask(p_hxge_t hxgep, uint16_t channel, tdc_int_mask_t *mask_p) argument
212 hxge_enable_txdma_channel(p_hxge_t hxgep, uint16_t channel, p_tx_ring_t tx_desc_p, p_tx_mbox_t mbox_p) argument
809 uint8_t channel; local
912 uint16_t channel; local
986 hxge_txdma_enable_channel(p_hxge_t hxgep, uint16_t channel) argument
1001 hxge_txdma_disable_channel(p_hxge_t hxgep, uint16_t channel) argument
1016 hxge_txdma_stop_inj_err(p_hxge_t hxgep, int channel) argument
1052 uint16_t channel; local
1097 hxge_txdma_fix_channel(p_hxge_t hxgep, uint16_t channel) argument
1123 hxge_txdma_fixup_channel(p_hxge_t hxgep, p_tx_ring_t ring_p, uint16_t channel) argument
1156 uint16_t channel; local
1195 hxge_txdma_kick_channel(p_hxge_t hxgep, uint16_t channel) argument
1221 hxge_txdma_hw_kick_channel(p_hxge_t hxgep, p_tx_ring_t ring_p, uint16_t channel) argument
1255 uint16_t channel; local
1297 hxge_txdma_channel_hung(p_hxge_t hxgep, p_tx_ring_t tx_ring_p, uint16_t channel) argument
1357 uint16_t channel; local
1395 hxge_txdma_fix_hung_channel(p_hxge_t hxgep, uint16_t channel) argument
1419 hxge_txdma_fixup_hung_channel(p_hxge_t hxgep, p_tx_ring_t ring_p, uint16_t channel) argument
1476 uint16_t channel; local
1522 uint16_t channel; local
1626 uint8_t channel; local
1683 hxge_map_txdma_channel(p_hxge_t hxgep, uint16_t channel, p_hxge_dma_common_t *dma_buf_p, p_tx_ring_t *tx_desc_p, uint32_t num_chunks, p_hxge_dma_common_t *dma_cntl_p, p_tx_mbox_t *tx_mbox_p) argument
1731 hxge_unmap_txdma_channel(p_hxge_t hxgep, uint16_t channel, p_tx_ring_t tx_ring_p, p_tx_mbox_t tx_mbox_p) argument
1854 hxge_map_txdma_channel_buf_ring(p_hxge_t hxgep, uint16_t channel, p_hxge_dma_common_t *dma_buf_p, p_tx_ring_t *tx_desc_p, uint32_t num_chunks) argument
2082 uint16_t channel; local
2261 uint16_t channel; local
2309 hxge_txdma_start_channel(p_hxge_t hxgep, uint16_t channel, p_tx_ring_t tx_ring_p, p_tx_mbox_t tx_mbox_p) argument
2375 hxge_txdma_stop_channel(p_hxge_t hxgep, uint16_t channel, p_tx_ring_t tx_ring_p, p_tx_mbox_t tx_mbox_p) argument
2407 hxge_txdma_get_ring(p_hxge_t hxgep, uint16_t channel) argument
2454 hxge_txdma_get_mbox(p_hxge_t hxgep, uint16_t channel) argument
2515 uint8_t channel; local
2725 hxge_txdma_fatal_err_recover(p_hxge_t hxgep, uint16_t channel, p_tx_ring_t tx_ring_p) argument
2842 uint16_t channel; local
[all...]
/illumos-gate/usr/src/uts/i86pc/io/ioat/
H A Dioat_chan.c88 static int ioat_completion_alloc(ioat_channel_t channel);
89 static void ioat_completion_free(ioat_channel_t channel);
90 static void ioat_channel_start(ioat_channel_t channel);
91 static void ioat_channel_reset(ioat_channel_t channel);
93 int ioat_ring_alloc(ioat_channel_t channel, uint_t desc_cnt);
94 void ioat_ring_free(ioat_channel_t channel);
95 void ioat_ring_seed(ioat_channel_t channel, ioat_chan_dma_desc_t *desc);
96 int ioat_ring_reserve(ioat_channel_t channel, ioat_channel_ring_t *ring,
113 * initialize each dma channel's state which doesn't change across
114 * channel allo
155 struct ioat_channel_s *channel; local
296 ioat_channel_t channel; local
390 ioat_channel_t channel = state->is_channel + i; local
411 struct ioat_channel_s *channel; local
449 ioat_channel_intr(ioat_channel_t channel) argument
501 ioat_channel_start(ioat_channel_t channel) argument
521 ioat_channel_reset(ioat_channel_t channel) argument
543 ioat_completion_alloc(ioat_channel_t channel) argument
607 ioat_completion_free(ioat_channel_t channel) argument
629 ioat_ring_alloc(ioat_channel_t channel, uint_t desc_cnt) argument
725 ioat_ring_free(ioat_channel_t channel) argument
763 ioat_ring_seed(ioat_channel_t channel, ioat_chan_dma_desc_t *in_desc) argument
822 ioat_channel_t channel; local
880 ioat_channel_t channel; local
932 ioat_channel_t channel; local
962 ioat_channel_t channel; local
1126 ioat_channel_t channel; local
1217 ioat_channel_t channel; local
1298 ioat_channel_t channel; local
1383 ioat_ring_reserve(ioat_channel_t channel, ioat_channel_ring_t *ring, dcopy_cmd_t cmd) argument
[all...]
/illumos-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_txdma.c36 uint8_t channel);
38 uint8_t channel);
40 uint8_t channel);
285 * channel - hardware TXDMA channel from 0 to 23.
297 npi_txdma_log_page_set(npi_handle_t handle, uint8_t channel, argument
305 DMA_LOG_PAGE_FN_VALIDATE(channel, cfgp->page_num, cfgp->func_num,
314 TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG, channel, 0);
315 TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel, &val);
322 TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel,
390 npi_txdma_log_page_get(npi_handle_t handle, uint8_t channel, p_dma_log_page_t cfgp) argument
460 npi_txdma_log_page_handle_set(npi_handle_t handle, uint8_t channel, p_log_page_hdl_t hdl_p) argument
508 npi_txdma_log_page_config(npi_handle_t handle, io_op_t op_mode, txdma_log_cfg_t type, uint8_t channel, p_dma_log_page_t cfgp) argument
668 npi_txdma_log_page_vld_config(npi_handle_t handle, io_op_t op_mode, uint8_t channel, p_log_page_vld_t vld_p) argument
739 npi_txdma_channel_reset(npi_handle_t handle, uint8_t channel) argument
766 npi_txdma_channel_init_enable(npi_handle_t handle, uint8_t channel) argument
790 npi_txdma_channel_enable(npi_handle_t handle, uint8_t channel) argument
814 npi_txdma_channel_disable(npi_handle_t handle, uint8_t channel) argument
838 npi_txdma_channel_resume(npi_handle_t handle, uint8_t channel) argument
861 npi_txdma_channel_mmk_clear(npi_handle_t handle, uint8_t channel) argument
885 npi_txdma_channel_mbox_enable(npi_handle_t handle, uint8_t channel) argument
919 npi_txdma_channel_control(npi_handle_t handle, txdma_cs_cntl_t control, uint8_t channel) argument
1036 npi_txdma_control_status(npi_handle_t handle, io_op_t op_mode, uint8_t channel, p_tx_cs_t cs_p) argument
1101 npi_txdma_event_mask(npi_handle_t handle, io_op_t op_mode, uint8_t channel, p_tx_dma_ent_msk_t mask_p) argument
1167 npi_txdma_event_mask_config(npi_handle_t handle, io_op_t op_mode, uint8_t channel, txdma_ent_msk_cfg_t *mask_cfgp) argument
1232 npi_txdma_event_mask_mk_out(npi_handle_t handle, uint8_t channel) argument
1269 npi_txdma_event_mask_mk_in(npi_handle_t handle, uint8_t channel) argument
1314 npi_txdma_ring_addr_set(npi_handle_t handle, uint8_t channel, uint64_t start_addr, uint32_t len) argument
1360 npi_txdma_ring_config(npi_handle_t handle, io_op_t op_mode, uint8_t channel, uint64_t *reg_data) argument
1418 npi_txdma_mbox_config(npi_handle_t handle, io_op_t op_mode, uint8_t channel, uint64_t *mbox_addr) argument
1657 npi_txdma_desc_kick_reg_set(npi_handle_t handle, uint8_t channel, uint16_t tail_index, boolean_t wrap) argument
1710 npi_txdma_desc_kick_reg_get(npi_handle_t handle, uint8_t channel, p_tx_ring_kick_t kick_p) argument
1750 npi_txdma_ring_head_get(npi_handle_t handle, uint8_t channel, p_tx_ring_hdl_t hdl_p) argument
1771 npi_txdma_channel_mbox_get(npi_handle_t handle, uint8_t channel, p_txdma_mailbox_t mbox_p) argument
1781 npi_txdma_channel_pre_state_get(npi_handle_t handle, uint8_t channel, p_tx_dma_pre_st_t prep) argument
1801 npi_txdma_ring_error_get(npi_handle_t handle, uint8_t channel, p_txdma_ring_errlog_t ring_errlog_p) argument
1979 npi_txdma_inj_int_error_set(npi_handle_t handle, uint8_t channel, p_tdmc_intr_dbg_t erp) argument
2002 npi_txdma_control_reset_wait(npi_handle_t handle, uint8_t channel) argument
2027 npi_txdma_control_stop_wait(npi_handle_t handle, uint8_t channel) argument
2052 npi_txdma_control_resume_wait(npi_handle_t handle, uint8_t channel) argument
[all...]
H A Dnpi_rx_rd32.h48 * channel The channel, which is used as a multiplicand.
58 * The rest of it is pretty straighforward. In a VR, a channel is
65 * offset += ((channel << 1) + 1) << DMA_CSR_SLL;
69 * RXDMA_REG_READ32(handle, RX_DMA_CTL_STAT_REG, channel);
70 * Let's say channel is 3
84 * E00 - FFF CSRs for bound logical receive DMA channel 3.
87 * channel number by 512 bytes, and get the correct offset to
89 * is, as are all of these registers, in a table where each channel
90 * is offset 512 bytes from the previous channel (coun
114 RXDMA_REG_READ32( npi_handle_t handle, uint32_t offset, int channel) argument
[all...]
H A Dnpi_rx_rd64.h44 * #define RXDMA_REG_READ64(handle, reg, channel, data_p) { \
46 * handle.is_vraddr, channel)), (data_p))
106 * #define NXGE_RXDMA_OFFSET(x, v, channel) (x + \
107 * (!v ? DMC_OFFSET(channel) : \
108 * RDMC_PIOVADDR_OFFSET(channel)))
111 * #define DMC_OFFSET(channel) (DMA_CSR_SIZE * channel)
113 * #define TDMC_PIOVADDR_OFFSET(channel) (2 * DMA_CSR_SIZE * channel)
115 * #define RDMC_PIOVADDR_OFFSET(channel) \
222 RXDMA_REG_READ64( npi_handle_t handle, uint64_t offset, int channel, uint64_t *value) argument
[all...]
H A Dnpi_rx_wr64.h44 * #define RXDMA_REG_WRITE64(handle, reg, channel, data) { \
46 * channel)), (data)) \
85 * #define NXGE_RXDMA_OFFSET(x, v, channel) (x + \
86 * (!v ? DMC_OFFSET(channel) : \
87 * RDMC_PIOVADDR_OFFSET(channel)))
90 * #define DMC_OFFSET(channel) (DMA_CSR_SIZE * channel)
92 * #define TDMC_PIOVADDR_OFFSET(channel) (2 * DMA_CSR_SIZE * channel)
94 * #define RDMC_PIOVADDR_OFFSET(channel) \
200 RXDMA_REG_WRITE64( npi_handle_t handle, uint64_t offset, int channel, uint64_t value) argument
[all...]
H A Dnpi_tx_rd64.h48 * channel The channel, which is used as a multiplicand.
54 * #define TXDMA_REG_READ64(handle, reg, channel, val_p) \
56 * (NXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel)), val_p)
65 * The rest of it is pretty straighforward. In a VR, a channel is
72 * offset += ((channel << 1) << DMA_CSR_SLL);
76 * TXDMA_REG_READ64(handle, TX_CS_REG, channel, &value);
77 * Let's say channel is 3
90 * C00 - dFF CSRs for bound logical transmit DMA channel 3.
93 * channel numbe
122 TXDMA_REG_READ64( npi_handle_t handle, uint64_t offset, int channel, uint64_t *value) argument
[all...]
H A Dnpi_tx_wr64.h48 * channel The channel, which is used as a multiplicand.
54 * #define TXDMA_REG_WRITE64(handle, reg, channel, data) \
56 * NXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel), data)
65 * The rest of it is pretty straighforward. In a VR, a channel is
72 * offset += ((channel << 1) << DMA_CSR_SLL);
76 * TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, value);
77 * Let's say channel is 3
90 * C00 - dFF CSRs for bound logical transmit DMA channel 3.
93 * channel numbe
122 TXDMA_REG_WRITE64( npi_handle_t handle, uint64_t offset, int channel, uint64_t value) argument
[all...]
/illumos-gate/usr/src/uts/intel/io/intel_nhm/
H A Dintel_nhm.h76 #define MC_CHANNEL_RANK_PRESENT_RD(cpu, channel) \
77 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 0, 0x7c, 0)
78 #define MC_DOD_RD(cpu, channel, select) \
79 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 1, 0x48 + ((select) * 4), 0)
80 #define MC_SAG_RD(cpu, channel, select) \
81 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 1, 0x80 + ((select) * 4), 0)
82 #define MC_RIR_LIMIT_RD(cpu, channel, select) \
83 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 2, 0x40 + ((select) * 4), 0)
84 #define MC_RIR_WAY_RD(cpu, channel, select) \
85 nhm_pci_getl(SOCKET_BUS(cpu), (channel)
[all...]
H A Dmem_addr.c52 channel_in_interleave(int node, int channel, int rule, int *way_p, argument
65 if (channel > 1)
72 c = 1 << channel;
158 channel_address(int node, int channel, int rule, uint64_t addr) argument
163 channel = 0;
165 (int64_t)sag_ch[node][channel][rule].soffset) << 16) |
167 if (sag_ch[node][channel][rule].remove8) {
170 if (sag_ch[node][channel][rule].remove7) {
173 if (sag_ch[node][channel][rule].remove6) {
177 if (sag_ch[node][channel][rul
189 int channel = -1; local
283 channel_addr_to_dimm(int node, int channel, uint64_t caddr, int *rank_p, uint64_t *rank_addr_p) argument
326 socket_interleave(uint64_t addr, int node, int channel, int rule, int *way_p) argument
402 dimm_to_addr(int node, int channel, int rank, uint64_t rank_addr, uint64_t *rank_base_p, uint64_t *rank_sz_p, uint32_t *socket_interleave_p, uint32_t *channel_interleave_p, uint32_t *rank_interleave_p, uint32_t *socket_way_p, uint32_t *channel_way_p, uint32_t *rank_way_p) argument
640 int channel; local
697 int channel; local
866 set_rank(int socket, int channel, int rule, int way, int rank, uint64_t rank_addr) argument
[all...]
/illumos-gate/usr/src/uts/common/io/nxge/
H A Dnxge_txdma.c91 p_tx_ring_t ring_p, uint16_t channel);
150 int channel)
156 status = nxge_map_txdma(nxge, channel);
160 (void) npi_txdma_dump_tdc_regs(nxge->npi_handle, channel);
164 status = nxge_txdma_hw_start(nxge, channel);
166 (void) nxge_unmap_txdma_channel(nxge, channel);
167 (void) npi_txdma_dump_tdc_regs(nxge->npi_handle, channel);
171 if (!nxge->statsp->tdc_ksp[channel])
172 nxge_setup_tdc_kstats(nxge, channel);
203 nxge_uninit_txdma_channel(p_nxge_t nxgep, int channel) argument
148 nxge_init_txdma_channel( p_nxge_t nxge, int channel) argument
263 nxge_reset_txdma_channel(p_nxge_t nxgep, uint16_t channel, uint64_t reg_data) argument
316 nxge_init_txdma_channel_event_mask(p_nxge_t nxgep, uint16_t channel, p_tx_dma_ent_msk_t mask_p) argument
356 nxge_init_txdma_channel_cntl_stat(p_nxge_t nxgep, uint16_t channel, uint64_t reg_data) argument
405 nxge_enable_txdma_channel(p_nxge_t nxgep, uint16_t channel, p_tx_ring_t tx_desc_p, p_tx_mbox_t mbox_p) argument
1131 uint8_t channel; local
1248 nxge_txdma_channel_disable( nxge_t *nxge, int channel) argument
1368 nxge_txdma_enable_channel(p_nxge_t nxgep, uint16_t channel) argument
1383 nxge_txdma_disable_channel(p_nxge_t nxgep, uint16_t channel) argument
1423 nxge_txdma_stop_inj_err(p_nxge_t nxgep, int channel) argument
1507 nxge_txdma_fix_channel(p_nxge_t nxgep, uint16_t channel) argument
1533 nxge_txdma_fixup_channel(p_nxge_t nxgep, p_tx_ring_t ring_p, uint16_t channel) argument
1594 nxge_txdma_kick_channel(p_nxge_t nxgep, uint16_t channel) argument
1622 nxge_txdma_hw_kick_channel(p_nxge_t nxgep, p_tx_ring_t ring_p, uint16_t channel) argument
1773 nxge_txdma_channel_hung(p_nxge_t nxgep, p_tx_ring_t tx_ring_p, uint16_t channel) argument
1915 nxge_txdma_fix_hung_channel(p_nxge_t nxgep, uint16_t channel) argument
1942 nxge_txdma_fixup_hung_channel(p_nxge_t nxgep, p_tx_ring_t ring_p, uint16_t channel) argument
2091 nxge_txdma_regs_dump(p_nxge_t nxgep, int channel) argument
2170 nxge_tdc_hvio_setup( nxge_t *nxgep, int channel) argument
2213 nxge_map_txdma(p_nxge_t nxgep, int channel) argument
2284 nxge_map_txdma_channel(p_nxge_t nxgep, uint16_t channel, p_nxge_dma_common_t *dma_buf_p, p_tx_ring_t *tx_desc_p, uint32_t num_chunks, p_nxge_dma_common_t *dma_cntl_p, p_tx_mbox_t *tx_mbox_p) argument
2337 nxge_unmap_txdma_channel(p_nxge_t nxgep, uint16_t channel) argument
2528 nxge_map_txdma_channel_buf_ring(p_nxge_t nxgep, uint16_t channel, p_nxge_dma_common_t *dma_buf_p, p_tx_ring_t *tx_desc_p, uint32_t num_chunks) argument
2762 nxge_txdma_hw_start(p_nxge_t nxgep, int channel) argument
2844 nxge_txdma_start_channel(p_nxge_t nxgep, uint16_t channel, p_tx_ring_t tx_ring_p, p_tx_mbox_t tx_mbox_p) argument
2939 nxge_txdma_stop_channel(p_nxge_t nxgep, uint16_t channel) argument
3031 nxge_txdma_get_ring(p_nxge_t nxgep, uint16_t channel) argument
3084 nxge_txdma_get_mbox(p_nxge_t nxgep, uint16_t channel) argument
3162 uint8_t channel; local
3285 nxge_txdma_fatal_err_recover( p_nxge_t nxgep, uint16_t channel, p_tx_ring_t tx_ring_p) argument
[all...]
/illumos-gate/usr/src/cmd/mdb/intel/amd64/qlc/
H A DMakefile37 CPPFLAGS += -I$(SRC)/uts/common/sys/fibre-channel
38 CPPFLAGS += -I$(SRC)/uts/common/sys/fibre-channel/fca/qlc
39 CPPFLAGS += -I$(SRC)/uts/common/sys/fibre-channel/impl
/illumos-gate/usr/src/cmd/mdb/intel/ia32/qlc/
H A DMakefile36 CPPFLAGS += -I$(SRC)/uts/common/sys/fibre-channel
37 CPPFLAGS += -I$(SRC)/uts/common/sys/fibre-channel/fca/qlc
38 CPPFLAGS += -I$(SRC)/uts/common/sys/fibre-channel/impl
/illumos-gate/usr/src/cmd/mdb/sparc/v9/qlc/
H A DMakefile37 CPPFLAGS += -I$(SRC)/uts/common/sys/fibre-channel
38 CPPFLAGS += -I$(SRC)/uts/common/sys/fibre-channel/fca/qlc
39 CPPFLAGS += -I$(SRC)/uts/common/sys/fibre-channel/impl

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