3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * CDDL HEADER START
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * The contents of this file are subject to the terms of the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Common Development and Distribution License (the "License").
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * You may not use this file except in compliance with the License.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * See the License for the specific language governing permissions
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * and limitations under the License.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * When distributing Covered Code, include this CDDL HEADER in each
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * If applicable, add the following below this CDDL HEADER, with the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * fields enclosed by brackets "[]" replaced with your own identifying
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * information: Portions Copyright [yyyy] [name of copyright owner]
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * CDDL HEADER END
cf6ef8948349f8e11c5d4068f50996f8c0e8926dMichael Speer * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Use is subject to license terms.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsuint32_t hxge_reclaim_pending = TXDMA_RECLAIM_PENDING_DEFAULT;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/* Device register access attributes for PIO. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/* Device descriptor access attributes for DMA. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/* Device buffer access attributes for DMA. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic hxge_status_t hxge_map_txdma_channel(p_hxge_t hxgep, uint16_t channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void hxge_unmap_txdma_channel(p_hxge_t hxgep, uint16_t channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic hxge_status_t hxge_map_txdma_channel_buf_ring(p_hxge_t hxgep, uint16_t,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void hxge_unmap_txdma_channel_buf_ring(p_hxge_t hxgep,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void hxge_map_txdma_channel_cfg_ring(p_hxge_t, uint16_t,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void hxge_unmap_txdma_channel_cfg_ring(p_hxge_t hxgep,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic hxge_status_t hxge_txdma_start_channel(p_hxge_t hxgep, uint16_t channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic hxge_status_t hxge_txdma_stop_channel(p_hxge_t hxgep, uint16_t channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic p_tx_ring_t hxge_txdma_get_ring(p_hxge_t hxgep, uint16_t channel);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic hxge_status_t hxge_tx_err_evnts(p_hxge_t hxgep, uint_t index,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic p_tx_mbox_t hxge_txdma_get_mbox(p_hxge_t hxgep, uint16_t channel);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic hxge_status_t hxge_txdma_fatal_err_recover(p_hxge_t hxgep,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic hxge_status_t hxge_tx_port_fatal_err_recover(p_hxge_t hxgep);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_init_txdma_channels"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Reset TDC block from PEU to cleanup any unknown configuration.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * This may be resulted from previous reboot.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_uninit_txdma_channels"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "<== hxge_uinit_txdma_channels"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_setup_dma_common(p_hxge_dma_common_t dest_p, p_hxge_dma_common_t src_p,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_reset_txdma_channel(p_hxge_t hxgep, uint16_t channel, uint64_t reg_data)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, " ==> hxge_reset_txdma_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs rs = hpi_txdma_channel_control(handle, TXDMA_RESET, channel);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Reset the tail (kick) register to 0. (Hardware will not reset it. Tx
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * overflow fatal error if tail is not set to 0 after reset!
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, " <== hxge_reset_txdma_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_init_txdma_channel_event_mask(p_hxge_t hxgep, uint16_t channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_init_txdma_channel_event_mask"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Mask off tx_rng_oflow since it is a false alarm. The driver
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * ensures not over flowing the hardware and check the hardware
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs rs = hpi_txdma_event_mask(handle, OP_SET, channel, mask_p);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_init_txdma_channel_event_mask"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint16_t channel, p_tx_ring_t tx_desc_p, p_tx_mbox_t mbox_p)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_enable_txdma_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Use configuration data composed at init time. Write to hardware the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * transmit ring configurations.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Write to hardware the mailbox */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Start the DMA engine. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "<== hxge_enable_txdma_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_fill_tx_hdr(p_mblk_t mp, boolean_t fill_len, boolean_t l4_cksum,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint8_t hdrs_buf[sizeof (struct ether_header) + 64 + sizeof (uint32_t)];
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((NULL, TX_CTL, "==> hxge_fill_tx_hdr: mp $%p", mp));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Caller should zero out the headers first.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_fill_tx_hdr: pkt_len %d npads %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs hdrp->value |= (tmp << TX_PKT_HEADER_TOT_XFER_LEN_SHIFT);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * mp is the original data packet (does not include the Neptune
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * transmit header).
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_fill_tx_hdr: mp $%p b_rptr $%p len %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs bcopy(nmp->b_rptr, &hdrs_buf[0], sizeof (struct ether_vlan_header));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs eth_type = ntohs(((p_ether_header_t)hdrs_buf)->ether_type);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> : hxge_fill_tx_hdr: (value 0x%llx) ether type 0x%x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_pkt_hdr_init: LLC value 0x%llx", hdrp->value));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_pkt_hdr_init: LLC ether type 0x%x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_pkt_hdr_init: VLAN value 0x%llx",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((NULL, TX_CTL, "==> hxge_fill_tx_hdr: IPv4 "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " iph_len %d l3start %d eth_hdr_size %d proto 0x%x"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_pkt_hdr_init: IP value 0x%llx", hdrp->value));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* byte 6 is the next header protocol */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((NULL, TX_CTL, "==> hxge_fill_tx_hdr: IPv6 "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " iph_len %d l3start %d eth_hdr_size %d proto 0x%x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((NULL, TX_CTL, "==> hxge_tx_pkt_hdr_init: IPv6 "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((NULL, TX_CTL, "==> hxge_fill_tx_hdr: non-IP"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_pkt_hdr_init: TCP CKSUM"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_pkt_hdr_init: TCP value 0x%llx", hdrp->value));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((NULL, TX_CTL, "==> hxge_fill_tx_hdr: UDP"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_pkt_hdr_init: UDP value 0x%llx",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_fill_tx_hdr: pkt_len %d npads %d value 0x%llx",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if ((newmp = allocb(TX_PKT_HEADER_SIZE, BPRI_MED)) == NULL) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_tx_pkt_header_reserve: allocb failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_pkt_header_reserve: get new mp"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==>hxge_tx_pkt_header_reserve: b_rptr $%p b_wptr $%p",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_tx_pkt_header_reserve: use new mp"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_pkt_nmblocks: mp $%p rptr $%p wptr $%p len %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((NULL, TX_CTL, "==> hxge_tx_pkt_nmblocks: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "len %d pkt_len %d nmblks %d tot_xfer_len %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (len <= 0) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_pkt_nmblocks:"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((NULL, TX_CTL, "==> hxge_tx_pkt_nmblocks: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "len %d pkt_len %d nmblks %d tot_xfer_len %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_pkt_nmblocks: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "len %d (< thresh) pkt_len %d nmblks %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_pkt_nmblocks: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "len %d (> thresh) pkt_len %d nmblks %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Hardware limits the transfer length to 4K. If len is
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * more than 4K, we need to break it up to at most 2
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * more blocks.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_pkt_nmblocks: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "len %d pkt_len %d nmblks %d nsegs %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (0);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } while (nsegs);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Hardware limits the transmit gather pointers to 15.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (nmp->b_cont && (nmblks + TX_GATHER_POINTERS_THRESHOLD) >
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_pkt_nmblocks: pull msg - "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "len %d pkt_len %d nmblks %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Pull all message blocks from b_cont */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (0);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_tx_pkt_nmblocks: rptr $%p wptr $%p "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "nmblks %d len %d tot_xfer_len %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mp->b_rptr, mp->b_wptr, nmblks, MBLKL(mp), *tot_xfer_len_p));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_txdma_reclaim(p_hxge_t hxgep, p_tx_ring_t tx_ring_p, int nmblks)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_txdma_reclaim"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs status = ((tx_ring_p->descs_pending < hxge_reclaim_pending) &&
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_reclaim: pending %d reclaim %d nmblks %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs tx_ring_p->descs_pending, hxge_reclaim_pending, nmblks));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs tx_desc_ring_vp = (p_tx_desc_t)DMA_COMMON_VPTR(desc_area);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * tdc_byte_cnt reg can be used to get bytes transmitted. It
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * includes padding too in case of runt packets.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs TXDMA_REG_READ64(handle, TDC_BYTE_CNT, tdc, &byte_cnt.value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_reclaim: tdc %d tx_rd_index %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tail_index %d tail_wrap %d tx_desc_p $%p ($%p) ",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Read the hardware maintained transmit head and wrap around
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs TXDMA_REG_READ64(handle, TDC_TDR_HEAD, tdc, &tx_head.value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_reclaim: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_rd_index %d tail %d tail_wrap %d head %d wrap %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs tx_rd_index, tail_index, tail_wrap, head_index, head_wrap));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * For debug only. This can be used to verify the qlen and make
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * sure the hardware is wrapping the Tdr correctly.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs TXDMA_REG_READ64(handle, TDC_TDR_QLEN, tdc, &qlen.value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_reclaim: tdr_qlen %d tdr_pref_qlen %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_reclaim: EMPTY"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_reclaim: Checking if ring full"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_reclaim: full"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_reclaim: tx_rd_index and head_index"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* XXXX: limit the # of reclaims */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_reclaim: Checking if pending"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_reclaim: descs_pending %d ",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_reclaim: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "(tx_rd_index %d head_index %d (tx_desc_p $%p)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_reclaim: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "(tx_rd_index %d head_index %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_desc_p $%p (desc value 0x%llx) ",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_reclaim: dump desc:"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * tdc_byte_cnt reg can be used to get bytes
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * transmitted
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_reclaim: pkt_len %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tdc channel %d opackets %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_desc_p = $%p tx_desc_pp = $%p "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "index = %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_reclaim: USE DMA"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_dma_unbind_handle "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_reclaim: count packets"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * count a chained packet only once.
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer status = (nmblks <= ((int)tx_ring_p->tx_ring_size -
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer (int)tx_ring_p->descs_pending - TX_FULL_MARK));
75d94465dbafa487b716482dc36d5150a4ec9853Josef 'Jeff' Sipek (void) atomic_cas_32((uint32_t *)&tx_ring_p->queueing,
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer status = (nmblks <= ((int)tx_ring_p->tx_ring_size -
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer (int)tx_ring_p->descs_pending - TX_FULL_MARK));
dc10a9c2a5a49452cc30c6a110b64e5e074e37b3Michael Speer * If the interface is not started, just swallow the interrupt
dc10a9c2a5a49452cc30c6a110b64e5e074e37b3Michael Speer * and don't rearm the logical device.
dc10a9c2a5a49452cc30c6a110b64e5e074e37b3Michael Speer if (hxgep->hxge_mac_state != HXGE_MAC_STARTED)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_intr: hxgep(arg2) $%p ldvp(arg1) $%p", hxgep, ldvp));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * This interrupt handler is for a specific transmit dma channel.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Get the control and status for this channel. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_intr: hxgep $%p ldvp (ldvp) $%p channel %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs rs = hpi_txdma_control_status(handle, OP_GET, channel, &cs);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_intr:channel %d ring index %d status 0x%08x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_intr:channel %d ring index %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_intr:channel %d ring index %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "status 0x%08x (marked bit set, calling reclaim)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Process other transmit control and status. Check the ldv state.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs status = hxge_tx_err_evnts(hxgep, ldvp->vdma_index, ldvp, cs);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Clear the error bits */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Rearm this logical group if this is a single device group.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_tx_intr: rearm"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_mode: not initialized"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_hw_mode: NULL global ring pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_hw_mode: NULL rings pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_hw_mode: no dma channel allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_txdma_hw_mode: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_rings $%p tx_desc_rings $%p ndmas %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_hw_mode: channel %d (enable) "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Stop the dma channel and waits for the stop done. If
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * the stop done bit is not set, then force an error so
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * TXC will stop. All channels bound to this port need
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * to be stopped and reset after injecting an interrupt
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_hw_mode: channel %d (disable) "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs status = ((rs == HPI_SUCCESS) ? HXGE_OK : HXGE_ERROR | rs);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_txdma_enable_channel(p_hxge_t hxgep, uint16_t channel)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* enable the transmit dma channels */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_txdma_enable_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_txdma_disable_channel(p_hxge_t hxgep, uint16_t channel)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* stop the transmit dma channels */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_txdma_disable_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_txdma_stop_inj_err"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Stop the dma channel waits for the stop done. If the stop done bit
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * is not set, then create an error.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs status = ((rs == HPI_SUCCESS) ? HXGE_OK : HXGE_ERROR | rs);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_stop_inj_err (channel %d): "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_stop_inj_err (channel): stop failed (0x%x) "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " (injected error but still not stopped)", channel, rs));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_txdma_stop_inj_err"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_fixup_txdma_rings"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * For each transmit channel, reclaim each descriptor and free buffers.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_fixup_txdma_rings: NULL ring pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_fixup_txdma_rings: no channel allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_fixup_txdma_rings: NULL rings pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_fixup_txdma_rings: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_rings $%p tx_desc_rings $%p ndmas %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_fixup_txdma_rings"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_txdma_fix_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_txdma_fix_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_fix_channel: channel not matched "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_txdma_fix_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_txdma_fixup_channel(p_hxge_t hxgep, p_tx_ring_t ring_p, uint16_t channel)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_txdma_fixup_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_fixup_channel: NULL ring pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_fixup_channel: channel not matched "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_txdma_fixup_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_txdma_hw_kick"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_hw_kick: NULL ring pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_hw_kick: no channel allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_hw_kick: NULL rings pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_txdma_hw_kick: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_rings $%p tx_desc_rings $%p ndmas %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs hxge_txdma_hw_kick_channel(hxgep, tx_rings->rings[index],
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_txdma_hw_kick"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_txdma_kick_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, " hxge_txdma_kick_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_kick_channel: channel not matched "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_txdma_kick_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_txdma_hw_kick_channel(p_hxge_t hxgep, p_tx_ring_t ring_p, uint16_t channel)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_txdma_hw_kick_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_hw_kick_channel: NULL ring pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_txdma_hw_kick_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_check_tx_hang"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Needs inputs from hardware for regs: head index had not moved since
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * last timeout. packets not transmitted or stuffed registers.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_check_tx_hang"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_hung: NULL ring pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_hung: no channel allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_hung: NULL rings pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (hxge_txdma_channel_hung(hxgep, tx_ring_p, channel)) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_txdma_channel_hung(p_hxge_t hxgep, p_tx_ring_t tx_ring_p, uint16_t channel)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_txdma_channel_hung"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_channel_hung: tdc %d tx_rd_index %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tail_index %d tail_wrap %d ",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Read the hardware maintained transmit head and wrap around bit.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (void) hpi_txdma_ring_head_get(handle, channel, &tx_head);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_txdma_channel_hung: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_rd_index %d tail %d tail_wrap %d head %d wrap %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs tx_rd_index, tail_index, tail_wrap, head_index, head_wrap));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (TXDMA_RING_EMPTY(head_index, head_wrap, tail_index, tail_wrap) &&
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_channel_hung: EMPTY"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_channel_hung: Checking if ring full"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (TXDMA_RING_FULL(head_index, head_wrap, tail_index, tail_wrap)) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_channel_hung: full"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* If not full, check with hardware to see if it is hung */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_txdma_channel_hung"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_fixup_hung_txdma_rings"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_fixup_hung_txdma_rings: NULL ring pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_fixup_hung_txdma_rings: no channel allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_fixup_hung_txdma_rings: NULL rings pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_fixup_hung_txdma_rings: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_rings $%p tx_desc_rings $%p ndmas %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_fixup_hung_txdma_rings: channel %d", channel));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs hxge_txdma_fixup_hung_channel(hxgep, tx_rings->rings[index],
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_fixup_hung_txdma_rings"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_txdma_fix_hung_channel(p_hxge_t hxgep, uint16_t channel)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_txdma_fix_hung_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_fix_hung_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_fix_hung_channel: channel not matched "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_txdma_fix_hung_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_txdma_fixup_hung_channel(p_hxge_t hxgep, p_tx_ring_t ring_p,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_txdma_fixup_hung_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_fixup_hung_channel: NULL ring pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_fixup_hung_channel: channel "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "not matched ring tdc %d passed channel",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Reclaim descriptors */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Stop the dma channel waits for the stop done. If the stop done bit
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * is not set, then force an error.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_fixup_hung_channel: stopped OK "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Stop done bit will be set as a result of error injection */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_fixup_hung_channel: stopped again"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_fixup_hung_channel: stop done still not set!! "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_txdma_fixup_hung_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_reclaim_ring"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_reclain_rimgs: NULL ring pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_reclain_rimgs: no channel allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_reclain_rimgs: NULL rings pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_reclain_rimgs: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_rings $%p tx_desc_rings $%p ndmas %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> reclain_rimgs: channel %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_reclaim_rings"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Static functions start here.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_map_txdma: buf not allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_map_txdma: no dma allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs tx_rings = (p_tx_rings_t)KMEM_ZALLOC(sizeof (tx_rings_t), KM_SLEEP);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_rings $%p tx_desc_rings $%p", tx_rings, tx_desc_rings));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Map descriptors from the buffer pools for each dma channel.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Set up and prepare buffer blocks, descriptors and mailbox.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs tx_desc_rings[i]->tdc_stats = &hxgep->statsp->tdc_stats[i];
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_rings $%p rings $%p", hxgep->tx_rings, hxgep->tx_rings->rings));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_rings $%p tx_desc_rings $%p",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_map_txdma: uninit tx desc "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "(status 0x%x channel %d i %d)", hxgep, status, channel, i));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (; i >= 0; i--) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs hxge_unmap_txdma_channel(hxgep, channel, tx_desc_rings[i],
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_map_txdma: (status 0x%x channel %d)", status, channel));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_unmap_txdma"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_unmap_txdma: buf not allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_unmap_txdma: no dma allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_unmap_txdma: NULL ring pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_unmap_txdma: NULL ring pointers"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_unmap_txdma: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_rings $%p tx_desc_rings $%p ndmas %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "<== hxge_unmap_txdma"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Set up and prepare buffer blocks, descriptors and mailbox.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Transmit buffer blocks
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_map_txdma_channel (channel %d): "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Transmit block ring, and mailbox.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs hxge_map_txdma_channel_cfg_ring(hxgep, channel, dma_cntl_p, *tx_desc_p,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_map_txdma_channel: unmap buf"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_map_txdma_channel: (status 0x%x channel %d)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_unmap_txdma_channel(p_hxge_t hxgep, uint16_t channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* unmap tx block ring, and mailbox. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (void) hxge_unmap_txdma_channel_cfg_ring(hxgep, tx_ring_p, tx_mbox_p);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* unmap buffer blocks */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (void) hxge_unmap_txdma_channel_buf_ring(hxgep, tx_ring_p);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "<== hxge_unmap_txdma_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_map_txdma_channel_cfg_ring(p_hxge_t hxgep, uint16_t dma_channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_map_txdma_channel_cfg_ring"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs hxge_setup_dma_common(dmap, cntl_dmap, tx_ring_p->tx_ring_size,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Zero out transmit ring descriptors.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_map_txdma_channel_cfg_ring: channel %d des $%p",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Hydra len is 11 bits and the lower 5 bits are 0s */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (dmap->dma_cookie.dmac_laddress & TDC_TDR_CFG_ADDR_MASK) |
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_map_txdma_channel_cfg_ring: channel %d cfg 0x%llx",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Map in mailbox */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mboxp = (p_tx_mbox_t)KMEM_ZALLOC(sizeof (tx_mbox_t), KM_SLEEP);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs hxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (txdma_mailbox_t));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_map_txdma_channel_cfg_ring: mbox 0x%lx",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mboxh_p->bits.mbaddr = ((dmap->dma_cookie.dmac_laddress >>
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mboxl_p->bits.mbaddr = ((dmap->dma_cookie.dmac_laddress &
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_map_txdma_channel_cfg_ring: mbox 0x%lx",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_map_txdma_channel_cfg_ring: hmbox $%p mbox $%p",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Set page valid and no mask
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_map_txdma_channel_cfg_ring"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_unmap_txdma_channel_cfg_ring: channel %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_unmap_txdma_channel_cfg_ring"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_map_txdma_channel_buf_ring(p_hxge_t hxgep, uint16_t channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_map_txdma_channel_buf_ring"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hxge_map_txdma_channel_buf_ring: channel %d to map %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_map_txdma_channel_buf_ring: channel %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "bufp $%p nblocks %d nmsgs %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_map_txdma_channel_buf_ring: channel %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs tx_ring_p = (p_tx_ring_t)KMEM_ZALLOC(sizeof (tx_ring_t), KM_SLEEP);
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer (void) snprintf(qname, TASKQ_NAMELEN, "hxge_%d_%d",
1ed830817782694e7259ee818a2f8eee72233f1eMichael Speer tx_ring_p->taskq = ddi_taskq_create(hxgep->dip, qname, 1,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Allocate transmit message rings and handles for packets not to be
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * copied to premapped buffers.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < nmsgs; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ddi_status = ddi_dma_alloc_handle(hxgep->dip, &hxge_tx_dma_attr,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (i < nmsgs) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "Allocate handles failed."));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_map_txdma_channel_buf_ring: channel %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "actual tx desc max %d nmsgs %d (config hxge_tx_ring_size %d)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs channel, tx_ring_p->tx_ring_size, nmsgs, hxge_tx_ring_size));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Map in buffers from the buffer pool.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_map_txdma_channel_buf_ring: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "dma_bufp $%p tx_rng_p $%p tx_msg_rng_p $%p bsize %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_map_txdma_channel_buf_ring: dma chunk %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "size %d dma_bufp $%p",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (j = 0; j < nblocks; j++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_map_txdma_channel_buf_ring: j %d"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_map_txdma_channel_buf_ring status 0x%x", status));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_unmap_txdma_channel_buf_ring(p_hxge_t hxgep, p_tx_ring_t tx_ring_p)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_unmap_txdma_channel_buf_ring"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_unmap_txdma_channel_buf_ring: NULL ringp"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_unmap_txdma_channel_buf_ring: channel %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_dma_unbind_handle failed.");
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs KMEM_FREE(tx_msg_ring, sizeof (tx_msg_t) * tx_ring_p->tx_ring_size);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_unmap_txdma_channel_buf_ring"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_txdma_hw_start"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Initialize REORD Table 1. Disable VMAC 2. Reset the FIFO Err Stat.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 3. Scrub memory and check for errors.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Clear the error status
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_REG_WR64(hxgep->hpi_handle, TDC_FIFO_ERR_STAT, 0x7);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Scrub the rtab memory for the TDC and reset the TDC.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_REG_WR64(hxgep->hpi_handle, TDC_REORD_TBL_DATA_HI, 0x0ULL);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_REG_WR64(hxgep->hpi_handle, TDC_REORD_TBL_DATA_LO, 0x0ULL);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < 256; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Write the command register with an indirect read instruction
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_REG_WR64(hxgep->hpi_handle, TDC_REORD_TBL_CMD, tmp);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Wait for status done
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < 256; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Write the command register with an indirect read instruction
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_REG_WR64(hxgep->hpi_handle, TDC_REORD_TBL_CMD, tmp);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Wait for status done
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_REG_RD64(hxgep->hpi_handle, TDC_REORD_TBL_DATA_HI, &tmp);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "unexpected data (hi), entry: %x, value: 0x%0llx\n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs i, (unsigned long long)tmp));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_REG_RD64(hxgep->hpi_handle, TDC_REORD_TBL_DATA_LO, &tmp);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (tmp != 0) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "unexpected data (lo), entry: %x\n", i));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_REG_RD64(hxgep->hpi_handle, TDC_FIFO_ERR_STAT, &tmp);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (tmp != 0) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "parity error, entry: %x, val 0x%llx\n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs i, (unsigned long long)tmp));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_REG_RD64(hxgep->hpi_handle, TDC_FIFO_ERR_STAT, &tmp);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (tmp != 0) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "parity error, entry: %x\n", i));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Reset FIFO Error Status for the TDC and enable FIFO error events.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_REG_WR64(hxgep->hpi_handle, TDC_FIFO_ERR_STAT, 0x7);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_REG_WR64(hxgep->hpi_handle, TDC_FIFO_ERR_MASK, 0x0);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Initialize the Transmit DMAs.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_hw_start: NULL ring pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_hw_start: NULL ring pointers"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_hw_start: no dma channel allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_txdma_hw_start: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_rings $%p tx_desc_rings $%p ndmas %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Init the DMAs.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_hw_start: tx_rings $%p rings $%p",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_hw_start: tx_rings $%p tx_desc_rings $%p",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_hw_start: disable (status 0x%x channel %d i %d)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (; i >= 0; i--) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_txdma_hw_stop"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_hw_stop: NULL ring pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_hw_stop: NULL ring pointers"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_hw_stop: no dma channel allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_txdma_hw_stop: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_rings $%p tx_desc_rings $%p", tx_rings, tx_desc_rings));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_txdma_hw_stop: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_rings $%p tx_desc_rings $%p", tx_rings, tx_desc_rings));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "<== hxge_txdma_hw_stop"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_txdma_start_channel(p_hxge_t hxgep, uint16_t channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * TXDMA/TXC must be in stopped state.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Reset TXDMA channel
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_start_channel (channel %d)"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Initialize the TXDMA channel specific FZC control configurations.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * These FZC registers are pertaining to each TX channel (i.e. logical
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Initialize the event masks.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Load TXDMA descriptors, buffers, mailbox, initialise the DMA
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * channels and enable each DMA channel.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "<== hxge_txdma_start_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Stop (disable) TXDMA and TXC (if stop bit is set and STOP_N_GO bit
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * not set, the TXDMA reset state will not be set if reset TXDMA.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Reset TXDMA channel
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "<== hxge_txdma_stop_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_txdma_get_ring"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_get_ring: NULL ring pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_get_ring: no channel allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_get_ring: NULL rings pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_txdma_get_ring: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_rings $%p tx_desc_rings $%p ndmas %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_get_ring: tdc %d ring $%p",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_txdma_get_ring"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_txdma_get_mbox"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_get_mbox: NULL ring pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_get_mbox: NULL mbox pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_get_mbox: no channel allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_get_mbox: NULL rings pointer"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_txdma_get_mbox: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "tx_rings $%p tx_desc_rings $%p ndmas %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_txdma_get_mbox: tdc %d ring $%p",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_txdma_get_mbox"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_tx_err_evnts(p_hxge_t hxgep, uint_t index, p_hxge_ldv_t ldvp,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_ERR_CTL, "==> hxge_tx_err_evnts"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Get the error counts if any */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs TXDMA_REG_READ64(handle, TDC_DROP_CNT, channel, &drop_cnt.value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs tdc_stats->count_hdr_size_err += drop_cnt.bits.hdr_size_error_count;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_err_evnts(channel %d): "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_err_evnts(channel %d): "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_err_evnts(channel %d): "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_err_evnts(channel %d): "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_err_evnts(channel %d): "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Get the address of parity error read data */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_err_evnts(channel %d): "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_err_evnts(channel %d): "
fd9489cef0e9b7d8a708339e560d453f230af2cfQiyan Sun - Sun Microsystems - San Diego United States "fatal error: tdr_pref_cpl_to", channel));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_err_evnts(channel %d): "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_err_evnts(channel %d): "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_err_evnts(channel %d): "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Clear error injection source in case this is an injected error */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs TXDMA_REG_WRITE64(hxgep->hpi_handle, TDC_STAT_INT_DBG, channel, 0);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hxge_tx_err_evnts: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " fatal error on channel %d cs 0x%llx\n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_ERR_CTL, "<== hxge_tx_err_evnts"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_txdma_handle_sys_errors"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * The FIFO is shared by all channels.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Get the status of Reorder Buffer and Reorder Table Buffer Errors
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_REG_RD64(handle, TDC_FIFO_ERR_STAT, &fifo_stat.value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Clear the error bits. Note that writing a 1 clears the bit. Writing
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * a 0 does nothing.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_REG_WR64(handle, TDC_FIFO_ERR_STAT, fifo_stat.value);
3a109ad9413b360a5bfa6fa5ddfacef5fd64fe5bQiyan Sun - Sun Microsystems - San Diego United States HXGE_FM_REPORT_ERROR(hxgep, NULL,
3a109ad9413b360a5bfa6fa5ddfacef5fd64fe5bQiyan Sun - Sun Microsystems - San Diego United States HXGE_FM_EREPORT_TDMC_REORD_TBL_PAR);
3a109ad9413b360a5bfa6fa5ddfacef5fd64fe5bQiyan Sun - Sun Microsystems - San Diego United States HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3a109ad9413b360a5bfa6fa5ddfacef5fd64fe5bQiyan Sun - Sun Microsystems - San Diego United States "==> hxge_txdma_handle_sys_errors: fatal error: "
3a109ad9413b360a5bfa6fa5ddfacef5fd64fe5bQiyan Sun - Sun Microsystems - San Diego United States "reord_tbl_par_err"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_handle_sys_errors: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "fatal error: reord_buf_ded_err"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_handle_sys_errors: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "reord_buf_sec_err"));
3a109ad9413b360a5bfa6fa5ddfacef5fd64fe5bQiyan Sun - Sun Microsystems - San Diego United States if (fifo_stat.bits.reord_tbl_par_err ||
3a109ad9413b360a5bfa6fa5ddfacef5fd64fe5bQiyan Sun - Sun Microsystems - San Diego United States fifo_stat.bits.reord_buf_ded_err) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_txdma_handle_sys_errors"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_txdma_fatal_err_recover(p_hxge_t hxgep, uint16_t channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_ERR_CTL, "==> hxge_txdma_fatal_err_recover"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Stop the dma channel waits for the stop done. If the stop done bit
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * is not set, then create an error.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_ERR_CTL, "stopping txdma channel(%d)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs rs = hpi_txdma_channel_control(handle, TXDMA_STOP, channel);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_fatal_err_recover (channel %d): "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_ERR_CTL, "reclaiming txdma channel(%d)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Reset TXDMA channel
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_ERR_CTL, "resetting txdma channel(%d)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if ((rs = hpi_txdma_channel_control(handle, TXDMA_RESET, channel)) !=
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_fatal_err_recover (channel %d)"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Reset the tail (kick) register to 0. (Hardware will not reset it. Tx
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * overflow fatal error if tail is not set to 0 after reset!
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Restart TXDMA channel
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Initialize the TXDMA channel specific FZC control configurations.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * These FZC registers are pertaining to each TX channel (i.e. logical
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_ERR_CTL, "restarting txdma channel(%d)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Initialize the event masks.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs status = hxge_init_txdma_channel_event_mask(hxgep, channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Load TXDMA descriptors, buffers, mailbox, initialise the DMA
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * channels and enable each DMA channel.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_ERR_CTL, "enabling txdma channel(%d)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "Recovery Successful, TxDMAChannel#%d Restored", channel));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_ERR_CTL, "==> hxge_txdma_fatal_err_recover"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_txdma_fatal_err_recover (channel %d): "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovery failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_tx_port_fatal_err_recover"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "Recovering from TxPort error..."));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Reset TDC block from PEU for this fatal error */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Stop the dma channel waits for the stop done. If the stop done bit
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * is not set, then create an error.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_ERR_CTL, "stopping all DMA channels..."));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs rs = hpi_txdma_channel_control(handle, TXDMA_STOP, channel);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_txdma_fatal_err_recover (channel %d): "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Do reclaim on all of th DMAs.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, TX_ERR_CTL, "reclaiming all DMA channels..."));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Restart the TDC */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "Recovery Successful, TxPort Restored"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_tx_port_fatal_err_recover"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovery failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_txdma_fatal_err_recover (channel %d): "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "failed to recover this txdma channel"));