Lines Matching refs:channel
59 static hxge_status_t hxge_map_txdma_channel(p_hxge_t hxgep, uint16_t channel,
63 static void hxge_unmap_txdma_channel(p_hxge_t hxgep, uint16_t channel,
73 static hxge_status_t hxge_txdma_start_channel(p_hxge_t hxgep, uint16_t channel,
75 static hxge_status_t hxge_txdma_stop_channel(p_hxge_t hxgep, uint16_t channel,
77 static p_tx_ring_t hxge_txdma_get_ring(p_hxge_t hxgep, uint16_t channel);
80 static p_tx_mbox_t hxge_txdma_get_mbox(p_hxge_t hxgep, uint16_t channel);
82 uint16_t channel, p_tx_ring_t tx_ring_p);
152 hxge_reset_txdma_channel(p_hxge_t hxgep, uint16_t channel, uint64_t reg_data)
162 rs = hpi_txdma_channel_reset(handle, channel);
164 rs = hpi_txdma_channel_control(handle, TXDMA_RESET, channel);
175 TXDMA_REG_WRITE64(handle, TDC_TDR_KICK, channel, 0);
183 hxge_init_txdma_channel_event_mask(p_hxge_t hxgep, uint16_t channel,
201 rs = hpi_txdma_event_mask(handle, OP_SET, channel, mask_p);
213 uint16_t channel, p_tx_ring_t tx_desc_p, p_tx_mbox_t mbox_p)
226 rs = hpi_txdma_ring_config(handle, OP_SET, channel,
234 rs = hpi_txdma_mbox_config(handle, OP_SET, channel,
242 rs = hpi_txdma_channel_init_enable(handle, channel);
737 "tdc channel %d opackets %d",
809 uint8_t channel;
840 * This interrupt handler is for a specific transmit dma channel.
844 /* Get the control and status for this channel. */
845 channel = ldvp->channel;
848 "==> hxge_tx_intr: hxgep $%p ldvp (ldvp) $%p channel %d",
849 hxgep, ldvp, channel));
851 rs = hpi_txdma_control_status(handle, OP_GET, channel, &cs);
854 "==> hxge_tx_intr:channel %d ring index %d status 0x%08x",
855 channel, vindex, rs));
859 "==> hxge_tx_intr:channel %d ring index %d "
860 "status 0x%08x (marked bit set)", channel, vindex, rs));
864 "==> hxge_tx_intr:channel %d ring index %d "
866 channel, vindex, rs));
880 RXDMA_REG_WRITE64(handle, TDC_STAT, channel, cs.value);
912 uint16_t channel;
942 "<== hxge_txdma_hw_mode: no dma channel allocated"));
954 channel = tx_desc_rings[i]->tdc;
956 "==> hxge_txdma_hw_mode: channel %d", channel));
958 rs = hpi_txdma_channel_enable(handle, channel);
960 "==> hxge_txdma_hw_mode: channel %d (enable) "
961 "rs 0x%x", channel, rs));
964 * Stop the dma channel and waits for the stop done. If
970 rs = hpi_txdma_channel_disable(handle, channel);
972 "==> hxge_txdma_hw_mode: channel %d (disable) "
973 "rs 0x%x", channel, rs));
986 hxge_txdma_enable_channel(p_hxge_t hxgep, uint16_t channel)
991 "==> hxge_txdma_enable_channel: channel %d", channel));
995 (void) hpi_txdma_channel_enable(handle, channel);
1001 hxge_txdma_disable_channel(p_hxge_t hxgep, uint16_t channel)
1006 "==> hxge_txdma_disable_channel: channel %d", channel));
1010 (void) hpi_txdma_channel_disable(handle, channel);
1016 hxge_txdma_stop_inj_err(p_hxge_t hxgep, int channel)
1025 * Stop the dma channel waits for the stop done. If the stop done bit
1029 rs = hpi_txdma_channel_disable(handle, channel);
1033 "<== hxge_txdma_stop_inj_err (channel %d): "
1034 "stopped OK", channel));
1039 "==> hxge_txdma_stop_inj_err (channel): stop failed (0x%x) "
1040 " (injected error but still not stopped)", channel, rs));
1052 uint16_t channel;
1058 * For each transmit channel, reclaim each descriptor and free buffers.
1070 "<== hxge_fixup_txdma_rings: no channel allocated"));
1085 channel = tx_rings->rings[index]->tdc;
1087 "==> hxge_fixup_txdma_rings: channel %d", channel));
1089 channel);
1097 hxge_txdma_fix_channel(p_hxge_t hxgep, uint16_t channel)
1103 ring_p = hxge_txdma_get_ring(hxgep, channel);
1109 if (ring_p->tdc != channel) {
1111 "<== hxge_txdma_fix_channel: channel not matched "
1112 "ring tdc %d passed channel", ring_p->tdc, channel));
1116 hxge_txdma_fixup_channel(hxgep, ring_p, channel);
1123 hxge_txdma_fixup_channel(p_hxge_t hxgep, p_tx_ring_t ring_p, uint16_t channel)
1132 if (ring_p->tdc != channel) {
1134 "<== hxge_txdma_fixup_channel: channel not matched "
1135 "ring tdc %d passed channel", ring_p->tdc, channel));
1156 uint16_t channel;
1170 "<== hxge_txdma_hw_kick: no channel allocated"));
1183 channel = tx_rings->rings[index]->tdc;
1185 "==> hxge_txdma_hw_kick: channel %d", channel));
1187 channel);
1195 hxge_txdma_kick_channel(p_hxge_t hxgep, uint16_t channel)
1201 ring_p = hxge_txdma_get_ring(hxgep, channel);
1207 if (ring_p->tdc != channel) {
1209 "<== hxge_txdma_kick_channel: channel not matched "
1210 "ring tdc %d passed channel", ring_p->tdc, channel));
1214 hxge_txdma_hw_kick_channel(hxgep, ring_p, channel);
1221 hxge_txdma_hw_kick_channel(p_hxge_t hxgep, p_tx_ring_t ring_p, uint16_t channel)
1255 uint16_t channel;
1271 "<== hxge_txdma_hung: no channel allocated"));
1282 channel = tx_rings->rings[index]->tdc;
1285 "==> hxge_txdma_hung: channel %d", channel));
1286 if (hxge_txdma_channel_hung(hxgep, tx_ring_p, channel)) {
1297 hxge_txdma_channel_hung(p_hxge_t hxgep, p_tx_ring_t tx_ring_p, uint16_t channel)
1309 "==> hxge_txdma_channel_hung: channel %d", channel));
1321 channel, tx_rd_index, tail_index, tail_wrap));
1325 (void) hpi_txdma_ring_head_get(handle, channel, &tx_head);
1357 uint16_t channel;
1370 "<== hxge_fixup_hung_txdma_rings: no channel allocated"));
1383 channel = tx_rings->rings[index]->tdc;
1385 "==> hxge_fixup_hung_txdma_rings: channel %d", channel));
1387 channel);
1395 hxge_txdma_fix_hung_channel(p_hxge_t hxgep, uint16_t channel)
1400 ring_p = hxge_txdma_get_ring(hxgep, channel);
1406 if (ring_p->tdc != channel) {
1408 "<== hxge_txdma_fix_hung_channel: channel not matched "
1409 "ring tdc %d passed channel", ring_p->tdc, channel));
1412 hxge_txdma_fixup_channel(hxgep, ring_p, channel);
1420 uint16_t channel)
1432 if (ring_p->tdc != channel) {
1434 "<== hxge_txdma_fixup_hung_channel: channel "
1435 "not matched ring tdc %d passed channel",
1436 ring_p->tdc, channel));
1446 * Stop the dma channel waits for the stop done. If the stop done bit
1449 status = hpi_txdma_channel_disable(handle, channel);
1453 "ring tdc %d passed channel %d", ring_p->tdc, channel));
1457 status = hpi_txdma_channel_disable(handle, channel);
1461 "ring tdc %d passed channel", ring_p->tdc, channel));
1467 "ring tdc %d passed channel", ring_p->tdc, channel));
1476 uint16_t channel;
1490 "<== hxge_reclain_rimgs: no channel allocated"));
1503 channel = tx_rings->rings[index]->tdc;
1504 HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> reclain_rimgs: channel %d",
1505 channel));
1508 (void) hxge_txdma_reclaim(hxgep, tx_ring_p, channel);
1522 uint16_t channel;
1565 * Map descriptors from the buffer pools for each dma channel.
1571 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel;
1572 status = hxge_map_txdma_channel(hxgep, channel,
1602 "(status 0x%x channel %d i %d)", hxgep, status, channel, i));
1605 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel;
1606 hxge_unmap_txdma_channel(hxgep, channel, tx_desc_rings[i],
1617 "==> hxge_map_txdma: (status 0x%x channel %d)", status, channel));
1626 uint8_t channel;
1668 channel = tx_desc_rings[i]->tdc;
1669 (void) hxge_unmap_txdma_channel(hxgep, channel,
1683 hxge_map_txdma_channel(p_hxge_t hxgep, uint16_t channel,
1694 "==> hxge_map_txdma_channel (channel %d)", channel));
1699 status = hxge_map_txdma_channel_buf_ring(hxgep, channel,
1703 "==> hxge_map_txdma_channel (channel %d): "
1704 "map buffer failed 0x%x", channel, status));
1710 hxge_map_txdma_channel_cfg_ring(hxgep, channel, dma_cntl_p, *tx_desc_p,
1718 "(status 0x%x channel %d)", status, channel));
1723 "<== hxge_map_txdma_channel: (status 0x%x channel %d)",
1724 status, channel));
1731 hxge_unmap_txdma_channel(p_hxge_t hxgep, uint16_t channel,
1735 "==> hxge_unmap_txdma_channel (channel %d)", channel));
1786 "==> hxge_map_txdma_channel_cfg_ring: channel %d des $%p",
1798 "==> hxge_map_txdma_channel_cfg_ring: channel %d cfg 0x%llx",
1844 "==> hxge_unmap_txdma_channel_cfg_ring: channel %d",
1854 hxge_map_txdma_channel_buf_ring(p_hxge_t hxgep, uint16_t channel,
1875 " hxge_map_txdma_channel_buf_ring: channel %d to map %d "
1876 "chunks bufp $%p", channel, num_chunks, dma_bufp));
1882 "==> hxge_map_txdma_channel_buf_ring: channel %d "
1884 channel, tmp_bufp, tmp_bufp->nblocks, nmsgs));
1888 "<== hxge_map_txdma_channel_buf_ring: channel %d "
1889 "no msg blocks", channel));
1898 hxgep->instance, channel);
1928 tx_ring_p->tdc = channel;
1943 "==> hxge_map_txdma_channel_buf_ring: channel %d "
1945 channel, tx_ring_p->tx_ring_size, nmsgs, hxge_tx_ring_size));
2028 "==> hxge_unmap_txdma_channel_buf_ring: channel %d",
2082 uint16_t channel;
2204 "<== hxge_txdma_hw_start: no dma channel allocated"));
2218 channel = tx_desc_rings[i]->tdc;
2219 status = hxge_txdma_start_channel(hxgep, channel,
2240 "==> hxge_txdma_hw_start: disable (status 0x%x channel %d i %d)",
2241 status, channel, i));
2244 channel = tx_desc_rings[i]->tdc,
2245 (void) hxge_txdma_stop_channel(hxgep, channel,
2261 uint16_t channel;
2286 "<== hxge_txdma_hw_stop: no dma channel allocated"));
2297 channel = tx_desc_rings[i]->tdc;
2298 (void) hxge_txdma_stop_channel(hxgep, channel,
2309 hxge_txdma_start_channel(p_hxge_t hxgep, uint16_t channel,
2315 "==> hxge_txdma_start_channel (channel %d)", channel));
2319 (void) hxge_txdma_stop_inj_err(hxgep, channel);
2322 * Reset TXDMA channel
2326 status = hxge_reset_txdma_channel(hxgep, channel,
2330 "==> hxge_txdma_start_channel (channel %d)"
2331 " reset channel failed 0x%x", channel, status));
2337 * Initialize the TXDMA channel specific FZC control configurations.
2338 * These FZC registers are pertaining to each TX channel (i.e. logical
2341 status = hxge_init_fzc_txdma_channel(hxgep, channel,
2352 channel, &tx_ring_p->tx_evmask);
2359 * channels and enable each DMA channel.
2361 status = hxge_enable_txdma_channel(hxgep, channel,
2375 hxge_txdma_stop_channel(p_hxge_t hxgep, uint16_t channel,
2381 "==> hxge_txdma_stop_channel: channel %d", channel));
2387 (void) hxge_txdma_stop_inj_err(hxgep, channel);
2390 * Reset TXDMA channel
2394 status = hxge_reset_txdma_channel(hxgep, channel,
2407 hxge_txdma_get_ring(p_hxge_t hxgep, uint16_t channel)
2424 "<== hxge_txdma_get_ring: no channel allocated"));
2439 "==> hxge_fixup_txdma_rings: channel %d", tdc));
2440 if (channel == tdc) {
2454 hxge_txdma_get_mbox(p_hxge_t hxgep, uint16_t channel)
2480 "<== hxge_txdma_get_mbox: no channel allocated"));
2495 "==> hxge_txdma_get_mbox: channel %d", tdc));
2496 if (channel == tdc) {
2515 uint8_t channel;
2525 channel = ldvp->channel;
2532 TXDMA_REG_READ64(handle, TDC_DROP_CNT, channel, &drop_cnt.value);
2539 HXGE_FM_REPORT_ERROR(hxgep, channel,
2542 "==> hxge_tx_err_evnts(channel %d): "
2543 "fatal error: peu_resp_err", channel));
2549 HXGE_FM_REPORT_ERROR(hxgep, channel,
2552 "==> hxge_tx_err_evnts(channel %d): "
2553 "fatal error: pkt_size_hdr_err", channel));
2559 HXGE_FM_REPORT_ERROR(hxgep, channel,
2562 "==> hxge_tx_err_evnts(channel %d): "
2563 "fatal error: runt_pkt_drop_err", channel));
2569 HXGE_FM_REPORT_ERROR(hxgep, channel,
2572 "==> hxge_tx_err_evnts(channel %d): "
2573 "fatal error: pkt_size_err", channel));
2581 "==> hxge_tx_err_evnts(channel %d): "
2582 "fatal error: tx_rng_oflow", channel));
2590 channel, &tdc_stats->errlog.value);
2592 HXGE_FM_REPORT_ERROR(hxgep, channel,
2595 "==> hxge_tx_err_evnts(channel %d): "
2596 "fatal error: pref_par_err", channel));
2602 HXGE_FM_REPORT_ERROR(hxgep, channel,
2605 "==> hxge_tx_err_evnts(channel %d): "
2606 "fatal error: tdr_pref_cpl_to", channel));
2612 HXGE_FM_REPORT_ERROR(hxgep, channel,
2615 "==> hxge_tx_err_evnts(channel %d): "
2616 "fatal error: pkt_cpl_to", channel));
2622 HXGE_FM_REPORT_ERROR(hxgep, channel,
2625 "==> hxge_tx_err_evnts(channel %d): "
2626 "fatal error: invalid_sop", channel));
2632 HXGE_FM_REPORT_ERROR(hxgep, channel,
2635 "==> hxge_tx_err_evnts(channel %d): "
2636 "fatal error: unexpected_sop", channel));
2641 TXDMA_REG_WRITE64(hxgep->hpi_handle, TDC_STAT_INT_DBG, channel, 0);
2646 " fatal error on channel %d cs 0x%llx\n",
2647 channel, cs.value));
2648 status = hxge_txdma_fatal_err_recover(hxgep, channel,
2725 hxge_txdma_fatal_err_recover(p_hxge_t hxgep, uint16_t channel,
2735 "Recovering from TxDMAChannel#%d error...", channel));
2738 * Stop the dma channel waits for the stop done. If the stop done bit
2742 HXGE_DEBUG_MSG((hxgep, TX_ERR_CTL, "stopping txdma channel(%d)",
2743 channel));
2745 rs = hpi_txdma_channel_control(handle, TXDMA_STOP, channel);
2748 "==> hxge_txdma_fatal_err_recover (channel %d): "
2749 "stop failed ", channel));
2753 HXGE_DEBUG_MSG((hxgep, TX_ERR_CTL, "reclaiming txdma channel(%d)",
2754 channel));
2758 * Reset TXDMA channel
2760 HXGE_DEBUG_MSG((hxgep, TX_ERR_CTL, "resetting txdma channel(%d)",
2761 channel));
2762 if ((rs = hpi_txdma_channel_control(handle, TXDMA_RESET, channel)) !=
2765 "==> hxge_txdma_fatal_err_recover (channel %d)"
2766 " reset channel failed 0x%x", channel, rs));
2774 TXDMA_REG_WRITE64(handle, TDC_TDR_KICK, channel, 0);
2777 * Restart TXDMA channel
2779 * Initialize the TXDMA channel specific FZC control configurations.
2780 * These FZC registers are pertaining to each TX channel (i.e. logical
2783 tx_mbox_p = hxge_txdma_get_mbox(hxgep, channel);
2784 HXGE_DEBUG_MSG((hxgep, TX_ERR_CTL, "restarting txdma channel(%d)",
2785 channel));
2786 status = hxge_init_fzc_txdma_channel(hxgep, channel,
2795 status = hxge_init_txdma_channel_event_mask(hxgep, channel,
2806 * channels and enable each DMA channel.
2808 HXGE_DEBUG_MSG((hxgep, TX_ERR_CTL, "enabling txdma channel(%d)",
2809 channel));
2810 status = hxge_enable_txdma_channel(hxgep, channel,
2817 "Recovery Successful, TxDMAChannel#%d Restored", channel));
2825 "hxge_txdma_fatal_err_recover (channel %d): "
2826 "failed to recover this txdma channel", channel));
2842 uint16_t channel;
2860 * Stop the dma channel waits for the stop done. If the stop done bit
2881 channel = tx_desc_rings[i]->tdc;
2883 rs = hpi_txdma_channel_control(handle, TXDMA_STOP, channel);
2886 "==> hxge_txdma_fatal_err_recover (channel %d): "
2887 "stop failed ", channel));
2934 "hxge_txdma_fatal_err_recover (channel %d): "
2935 "failed to recover this txdma channel"));