Cross Reference: /illumos-gate/usr/src/uts/common/io/hxge/hpi

Lines Matching refs:channel
35     uint8_t channel);
38 hpi_txdma_log_page_handle_set(hpi_handle_t handle, uint8_t channel,
43 	if (!TXDMA_CHANNEL_VALID(channel)) {
46 		    " Invalid Input: channel <0x%x>", channel));
47 		return (HPI_FAILURE | HPI_TXDMA_CHANNEL_INVALID(channel));
50 	TXDMA_REG_WRITE64(handle, TDC_PAGE_HANDLE, channel, hdl_p->value);
56 hpi_txdma_channel_reset(hpi_handle_t handle, uint8_t channel)
59 	    " hpi_txdma_channel_reset" " RESETTING", channel));
60 	return (hpi_txdma_channel_control(handle, TXDMA_RESET, channel));
64 hpi_txdma_channel_init_enable(hpi_handle_t handle, uint8_t channel)
66 	return (hpi_txdma_channel_control(handle, TXDMA_INIT_START, channel));
70 hpi_txdma_channel_enable(hpi_handle_t handle, uint8_t channel)
72 	return (hpi_txdma_channel_control(handle, TXDMA_START, channel));
76 hpi_txdma_channel_disable(hpi_handle_t handle, uint8_t channel)
78 	return (hpi_txdma_channel_control(handle, TXDMA_STOP, channel));
82 hpi_txdma_channel_mbox_enable(hpi_handle_t handle, uint8_t channel)
84 	return (hpi_txdma_channel_control(handle, TXDMA_MBOX_ENABLE, channel));
89     uint8_t channel)
95 	if (!TXDMA_CHANNEL_VALID(channel)) {
98 		    " Invalid Input: channel <0x%x>", channel));
99 		return (HPI_FAILURE | HPI_TXDMA_CHANNEL_INVALID(channel));
105 		TXDMA_REG_READ64(handle, TDC_TDR_CFG, channel, &cfg.value);
107 		TXDMA_REG_WRITE64(handle, TDC_TDR_CFG, channel, cfg.value);
108 		return (hpi_txdma_control_reset_wait(handle, channel));
112 		TXDMA_REG_READ64(handle, TDC_TDR_CFG, channel, &cfg.value);
114 		TXDMA_REG_WRITE64(handle, TDC_TDR_CFG, channel, cfg.value);
124 		TXDMA_REG_WRITE64(handle, TDC_TDR_CFG, channel, cfg.value);
125 		return (hpi_txdma_control_reset_wait(handle, channel));
128 		/* Enable the DMA channel */
129 		TXDMA_REG_READ64(handle, TDC_TDR_CFG, channel, &cfg.value);
131 		TXDMA_REG_WRITE64(handle, TDC_TDR_CFG, channel, cfg.value);
135 		/* Disable the DMA channel */
136 		TXDMA_REG_READ64(handle, TDC_TDR_CFG, channel, &cfg.value);
138 		TXDMA_REG_WRITE64(handle, TDC_TDR_CFG, channel, cfg.value);
139 		status = hpi_txdma_control_stop_wait(handle, channel);
142 			    "Cannot stop channel %d (TXC hung!)", channel));
151 		TXDMA_REG_READ64(handle, TDC_STAT, channel, &cs.value);
153 		TXDMA_REG_WRITE64(handle, TDC_STAT, channel, cs.value);
157 		status = (HPI_FAILURE | HPI_TXDMA_OPCODE_INVALID(channel));
167 hpi_txdma_control_status(hpi_handle_t handle, io_op_t op_mode, uint8_t channel,
173 	if (!TXDMA_CHANNEL_VALID(channel)) {
176 		    " Invalid Input: channel <0x%x>", channel));
177 		return (HPI_FAILURE | HPI_TXDMA_CHANNEL_INVALID(channel));
181 		TXDMA_REG_READ64(handle, TDC_STAT, channel, &cs_p->value);
185 		TXDMA_REG_WRITE64(handle, TDC_STAT, channel, cs_p->value);
189 		TXDMA_REG_READ64(handle, TDC_STAT, channel, &txcs.value);
190 		TXDMA_REG_WRITE64(handle, TDC_STAT, channel,
198 		return (HPI_FAILURE | HPI_TXDMA_OPCODE_INVALID(channel));
205 hpi_txdma_event_mask(hpi_handle_t handle, io_op_t op_mode, uint8_t channel,
211 	if (!TXDMA_CHANNEL_VALID(channel)) {
213 		    " hpi_txdma_event_mask Invalid Input: channel <0x%x>",
214 		    channel));
215 		return (HPI_FAILURE | HPI_TXDMA_CHANNEL_INVALID(channel));
219 		TXDMA_REG_READ64(handle, TDC_INT_MASK, channel, &mask_p->value);
223 		TXDMA_REG_WRITE64(handle, TDC_INT_MASK, channel, mask_p->value);
227 		TXDMA_REG_READ64(handle, TDC_INT_MASK, channel, &mask.value);
228 		TXDMA_REG_WRITE64(handle, TDC_INT_MASK, channel,
236 		return (HPI_FAILURE | HPI_TXDMA_OPCODE_INVALID(channel));
244     uint8_t channel, uint64_t *reg_data)
248 	if (!TXDMA_CHANNEL_VALID(channel)) {
251 		    " Invalid Input: channel <0x%x>", channel));
252 		return (HPI_FAILURE | HPI_TXDMA_CHANNEL_INVALID(channel));
256 		TXDMA_REG_READ64(handle, TDC_TDR_CFG, channel, reg_data);
260 		TXDMA_REG_WRITE64(handle, TDC_TDR_CFG, channel, *reg_data);
267 		return (HPI_FAILURE | HPI_TXDMA_OPCODE_INVALID(channel));
275     uint8_t channel, uint64_t *mbox_addr)
281 	if (!TXDMA_CHANNEL_VALID(channel)) {
283 		    " hpi_txdma_mbox_config Invalid Input: channel <0x%x>",
284 		    channel));
285 		return (HPI_FAILURE | HPI_TXDMA_CHANNEL_INVALID(channel));
292 		TXDMA_REG_READ64(handle, TDC_MBH, channel, &mh.value);
293 		TXDMA_REG_READ64(handle, TDC_MBL, channel, &ml.value);
301 		TXDMA_REG_WRITE64(handle, TDC_MBL, channel, ml.value);
304 		TXDMA_REG_WRITE64(handle, TDC_MBH, channel, mh.value);
311 		return (HPI_FAILURE | HPI_TXDMA_OPCODE_INVALID(channel));
383 hpi_txdma_ring_head_get(hpi_handle_t handle, uint8_t channel,
388 	if (!TXDMA_CHANNEL_VALID(channel)) {
391 		    " Invalid Input: channel <0x%x>", channel));
392 		return (HPI_FAILURE | HPI_TXDMA_CHANNEL_INVALID(channel));
394 	TXDMA_REG_READ64(handle, TDC_TDR_HEAD, channel, &hdl_p->value);
437 hpi_txdma_control_reset_wait(hpi_handle_t handle, uint8_t channel)
445 		TXDMA_REG_READ64(handle, TDC_TDR_CFG, channel, &txcs.value);
466 hpi_txdma_control_stop_wait(hpi_handle_t handle, uint8_t channel)
474 		TXDMA_REG_READ64(handle, TDC_TDR_CFG, channel, &txcs.value);