io/intel_nhm/intel_nhm.h

84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/*
9384cec630155c229c70dfb8a445c6ccf433045aJohann 'Myrkraverk' Oskarsson * CDDL HEADER START
d15978eab6c23a98f0a5474466d5fe9b1be3ca9bGary Mills *
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov * The contents of this file are subject to the terms of the
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * Common Development and Distribution License (the "License").
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * You may not use this file except in compliance with the License.
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore *
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * or http://www.opensolaris.org/os/licensing.
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * See the License for the specific language governing permissions
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * and limitations under the License.
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84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * When distributing Covered Code, include this CDDL HEADER in each
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * CDDL HEADER END
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/*
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * Use is subject to license terms.
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#ifndef _INTEL_NHM_H
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define _INTEL_NHM_H
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#ifdef __cplusplus
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amoreextern "C" {
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#endif
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define NHM_EP_CPU  0x2c408086
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define NHM_WS_CPU  0x2c418086
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define NHM_CPU_RAS 0x2c1a8086
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define NHM_JF_CPU  0x2c588086
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define NHM_JF_CPU_RAS  0x2cda8086
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define NHM_WM_CPU  0x2c708086
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define NHM_WM_CPU_RAS  0x2d9a8086
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define NHM_INTERCONNECT    "Intel QuickPath"
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MAX_CPU_NODES   2
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov#define CPU_PCI_DEVS    6
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define CPU_PCI_FUNCS   6
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MAX_BUS_NUMBER  max_bus_number
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SOCKET_BUS(cpu) (MAX_BUS_NUMBER - (cpu))
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define CPU_ID_RD(cpu)  nhm_pci_getl(SOCKET_BUS(cpu), 0, 0, 0, 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_CONTROL_RD(cpu) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x48, 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_STATUS_RD(cpu) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x4c, 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_SMI_SPARE_DIMM_ERROR_STATUS_RD(cpu) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x50, 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_CPU_RAS_RD(cpu) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0, 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_SCRUB_CONTROL_RD(cpu) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x4c, 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_SCRUB_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    0x4c, reg);
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_SSR_CONTROL_RD(cpu)  nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x48, 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_SSR_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, 0x48, \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    reg);
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_SSR_SCRUB_CONTROL_RD(cpu)    nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    0x4c, 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_RAS_ENABLES_RD(cpu)  nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x50, 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_RAS_STATUS_RD(cpu)   nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x54, 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_SSR_STATUS_RD(cpu)   nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x60, 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_CHANNEL_MAPPER_RD(cpu)   nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    0x60, 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_COR_ECC_CNT_RD(cpu, select) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x80 + ((select) * 4), 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_CHANNEL_RANK_PRESENT_RD(cpu, channel) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 0, 0x7c, 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_DOD_RD(cpu, channel, select) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 1, 0x48 + ((select) * 4), 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_SAG_RD(cpu, channel, select) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 1, 0x80 + ((select) * 4), 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_RIR_LIMIT_RD(cpu, channel, select) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 2, 0x40 + ((select) * 4), 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_RIR_WAY_RD(cpu, channel, select) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 2, 0x80 + ((select) * 4), 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_CHANNEL_DIMM_INIT_PARAMS_RD(cpu, channel) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 0, 0x58, 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SAD_DRAM_RULE_RD(cpu, rule) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    nhm_pci_getl(SOCKET_BUS(cpu), 0, 1, 0x80 + (4 * (rule)), 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SAD_INTERLEAVE_LIST_RD(cpu, rule) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    nhm_pci_getl(SOCKET_BUS(cpu), 0, 1, 0xc0 + (4 * (rule)), 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define TAD_DRAM_RULE_RD(cpu, rule) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    nhm_pci_getl(SOCKET_BUS(cpu), 3, 1, 0x80 + (4 * (rule)), 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define TAD_INTERLEAVE_LIST_RD(cpu, rule) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    nhm_pci_getl(SOCKET_BUS(cpu), 3, 1, 0xc0 + (4 * (rule)), 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_DIMM_CLK_RATIO_STATUS(cpu) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    nhm_pci_getl(SOCKET_BUS(cpu), 3, 4, 0x50, 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/*
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * MC_CONTROL
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_CONTROL_CHANNEL_ACTIVE(reg, channel) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    ((reg) & (1 << (8 + (channel))) != 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_CONTROL_ECCEN(reg) (((reg) >> 1) & 1)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_CONTROL_CLOSED_PAGE(reg) ((reg) & 1)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MC_CONTROL_DIVBY3(reg) ((reg >> 6) &1)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define NUM_CACHELINE_BITS  6   /* Cachelines are 64B */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov/*
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov * MC_STATUS
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov */
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov#define CHANNEL_DISABLED(reg, channel) ((reg) & (1 << (channel)))
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov#define WS_ECC_ENABLED  0x10
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/*
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * MC_CHANNEL_DIMM_INIT_PARAMS
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define THREE_DIMMS_PRESENT     (1 << 24) /* not quad rank */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SINGLE_QUAD_RANK_PRESENT    (1 << 23)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define QUAD_RANK_PRESENT       (1 << 22) /* 1 or 2 quad rank dimms */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define REGISTERED_DIMM         (1 << 15)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/*
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * MC_DOD_CH
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define RANKOFFSET(reg) (((reg) >> 10) & 7)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define DIMMPRESENT(reg) (((reg) & (1 << 9)) != 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define NUMBANK(reg) (((reg) & (3 << 7)) == 0 ? 4 : (((reg) >> 7) & 3) * 8)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define NUMRANK(reg) (((reg) & (3 << 5)) == 0 ? 1 : (((reg) >> 5) & 3) * 2)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define NUMROW(reg) ((((reg) >> 2) & 7) + 12)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define NUMCOL(reg) (((reg) & 3) + 10)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define DIMMWIDTH   8
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define DIMMSIZE(reg) ((1ULL << (NUMCOL(reg) + NUMROW(reg))) * NUMRANK(reg) \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    * NUMBANK(reg) * DIMMWIDTH)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov/*
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov * MC_SAG_CH
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define DIVBY3(reg) (((reg) >> 27) & 1) /* 3 or 6 way interleave */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define REMOVE_6(reg)   (((reg) >> 24) & 1)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define REMOVE_7(reg)   (((reg) >> 25) & 1)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define REMOVE_8(reg)   (((reg) >> 26) & 1)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define CH_ADDRESS_OFFSET(reg) \
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov    (int64_t)((uint64_t)(reg) & 0x00ffffff)
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov#define CH_ADDRESS_SOFFSET(reg) \
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov    ((int64_t)(((uint64_t)(reg) & 0x00ffffff) << 40) >>40)
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov/* SAG offset covers SA[39:16] so granularity is 2^16 = 64KB */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SAG_OFFSET_GRANULARITY  16
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/* 24-bit mask for TTMAD_CR_SAG_CH*.OFFSET */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SAG_OFFSET_SIZE_MASK    0xffffffULL
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/* 16-bit mask for lower bits not covered by CREG value (SA[15:0]) */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SAG_OFFSET_ADDR_MASK    0xffffULL
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define CACHELINE_ADDR_MASK 0x3fULL /* 6-bit mask */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
d15978eab6c23a98f0a5474466d5fe9b1be3ca9bGary Mills/*
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * MC_RIR_LIMIT_CH
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define RIR_LIMIT(reg)  ((((uint64_t)(reg) & 0x000003ff) + 1) << 28)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/*
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * MC_RIR_WAY_CH
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define RIR_OFFSET(reg) (int64_t)((uint64_t)(reg >> 4)& 0x3ff)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define RIR_SOFFSET(reg)    ((int64_t)(((uint64_t)(reg) & 0x3ff0) << 50) \
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov                    >> 54)
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov#define RIR_DIMM_RANK(reg)  ((reg) & 0xf)
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov#define RIR_RANK(reg)   ((reg) & 0x3)
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov#define RIR_DIMM(reg)   ((reg)>>2 & 0x03)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define RIR_OFFSET_SIZE_MASK    0x3ff
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MAX_RIR_WAY 4
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define RIR_LIMIT_GRANULARITY   28
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define RIR_OFFSET_ADDR_MASK    0xfffffffULL    /* 28-bit mask */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define RIR_INTLV_PGOPEN_BIT    12  /* Rank interleaving */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define RIR_INTLV_PGOPEN_MASK   0xfffULL    /* 12-bit mask */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define RIR_INTLV_PGCLS_BIT 6   /* Rank interleaving */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define RIR_INTLV_PGCLS_MASK    0x3fULL /* 6-bit mask */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define RIR_INTLV_SIZE_MASK 0x3ULL
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/*
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * MC_RAS_ENABLES
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define RAS_LOCKSTEP_ENABLE(reg) (((reg) & 2) != 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define RAS_MIRROR_MEM_ENABLE(reg) (((reg) & 1) != 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/*
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * MC_RAS_STATUS
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define REDUNDANCY_LOSS(reg) (((reg) & 1) != 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/*
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * MC_SSRSTATUS
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SPAREING_IN_PROGRESS(reg) (((reg) & 2) != 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SPAREING_COMPLETE(reg) (((reg) & 1) != 0)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/*
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * MC_SSR_CONTROL
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SSR_MODE(reg) ((reg) & 3)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SSR_IDLE    0
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SSR_SCRUB   1
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SSR_SPARE   2
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define DEMAND_SCRUB_ENABLE (1 << 6)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/*
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * MC_SCRUB_CONTROL
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define STARTSCRUB  (1 << 24)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/*
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * MC_DIMM_CLK_RATIO_STATUS
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov */
e50226eccc6dfcba3cc6f0df38438900e3df225cYuri Pankov#define MAX_DIMM_CLK_RATIO(reg) (((reg) >> 24) & 0x1f)
da17b20b93fdfe86e22d0e290ed2601a95e74977Damian Wojslaw/*
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * MC_SMI_SPARE_DIMM_ERROR_STATUS_RD
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define REDUNDANCY_LOSS_FAILING_DIMM(status) (((status) >> 12) & 3)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define DIMM_ERROR_OVERFLOW_STATUS(status) ((status) & 0xfff)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MAX_MEMORY_CONTROLLERS  MAX_CPU_NODES
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define CHANNELS_PER_MEMORY_CONTROLLER  3
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MAX_DIMMS_PER_CHANNEL   3
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/*
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * SAD_DRAM_RULE
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SAD_DRAM_LIMIT(sad) ((((uint64_t)(sad) & 0x000fffc0ULL) + 0x40) << 20)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SAD_DRAM_MODE(sad) (((sad) >> 1) & 3)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SAD_DRAM_RULE_ENABLE(sad) ((sad) & 1)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/*
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * from SAD_DRAM_RULE*.MODE
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define DIRECT  0
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define XOR 1
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MOD3    2
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SAD_INTERLEAVE(list, num)   (((list) >> ((num) * 4)) & 0x3)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define INTERLEAVE_NWAY 8
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MAX_SAD_DRAM_RULE   8
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SAD_LIMIT_GRANULARITY   26
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SAD_LIMIT_ADDR_MASK 0x3ffffffULL
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SAD_INTLV_DIRECT_BIT    6
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SAD_INTLV_XOR_BIT   16
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SAD_INTLV_SIZE_MASK 0x7ULL
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define SAD_INTLV_ADDR_MASK 0x3fULL
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/*
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * TAD_DRAM_RULE
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define TAD_DRAM_LIMIT(tad) ((((uint64_t)(tad) & 0x000fffc0ULL) + 0x40) << 20)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define TAD_DRAM_MODE(tad) (((tad) >> 1) & 3)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define TAD_DRAM_RULE_ENABLE(tad) ((tad) & 1)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define TAD_INTERLEAVE(list, channel) (((list) >> ((channel) * 4)) & 3)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define MAX_TAD_DRAM_RULE 8
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define VRANK_SZ 0x10000000
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amoretypedef struct sad {
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    uint64_t limit;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    uint32_t node_list;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    uint32_t node_tgt[INTERLEAVE_NWAY];
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    char mode;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    char enable;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    char interleave;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore} sad_t;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amoretypedef struct tad {
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    uint64_t limit;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    uint32_t pkg_list;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    uint32_t pkg_tgt[INTERLEAVE_NWAY];
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    char mode;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    char enable;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    char interleave;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore} tad_t;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amoretypedef struct sag_ch {
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    uint32_t offset;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    int32_t soffset;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    char divby3;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    char remove6;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    char remove7;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    char remove8;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore} sag_ch_t;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amoretypedef struct rir_way {
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    uint16_t offset;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    int16_t soffset;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    uint8_t rank;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    uint8_t dimm;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    uint8_t dimm_rank;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    uint64_t rlimit;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore} way_t;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amoretypedef struct rir {
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    uint64_t limit;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    way_t way[MAX_RIR_WAY];
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    char interleave;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore} rir_t;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amoretypedef struct dod_type {
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    int NUMCol;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    int NUMRow;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    int NUMRank;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    int NUMBank;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    int DIMMPresent;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    int RankOffset;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore} dod_t;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore/*
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore * MC_CHANNEL_MAPPER
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore */
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#define CHANNEL_MAP(reg, channel, write) (((reg) >> ((channel) * 6 + \
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore    ((write) ? 0 : 3))) & 7)
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amoreextern int max_bus_number;
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#ifdef __cplusplus
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore}
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore#endif
84441f85b19f6b8080883f30109e58e43c893709Garrett D'Amore
c530934a778b6ba8ad55ddb0e3bbee8faa6260b0Garrett D'Amore#endif /* _INTEL_NHM_H */
9384cec630155c229c70dfb8a445c6ccf433045aJohann 'Myrkraverk' Oskarsson