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678453a8ed49104d8adad58f3ba591bdc39883e8speer * CDDL HEADER END
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Use is subject to license terms.
678453a8ed49104d8adad58f3ba591bdc39883e8speer#pragma ident "%Z%%M% %I% %E% SMI"
678453a8ed49104d8adad58f3ba591bdc39883e8speerextern "C" {
678453a8ed49104d8adad58f3ba591bdc39883e8speer * RXDMA_REG_WRITE64
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Write a 64-bit value to a DMC register.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * This is the old, rather convoluted, macro.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define RXDMA_REG_WRITE64(handle, reg, channel, data) { \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * NXGE_REG_WR64(handle, (NXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\
678453a8ed49104d8adad58f3ba591bdc39883e8speer * channel)), (data)) \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * There are 3 versions of NXGE_REG_WR64:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * -------------------------------------------------------------
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #if defined(REG_TRACE)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define NXGE_REG_WR64(handle, offset, val) { \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * NXGE_NPI_PIO_WRITE64(handle, (offset), (val)); \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * npi_rtrace_update(handle, B_TRUE, &npi_rtracebuf, (uint32_t)offset, \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * (uint64_t)(val)); \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #elif defined(REG_SHOW)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define NXGE_REG_WR64(handle, offset, val) {\
678453a8ed49104d8adad58f3ba591bdc39883e8speer * NXGE_NPI_PIO_WRITE64(handle, offset, (val));\
678453a8ed49104d8adad58f3ba591bdc39883e8speer * rt_show_reg(0xbadbad, B_TRUE, (uint32_t)offset, (uint64_t)(val));\
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define NXGE_REG_WR64(handle, offset, val) {\
678453a8ed49104d8adad58f3ba591bdc39883e8speer * NXGE_NPI_PIO_WRITE64(handle, (offset), (val));\
678453a8ed49104d8adad58f3ba591bdc39883e8speer * There are 2 versions of NXGE_NPI_PIO_WRITE64:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * -------------------------------------------------------------
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #if defined(__i386)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define NXGE_NPI_PIO_WRITE64(npi_handle, offset, data) \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * (ddi_put64(NPI_REGH(npi_handle), \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * (uint64_t *)(NPI_REGP(npi_handle) + (uint32_t)offset), data))
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define NXGE_NPI_PIO_WRITE64(npi_handle, offset, data) \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * (ddi_put64(NPI_REGH(npi_handle), \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * (uint64_t *)(NPI_REGP(npi_handle) + offset), data))
678453a8ed49104d8adad58f3ba591bdc39883e8speer * -------------------------------------------------------------
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define NPI_REGH(npi_handle) (npi_handle.regh)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define NPI_REGP(npi_handle) (npi_handle.regp)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Now let's tackle NXGE_RXDMA_OFFSET
678453a8ed49104d8adad58f3ba591bdc39883e8speer * -------------------------------------------------------------
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define NXGE_RXDMA_OFFSET(x, v, channel) (x + \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * (!v ? DMC_OFFSET(channel) : \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * RDMC_PIOVADDR_OFFSET(channel)))
678453a8ed49104d8adad58f3ba591bdc39883e8speer * -------------------------------------------------------------
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define DMC_OFFSET(channel) (DMA_CSR_SIZE * channel)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define TDMC_PIOVADDR_OFFSET(channel) (2 * DMA_CSR_SIZE * channel)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * -------------------------------------------------------------
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define RDMC_PIOVADDR_OFFSET(channel) \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * (TDMC_OFFSET(channel) + DMA_CSR_SIZE)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * -------------------------------------------------------------
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define DMA_CSR_SIZE 512
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define TDMC_OFFSET(channel) (TX_RNG_CFIG + DMA_CSR_SIZE * channel)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define TX_RNG_CFIG (DMC + 0x40000)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * -------------------------------------------------------------
678453a8ed49104d8adad58f3ba591bdc39883e8speer * This definition is clearly wrong! I think this was intended:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define RDMC_PIOVADDR_OFFSET(channel) \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * (TDMC_PIOVADDR__OFFSET(channel) + DMA_CSR_SIZE)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * -------------------------------------------------------------
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Finally, we have the full macro:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * -------------------------------------------------------------
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define RXDMA_REG_WRITE64(handle, reg, channel, data) { \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * NXGE_REG_WR64(handle, (NXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\
678453a8ed49104d8adad58f3ba591bdc39883e8speer * channel)), (data)) \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * ddi_put64(handle.regh, (uint64_t*)(handle.regp + ((0x600000 + 0x00000) +
678453a8ed49104d8adad58f3ba591bdc39883e8speer * (!handle.is_vraddr ?
678453a8ed49104d8adad58f3ba591bdc39883e8speer * (512 * channel) :
678453a8ed49104d8adad58f3ba591bdc39883e8speer * (0x600000 + 0x40000 + 512 * channel + 512))), data);
678453a8ed49104d8adad58f3ba591bdc39883e8speerstatic void RXDMA_REG_WRITE64(npi_handle_t, uint64_t, int, uint64_t);
678453a8ed49104d8adad58f3ba591bdc39883e8speer#pragma inline(RXDMA_REG_WRITE64)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * RXDMA_REG_WRITE64
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Write a 64-bit value to a DMC register.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Arguments:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * handle The NPI handle to use.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset The offset into the DMA CSR (the register).
678453a8ed49104d8adad58f3ba591bdc39883e8speer * channel The channel, which is used as a multiplicand.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * value The 64-bit value to write.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * If handle.regp is a virtual address (the address of a VR),
678453a8ed49104d8adad58f3ba591bdc39883e8speer * we have to subtract the value DMC right off the bat. DMC
678453a8ed49104d8adad58f3ba591bdc39883e8speer * is defined as 0x600000, which works in a non-virtual address
678453a8ed49104d8adad58f3ba591bdc39883e8speer * space, but not in a VR. In a VR, a DMA CSR's space begins
678453a8ed49104d8adad58f3ba591bdc39883e8speer * at zero (0). So, since every call to RXMDA_REG_READ64 uses
678453a8ed49104d8adad58f3ba591bdc39883e8speer * a register macro which adds in DMC, we have to subtract it.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * The rest of it is pretty straighforward. In a VR, a channel is
678453a8ed49104d8adad58f3ba591bdc39883e8speer * logical, not absolute; and every DMA CSR is 512 bytes big;
678453a8ed49104d8adad58f3ba591bdc39883e8speer * furthermore, a subpage of a VR is always ordered with the
678453a8ed49104d8adad58f3ba591bdc39883e8speer * transmit CSRs first, followed by the receive CSRs. That is,
678453a8ed49104d8adad58f3ba591bdc39883e8speer * a 512 byte space of Tx CSRs, followed by a 512 byte space of
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Rx CSRs. Hence this calculation:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += ((channel << 1) + 1) << DMA_CSR_SLL;
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Here's an example:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, value);
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Let's say channel is 3
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define RX_DMA_CTL_STAT_REG (DMC + 0x00070)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset = 0x600070
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset &= 0xff = 0x70
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += ((3 << 1) + 1) << 9
678453a8ed49104d8adad58f3ba591bdc39883e8speer * 3 << 1 = 6
678453a8ed49104d8adad58f3ba591bdc39883e8speer * 6 + 1 = 7
678453a8ed49104d8adad58f3ba591bdc39883e8speer * 7 << 9 = 0xe00
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += 0xe00 = 0xe70
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Therefore, our register's (virtual) PIO address is 0xe70.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * cf. Table 10-6 on page 181 of the Neptune PRM, v 1.4:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * E00 - FFF CSRs for bound logical receive DMA channel 3.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * In a non-virtual environment, you simply multiply the absolute
678453a8ed49104d8adad58f3ba591bdc39883e8speer * channel number by 512 bytes, and get the correct offset to
678453a8ed49104d8adad58f3ba591bdc39883e8speer * the register you're looking for. That is, the RX_DMA_CTL_STAT CSR,
678453a8ed49104d8adad58f3ba591bdc39883e8speer * is, as are all of these registers, in a table where each channel
678453a8ed49104d8adad58f3ba591bdc39883e8speer * is offset 512 bytes from the previous channel (count 16 step 512).
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += (channel << DMA_CSR_SLL); // channel<<9 = channel*512
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Here's an example:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, value);
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Let's say channel is 3
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define RX_DMA_CTL_STAT_REG (DMC + 0x00070)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset = 0x600070
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += (3 << 9)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * 3 << 9 = 0x600
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += 0x600 = 0x600670
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Therefore, our register's PIO address is 0x600670.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * cf. Table 12-42 on page 234 of the Neptune PRM, v 1.4:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * RX_DMA_CTL_STAT (DMC + [0x]00070) (count 16 step [0x]200)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Any domain
678453a8ed49104d8adad58f3ba591bdc39883e8speerextern const char *nxge_rx2str(int);
678453a8ed49104d8adad58f3ba591bdc39883e8speer#if defined(__i386)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Since we don't have a valid RTBUF index to show, send 0xBADBAD.
678453a8ed49104d8adad58f3ba591bdc39883e8speer rt_show_reg(0xbadbad, B_TRUE, (uint32_t)offset, value);
678453a8ed49104d8adad58f3ba591bdc39883e8speer#endif /* _NPI_RX_WR64_H */