Lines Matching refs:channel
48 #define HXGE_TXDMA_OFFSET(x, v, channel) (x + \
49 (!v ? DMC_OFFSET(channel) : TDMC_PIOVADDR_OFFSET(channel)))
53 #define TXDMA_REG_READ64(handle, reg, channel, val_p) \
55 (HXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel)), val_p)
57 #define TXDMA_REG_WRITE64(handle, reg, channel, data) \
59 HXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel), data)
104 uint8_t channel, tdc_page_handle_t *hdl_p);
105 hpi_status_t hpi_txdma_channel_reset(hpi_handle_t handle, uint8_t channel);
107 uint8_t channel);
108 hpi_status_t hpi_txdma_channel_enable(hpi_handle_t handle, uint8_t channel);
109 hpi_status_t hpi_txdma_channel_disable(hpi_handle_t handle, uint8_t channel);
111 uint8_t channel);
113 txdma_cs_cntl_t control, uint8_t channel);
115 uint8_t channel, tdc_stat_t *cs_p);
118 uint8_t channel, tdc_int_mask_t *mask_p);
121 uint8_t channel, uint64_t *reg_data);
123 uint8_t channel, uint64_t *mbox_addr);
129 uint8_t channel);
135 hpi_status_t hpi_txdma_ring_head_get(hpi_handle_t handle, uint8_t channel,