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678453a8ed49104d8adad58f3ba591bdc39883e8speer * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
678453a8ed49104d8adad58f3ba591bdc39883e8speer * See the License for the specific language governing permissions
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678453a8ed49104d8adad58f3ba591bdc39883e8speer * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Use is subject to license terms.
678453a8ed49104d8adad58f3ba591bdc39883e8speer#pragma ident "%Z%%M% %I% %E% SMI"
678453a8ed49104d8adad58f3ba591bdc39883e8speerextern "C" {
678453a8ed49104d8adad58f3ba591bdc39883e8speerstatic uint32_t RXDMA_REG_READ32(npi_handle_t, uint32_t, int);
678453a8ed49104d8adad58f3ba591bdc39883e8speer#pragma inline(RXDMA_REG_READ32)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * RXDMA_REG_READ32
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Read a 32-bit value from a DMC register.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Arguments:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * handle The NPI handle to use.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset The offset into the DMA CSR (the register).
678453a8ed49104d8adad58f3ba591bdc39883e8speer * channel The channel, which is used as a multiplicand.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * If handle.regp is a virtual address (the address of a VR),
678453a8ed49104d8adad58f3ba591bdc39883e8speer * we have to subtract the value DMC right off the bat. DMC
678453a8ed49104d8adad58f3ba591bdc39883e8speer * is defined as 0x600000, which works in a non-virtual address
678453a8ed49104d8adad58f3ba591bdc39883e8speer * space, but not in a VR. In a VR, a DMA CSR's space begins
678453a8ed49104d8adad58f3ba591bdc39883e8speer * at zero (0). So, since every call to RXMDA_REG_READ32 uses
678453a8ed49104d8adad58f3ba591bdc39883e8speer * a register macro which adds in DMC, we have to subtract it.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * The rest of it is pretty straighforward. In a VR, a channel is
678453a8ed49104d8adad58f3ba591bdc39883e8speer * logical, not absolute; and every DMA CSR is 512 bytes big;
678453a8ed49104d8adad58f3ba591bdc39883e8speer * furthermore, a subpage of a VR is always ordered with the
678453a8ed49104d8adad58f3ba591bdc39883e8speer * transmit CSRs first, followed by the receive CSRs. That is,
678453a8ed49104d8adad58f3ba591bdc39883e8speer * a 512 byte space of Tx CSRs, followed by a 512 byte space of
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Rx CSRs. Hence this calculation:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += ((channel << 1) + 1) << DMA_CSR_SLL;
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Here's an example:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * RXDMA_REG_READ32(handle, RX_DMA_CTL_STAT_REG, channel);
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Let's say channel is 3
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define RX_DMA_CTL_STAT_REG (DMC + 0x00070)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset = 0x600070
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset &= 0xff = 0x70
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += ((3 << 1) + 1) << 9
678453a8ed49104d8adad58f3ba591bdc39883e8speer * 3 << 1 = 6
678453a8ed49104d8adad58f3ba591bdc39883e8speer * 6 + 1 = 7
678453a8ed49104d8adad58f3ba591bdc39883e8speer * 7 << 9 = 0xe00
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += 0xe00 = 0xe70
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Therefore, our register's (virtual) PIO address is 0xe70.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * cf. Table 10-6 on page 181 of the Neptune PRM, v 1.4:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * E00 - FFF CSRs for bound logical receive DMA channel 3.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * In a non-virtual environment, you simply multiply the absolute
678453a8ed49104d8adad58f3ba591bdc39883e8speer * channel number by 512 bytes, and get the correct offset to
678453a8ed49104d8adad58f3ba591bdc39883e8speer * the register you're looking for. That is, the RX_DMA_CTL_STAT CSR,
678453a8ed49104d8adad58f3ba591bdc39883e8speer * is, as are all of these registers, in a table where each channel
678453a8ed49104d8adad58f3ba591bdc39883e8speer * is offset 512 bytes from the previous channel (count 16 step 512).
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += (channel << DMA_CSR_SLL); // channel<<9 = channel*512
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Here's an example:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * RXDMA_REG_READ32(handle, RX_DMA_CTL_STAT_REG, channel);
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Let's say channel is 3
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define RX_DMA_CTL_STAT_REG (DMC + 0x00070)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset = 0x600070
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += (3 << 9)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * 3 << 9 = 0x600
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += 0x600 = 0x600670
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Therefore, our register's PIO address is 0x600670.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * cf. Table 12-42 on page 234 of the Neptune PRM, v 1.4:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * RX_DMA_CTL_STAT (DMC + [0x]00070) (count 16 step [0x]200)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Guest domain
678453a8ed49104d8adad58f3ba591bdc39883e8speer return (ddi_get32(handle.regh, (uint32_t *)(handle.regp + offset)));
678453a8ed49104d8adad58f3ba591bdc39883e8speer#endif /* _NPI_RX_RD32_H */