678453a8ed49104d8adad58f3ba591bdc39883e8speer * CDDL HEADER START
678453a8ed49104d8adad58f3ba591bdc39883e8speer * The contents of this file are subject to the terms of the
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Common Development and Distribution License (the "License").
678453a8ed49104d8adad58f3ba591bdc39883e8speer * You may not use this file except in compliance with the License.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
678453a8ed49104d8adad58f3ba591bdc39883e8speer * See the License for the specific language governing permissions
678453a8ed49104d8adad58f3ba591bdc39883e8speer * and limitations under the License.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * When distributing Covered Code, include this CDDL HEADER in each
678453a8ed49104d8adad58f3ba591bdc39883e8speer * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * If applicable, add the following below this CDDL HEADER, with the
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678453a8ed49104d8adad58f3ba591bdc39883e8speer * information: Portions Copyright [yyyy] [name of copyright owner]
678453a8ed49104d8adad58f3ba591bdc39883e8speer * CDDL HEADER END
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Use is subject to license terms.
678453a8ed49104d8adad58f3ba591bdc39883e8speer#pragma ident "%Z%%M% %I% %E% SMI"
678453a8ed49104d8adad58f3ba591bdc39883e8speerextern "C" {
678453a8ed49104d8adad58f3ba591bdc39883e8speerstatic void TXDMA_REG_READ64(npi_handle_t, uint64_t, int, uint64_t *);
678453a8ed49104d8adad58f3ba591bdc39883e8speer#pragma inline(TXDMA_REG_READ64)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * TXDMA_REG_READ64
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Read a 64-bit value from a DMC register.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Arguments:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * handle The NPI handle to use.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset The offset into the DMA CSR (the register).
678453a8ed49104d8adad58f3ba591bdc39883e8speer * channel The channel, which is used as a multiplicand.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * value Where to put the 64-bit value to be read.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * For reference, here is the old macro:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define TXDMA_REG_READ64(handle, reg, channel, val_p) \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * NXGE_REG_RD64(handle, \
678453a8ed49104d8adad58f3ba591bdc39883e8speer * (NXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel)), val_p)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * If handle.regp is a virtual address (the address of a VR),
678453a8ed49104d8adad58f3ba591bdc39883e8speer * we have to subtract the value DMC right off the bat. DMC
678453a8ed49104d8adad58f3ba591bdc39883e8speer * is defined as 0x600000, which works in a non-virtual address
678453a8ed49104d8adad58f3ba591bdc39883e8speer * space, but not in a VR. In a VR, a DMA CSR's space begins
678453a8ed49104d8adad58f3ba591bdc39883e8speer * at zero (0). So, since every call to RXMDA_REG_READ64 uses
678453a8ed49104d8adad58f3ba591bdc39883e8speer * a register macro which adds in DMC, we have to subtract it.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * The rest of it is pretty straighforward. In a VR, a channel is
678453a8ed49104d8adad58f3ba591bdc39883e8speer * logical, not absolute; and every DMA CSR is 512 bytes big;
678453a8ed49104d8adad58f3ba591bdc39883e8speer * furthermore, a subpage of a VR is always ordered with the
678453a8ed49104d8adad58f3ba591bdc39883e8speer * transmit CSRs first, followed by the receive CSRs. That is,
678453a8ed49104d8adad58f3ba591bdc39883e8speer * a 512 byte space of Tx CSRs, followed by a 512 byte space of
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Rx CSRs. Hence this calculation:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += ((channel << 1) << DMA_CSR_SLL);
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Here's an example:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * TXDMA_REG_READ64(handle, TX_CS_REG, channel, &value);
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Let's say channel is 3
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define TX_CS_REG (DMC + 0x40028)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset = 0x640028
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset &= 0xff = 0x28
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += ((3 << 1) << 9)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * 3 << 1 = 6
678453a8ed49104d8adad58f3ba591bdc39883e8speer * 6 << 9 = 0xc00
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += 0xc00 = 0xc28
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Therefore, our register's (virtual) PIO address is 0xc28.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * cf. Table 10-6 on page 181 of the Neptune PRM, v 1.4:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * C00 - dFF CSRs for bound logical transmit DMA channel 3.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * In a non-virtual environment, you simply multiply the absolute
678453a8ed49104d8adad58f3ba591bdc39883e8speer * channel number by 512 bytes, and get the correct offset to
678453a8ed49104d8adad58f3ba591bdc39883e8speer * the register you're looking for. That is, the RX_DMA_CTL_STAT CSR,
678453a8ed49104d8adad58f3ba591bdc39883e8speer * is, as are all of these registers, in a table where each channel
678453a8ed49104d8adad58f3ba591bdc39883e8speer * is offset 512 bytes from the previous channel (count 16 step 512).
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += (channel << DMA_CSR_SLL); // channel<<9 = channel*512
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Here's an example:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * TXDMA_REG_READ64(handle, TX_CS_REG, channel, &value);
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Let's say channel is 3
678453a8ed49104d8adad58f3ba591bdc39883e8speer * #define TX_CS_REG (DMC + 0x40028)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset = 0x640028
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += (3 << 9)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * 3 << 9 = 0x600
678453a8ed49104d8adad58f3ba591bdc39883e8speer * offset += 0x600 = 0x640628
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Therefore, our register's PIO address is 0x640628.
678453a8ed49104d8adad58f3ba591bdc39883e8speer * cf. Table 13-15 on page 265 of the Neptune PRM, v 1.4:
678453a8ed49104d8adad58f3ba591bdc39883e8speer * TX_CS (DMC + 4002816) (count 24 step 0x200)
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Any domain
678453a8ed49104d8adad58f3ba591bdc39883e8speerextern const char *nxge_tx2str(int);
678453a8ed49104d8adad58f3ba591bdc39883e8speer#if defined(__i386)
678453a8ed49104d8adad58f3ba591bdc39883e8speer *value = ddi_get64(handle.regh, (uint64_t *)(handle.regp + offset));
678453a8ed49104d8adad58f3ba591bdc39883e8speer * Since we don't have a valid RTBUF index to show, send 0xBADBAD.
678453a8ed49104d8adad58f3ba591bdc39883e8speer rt_show_reg(0xbadbad, B_FALSE, (uint32_t)offset, *value);
678453a8ed49104d8adad58f3ba591bdc39883e8speer#endif /* _NPI_TX_RD64_H */