a23fd118e437af0a7877dd313db8fdaa3537c675yl/*
a23fd118e437af0a7877dd313db8fdaa3537c675yl * CDDL HEADER START
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * The contents of this file are subject to the terms of the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Common Development and Distribution License (the "License").
a23fd118e437af0a7877dd313db8fdaa3537c675yl * You may not use this file except in compliance with the License.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
a23fd118e437af0a7877dd313db8fdaa3537c675yl * or http://www.opensolaris.org/os/licensing.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See the License for the specific language governing permissions
a23fd118e437af0a7877dd313db8fdaa3537c675yl * and limitations under the License.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * When distributing Covered Code, include this CDDL HEADER in each
a23fd118e437af0a7877dd313db8fdaa3537c675yl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * If applicable, add the following below this CDDL HEADER, with the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * fields enclosed by brackets "[]" replaced with your own identifying
a23fd118e437af0a7877dd313db8fdaa3537c675yl * information: Portions Copyright [yyyy] [name of copyright owner]
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * CDDL HEADER END
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * Copyright (c) 2002-2006 Neterion, Inc.
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include "xgehal-ring.h"
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include "xgehal-device.h"
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING)
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic ptrdiff_t
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_item_dma_offset(xge_hal_mempool_h mempoolh,
a23fd118e437af0a7877dd313db8fdaa3537c675yl void *item)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl int memblock_idx;
a23fd118e437af0a7877dd313db8fdaa3537c675yl void *memblock;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* get owner memblock index */
a23fd118e437af0a7877dd313db8fdaa3537c675yl memblock_idx = __hal_ring_block_memblock_idx(item);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* get owner memblock by memblock index */
a23fd118e437af0a7877dd313db8fdaa3537c675yl memblock = __hal_mempool_memblock(mempoolh, memblock_idx);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl return (char*)item - (char*)memblock;
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic dma_addr_t
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_item_dma_addr(xge_hal_mempool_h mempoolh, void *item,
a23fd118e437af0a7877dd313db8fdaa3537c675yl pci_dma_h *dma_handle)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl int memblock_idx;
a23fd118e437af0a7877dd313db8fdaa3537c675yl void *memblock;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_mempool_dma_t *memblock_dma_object;
a23fd118e437af0a7877dd313db8fdaa3537c675yl ptrdiff_t dma_item_offset;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* get owner memblock index */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl memblock_idx = __hal_ring_block_memblock_idx((xge_hal_ring_block_t *) item);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* get owner memblock by memblock index */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl memblock = __hal_mempool_memblock((xge_hal_mempool_t *) mempoolh,
8347601bcb0a439f6e50fc36b4039a73d08700e1yl memblock_idx);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* get memblock DMA object by memblock index */
a23fd118e437af0a7877dd313db8fdaa3537c675yl memblock_dma_object =
8347601bcb0a439f6e50fc36b4039a73d08700e1yl __hal_mempool_memblock_dma((xge_hal_mempool_t *) mempoolh,
8347601bcb0a439f6e50fc36b4039a73d08700e1yl memblock_idx);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* calculate offset in the memblock of this item */
a23fd118e437af0a7877dd313db8fdaa3537c675yl dma_item_offset = (char*)item - (char*)memblock;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl *dma_handle = memblock_dma_object->handle;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl return memblock_dma_object->addr + dma_item_offset;
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic void
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_rxdblock_link(xge_hal_mempool_h mempoolh,
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ring_t *ring, int from, int to)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ring_block_t *to_item, *from_item;
a23fd118e437af0a7877dd313db8fdaa3537c675yl dma_addr_t to_dma, from_dma;
a23fd118e437af0a7877dd313db8fdaa3537c675yl pci_dma_h to_dma_handle, from_dma_handle;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* get "from" RxD block */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl from_item = (xge_hal_ring_block_t *)
8347601bcb0a439f6e50fc36b4039a73d08700e1yl __hal_mempool_item((xge_hal_mempool_t *) mempoolh, from);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_assert(from_item);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* get "to" RxD block */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl to_item = (xge_hal_ring_block_t *)
8347601bcb0a439f6e50fc36b4039a73d08700e1yl __hal_mempool_item((xge_hal_mempool_t *) mempoolh, to);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_assert(to_item);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* return address of the beginning of previous RxD block */
a23fd118e437af0a7877dd313db8fdaa3537c675yl to_dma = __hal_ring_item_dma_addr(mempoolh, to_item, &to_dma_handle);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* set next pointer for this RxD block to point on
a23fd118e437af0a7877dd313db8fdaa3537c675yl * previous item's DMA start address */
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_ring_block_next_pointer_set(from_item, to_dma);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* return "from" RxD block's DMA start address */
a23fd118e437af0a7877dd313db8fdaa3537c675yl from_dma =
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_ring_item_dma_addr(mempoolh, from_item, &from_dma_handle);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING)
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* we must sync "from" RxD block, so hardware will see it */
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_dma_sync(ring->channel.pdev,
a23fd118e437af0a7877dd313db8fdaa3537c675yl from_dma_handle,
a23fd118e437af0a7877dd313db8fdaa3537c675yl from_dma + XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET,
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_ring_item_dma_offset(mempoolh, from_item) +
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET,
a23fd118e437af0a7877dd313db8fdaa3537c675yl sizeof(u64),
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_OS_DMA_DIR_TODEVICE);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl xge_debug_ring(XGE_TRACE, "block%d:0x"XGE_OS_LLXFMT" => block%d:0x"XGE_OS_LLXFMT,
a23fd118e437af0a7877dd313db8fdaa3537c675yl from, (unsigned long long)from_dma, to,
a23fd118e437af0a7877dd313db8fdaa3537c675yl (unsigned long long)to_dma);
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic xge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_mempool_item_alloc(xge_hal_mempool_h mempoolh,
a23fd118e437af0a7877dd313db8fdaa3537c675yl void *memblock,
a23fd118e437af0a7877dd313db8fdaa3537c675yl int memblock_index,
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_mempool_dma_t *dma_object,
a23fd118e437af0a7877dd313db8fdaa3537c675yl void *item,
a23fd118e437af0a7877dd313db8fdaa3537c675yl int index,
a23fd118e437af0a7877dd313db8fdaa3537c675yl int is_last,
a23fd118e437af0a7877dd313db8fdaa3537c675yl void *userdata)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl int i;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ring_t *ring = (xge_hal_ring_t *)userdata;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_assert(item);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_assert(ring);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* format rxds array */
a23fd118e437af0a7877dd313db8fdaa3537c675yl for (i=ring->rxds_per_block-1; i>=0; i--) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl void *rxdblock_priv;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ring_rxd_priv_t *rxd_priv;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ring_rxd_1_t *rxdp;
a23fd118e437af0a7877dd313db8fdaa3537c675yl int reserve_index = index * ring->rxds_per_block + i;
a23fd118e437af0a7877dd313db8fdaa3537c675yl int memblock_item_idx;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->reserved_rxds_arr[reserve_index] = (char *)item +
a23fd118e437af0a7877dd313db8fdaa3537c675yl (ring->rxds_per_block - 1 - i) * ring->rxd_size;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Note: memblock_item_idx is index of the item within
a23fd118e437af0a7877dd313db8fdaa3537c675yl * the memblock. For instance, in case of three RxD-blocks
a23fd118e437af0a7877dd313db8fdaa3537c675yl * per memblock this value can be 0,1 or 2. */
a23fd118e437af0a7877dd313db8fdaa3537c675yl rxdblock_priv =
8347601bcb0a439f6e50fc36b4039a73d08700e1yl __hal_mempool_item_priv((xge_hal_mempool_t *) mempoolh,
8347601bcb0a439f6e50fc36b4039a73d08700e1yl memblock_index, item,
8347601bcb0a439f6e50fc36b4039a73d08700e1yl &memblock_item_idx);
a23fd118e437af0a7877dd313db8fdaa3537c675yl rxdp = (xge_hal_ring_rxd_1_t *)
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->reserved_rxds_arr[reserve_index];
a23fd118e437af0a7877dd313db8fdaa3537c675yl rxd_priv = (xge_hal_ring_rxd_priv_t *) (void *)
a23fd118e437af0a7877dd313db8fdaa3537c675yl ((char*)rxdblock_priv + ring->rxd_priv_size * i);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* pre-format per-RxD Ring's private */
a23fd118e437af0a7877dd313db8fdaa3537c675yl rxd_priv->dma_offset = (char*)rxdp - (char*)memblock;
a23fd118e437af0a7877dd313db8fdaa3537c675yl rxd_priv->dma_addr = dma_object->addr + rxd_priv->dma_offset;
a23fd118e437af0a7877dd313db8fdaa3537c675yl rxd_priv->dma_handle = dma_object->handle;
a23fd118e437af0a7877dd313db8fdaa3537c675yl#ifdef XGE_DEBUG_ASSERT
a23fd118e437af0a7877dd313db8fdaa3537c675yl rxd_priv->dma_object = dma_object;
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* pre-format Host_Control */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined(XGE_HAL_USE_5B_MODE)
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (ring->buffer_mode == XGE_HAL_RING_QUEUE_BUFFER_MODE_5) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ring_rxd_5_t *rxdp_5 = (xge_hal_ring_rxd_5_t *)rxdp;
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined(XGE_OS_PLATFORM_64BIT)
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_assert(memblock_index <= 0xFFFF);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_assert(i <= 0xFFFF);
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* store memblock's index */
a23fd118e437af0a7877dd313db8fdaa3537c675yl rxdp_5->host_control = (u32)memblock_index << 16;
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* store index of memblock's private */
a23fd118e437af0a7877dd313db8fdaa3537c675yl rxdp_5->host_control |= (u32)(memblock_item_idx *
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->rxds_per_block + i);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#else
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* 32-bit case */
a23fd118e437af0a7877dd313db8fdaa3537c675yl rxdp_5->host_control = (u32)rxd_priv;
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl } else {
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* 1b and 3b modes */
a23fd118e437af0a7877dd313db8fdaa3537c675yl rxdp->host_control = (u64)(ulong_t)rxd_priv;
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl#else
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* 1b and 3b modes */
a23fd118e437af0a7877dd313db8fdaa3537c675yl rxdp->host_control = (u64)(ulong_t)rxd_priv;
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl __hal_ring_block_memblock_idx_set((xge_hal_ring_block_t *) item, memblock_index);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (is_last) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* link last one with first one */
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_ring_rxdblock_link(mempoolh, ring, 0, index);
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (index > 0 ) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* link this RxD block with previous one */
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_ring_rxdblock_link(mempoolh, ring, index, index-1);
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl return XGE_HAL_OK;
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_initial_replenish(xge_hal_channel_t *channel,
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_channel_reopen_e reopen)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
7eced415e5dd557aef2d78483b5a7785f0e13670xw xge_hal_dtr_h dtr = NULL;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl while (xge_hal_channel_dtr_count(channel) > 0) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_status_e status;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl status = xge_hal_ring_dtr_reserve(channel, &dtr);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_assert(status == XGE_HAL_OK);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (channel->dtr_init) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl status = channel->dtr_init(channel,
a23fd118e437af0a7877dd313db8fdaa3537c675yl dtr, channel->reserve_length,
a23fd118e437af0a7877dd313db8fdaa3537c675yl channel->userdata,
a23fd118e437af0a7877dd313db8fdaa3537c675yl reopen);
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (status != XGE_HAL_OK) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ring_dtr_free(channel, dtr);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_channel_abort(channel,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_CHANNEL_OC_NORMAL);
a23fd118e437af0a7877dd313db8fdaa3537c675yl return status;
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ring_dtr_post(channel, dtr);
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl return XGE_HAL_OK;
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_open(xge_hal_channel_h channelh, xge_hal_channel_attr_t *attr)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_status_e status;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_device_t *hldev;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ring_t *ring = (xge_hal_ring_t *)channelh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ring_queue_t *queue;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Note: at this point we have channel.devh and channel.pdev
a23fd118e437af0a7877dd313db8fdaa3537c675yl * pre-set only! */
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl hldev = (xge_hal_device_t *)ring->channel.devh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->config = &hldev->config.ring;
a23fd118e437af0a7877dd313db8fdaa3537c675yl queue = &ring->config->queue[attr->post_qid];
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->indicate_max_pkts = queue->indicate_max_pkts;
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->buffer_mode = queue->buffer_mode;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_assert(queue->configured);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined(XGE_HAL_RX_MULTI_RESERVE)
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_spin_lock_init(&ring->channel.reserve_lock, hldev->pdev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#elif defined(XGE_HAL_RX_MULTI_RESERVE_IRQ)
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_spin_lock_init_irq(&ring->channel.reserve_lock, hldev->irqh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined(XGE_HAL_RX_MULTI_POST)
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_spin_lock_init(&ring->channel.post_lock, hldev->pdev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#elif defined(XGE_HAL_RX_MULTI_POST_IRQ)
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_spin_lock_init_irq(&ring->channel.post_lock, hldev->irqh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->rxd_size = XGE_HAL_RING_RXD_SIZEOF(queue->buffer_mode);
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->rxd_priv_size =
a23fd118e437af0a7877dd313db8fdaa3537c675yl sizeof(xge_hal_ring_rxd_priv_t) + attr->per_dtr_space;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* how many RxDs can fit into one block. Depends on configured
a23fd118e437af0a7877dd313db8fdaa3537c675yl * buffer_mode. */
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->rxds_per_block = XGE_HAL_RING_RXDS_PER_BLOCK(queue->buffer_mode);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* calculate actual RxD block private size */
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl ring->reserved_rxds_arr = (void **) xge_os_malloc(ring->channel.pdev,
a23fd118e437af0a7877dd313db8fdaa3537c675yl sizeof(void*) * queue->max * ring->rxds_per_block);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (ring->reserved_rxds_arr == NULL) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_ring_close(channelh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl return XGE_HAL_ERR_OUT_OF_MEMORY;
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->mempool = __hal_mempool_create(
a23fd118e437af0a7877dd313db8fdaa3537c675yl hldev->pdev,
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->config->memblock_size,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_RING_RXDBLOCK_SIZE,
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->rxdblock_priv_size,
a23fd118e437af0a7877dd313db8fdaa3537c675yl queue->initial, queue->max,
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_ring_mempool_item_alloc,
a23fd118e437af0a7877dd313db8fdaa3537c675yl NULL, /* nothing to free */
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring);
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (ring->mempool == NULL) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_ring_close(channelh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl return XGE_HAL_ERR_OUT_OF_MEMORY;
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl status = __hal_channel_initialize(channelh,
a23fd118e437af0a7877dd313db8fdaa3537c675yl attr,
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->reserved_rxds_arr,
a23fd118e437af0a7877dd313db8fdaa3537c675yl queue->initial * ring->rxds_per_block,
a23fd118e437af0a7877dd313db8fdaa3537c675yl queue->max * ring->rxds_per_block,
a23fd118e437af0a7877dd313db8fdaa3537c675yl 0 /* no threshold for ring! */);
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (status != XGE_HAL_OK) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_ring_close(channelh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl return status;
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* sanity check that everything formatted ok */
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_assert(ring->reserved_rxds_arr[0] ==
a23fd118e437af0a7877dd313db8fdaa3537c675yl (char *)ring->mempool->items_arr[0] +
a23fd118e437af0a7877dd313db8fdaa3537c675yl (ring->rxds_per_block * ring->rxd_size - ring->rxd_size));
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Note:
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Specifying dtr_init callback means two things:
a23fd118e437af0a7877dd313db8fdaa3537c675yl * 1) dtrs need to be initialized by ULD at channel-open time;
a23fd118e437af0a7877dd313db8fdaa3537c675yl * 2) dtrs need to be posted at channel-open time
a23fd118e437af0a7877dd313db8fdaa3537c675yl * (that's what the initial_replenish() below does)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Currently we don't have a case when the 1) is done without the 2).
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (ring->channel.dtr_init) {
8347601bcb0a439f6e50fc36b4039a73d08700e1yl if ((status = __hal_ring_initial_replenish (
8347601bcb0a439f6e50fc36b4039a73d08700e1yl (xge_hal_channel_t *) channelh,
8347601bcb0a439f6e50fc36b4039a73d08700e1yl XGE_HAL_CHANNEL_OC_NORMAL) )
8347601bcb0a439f6e50fc36b4039a73d08700e1yl != XGE_HAL_OK) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_ring_close(channelh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl return status;
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl /* initial replenish will increment the counter in its post() routine,
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * we have to reset it */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl ring->channel.usage_cnt = 0;
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl return XGE_HAL_OK;
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_close(xge_hal_channel_h channelh)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ring_t *ring = (xge_hal_ring_t *)channelh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ring_queue_t *queue;
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined(XGE_HAL_RX_MULTI_RESERVE)||defined(XGE_HAL_RX_MULTI_RESERVE_IRQ)||\
a23fd118e437af0a7877dd313db8fdaa3537c675yl defined(XGE_HAL_RX_MULTI_POST) || defined(XGE_HAL_RX_MULTI_POST_IRQ)
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_device_t *hldev = (xge_hal_device_t *)ring->channel.devh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_assert(ring->channel.pdev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl queue = &ring->config->queue[ring->channel.post_qid];
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (ring->mempool) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_mempool_destroy(ring->mempool);
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (ring->reserved_rxds_arr) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_free(ring->channel.pdev,
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->reserved_rxds_arr,
a23fd118e437af0a7877dd313db8fdaa3537c675yl sizeof(void*) * queue->max * ring->rxds_per_block);
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_channel_terminate(channelh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined(XGE_HAL_RX_MULTI_RESERVE)
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_spin_lock_destroy(&ring->channel.reserve_lock, hldev->pdev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#elif defined(XGE_HAL_RX_MULTI_RESERVE_IRQ)
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_spin_lock_destroy_irq(&ring->channel.reserve_lock, hldev->pdev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined(XGE_HAL_RX_MULTI_POST)
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_spin_lock_destroy(&ring->channel.post_lock, hldev->pdev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#elif defined(XGE_HAL_RX_MULTI_POST_IRQ)
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_spin_lock_destroy_irq(&ring->channel.post_lock, hldev->pdev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_prc_enable(xge_hal_channel_h channelh)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ring_t *ring = (xge_hal_ring_t *)channelh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_device_t *hldev = (xge_hal_device_t *)ring->channel.devh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_pci_bar0_t *bar0;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u64 val64;
a23fd118e437af0a7877dd313db8fdaa3537c675yl void *first_block;
a23fd118e437af0a7877dd313db8fdaa3537c675yl int block_num;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ring_queue_t *queue;
a23fd118e437af0a7877dd313db8fdaa3537c675yl pci_dma_h dma_handle;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_assert(ring);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_assert(ring->channel.pdev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl bar0 = (xge_hal_pci_bar0_t *) (void *)
a23fd118e437af0a7877dd313db8fdaa3537c675yl ((xge_hal_device_t *)ring->channel.devh)->bar0;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl queue = &ring->config->queue[ring->channel.post_qid];
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_assert(queue->buffer_mode == 1 ||
a23fd118e437af0a7877dd313db8fdaa3537c675yl queue->buffer_mode == 3 ||
a23fd118e437af0a7877dd313db8fdaa3537c675yl queue->buffer_mode == 5);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* last block in fact becomes first. This is just the way it
a23fd118e437af0a7877dd313db8fdaa3537c675yl * is filled up and linked by item_alloc() */
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl block_num = queue->initial;
a23fd118e437af0a7877dd313db8fdaa3537c675yl first_block = __hal_mempool_item(ring->mempool, block_num - 1);
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 = __hal_ring_item_dma_addr(ring->mempool,
a23fd118e437af0a7877dd313db8fdaa3537c675yl first_block, &dma_handle);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0,
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64, &bar0->prc_rxd0_n[ring->channel.post_qid]);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl xge_debug_ring(XGE_TRACE, "ring%d PRC DMA addr 0x"XGE_OS_LLXFMT" initialized",
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->channel.post_qid, (unsigned long long)val64);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 = xge_os_pio_mem_read64(ring->channel.pdev,
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->channel.regh0, &bar0->prc_ctrl_n[ring->channel.post_qid]);
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC &&
a23fd118e437af0a7877dd313db8fdaa3537c675yl !queue->rth_en) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= XGE_HAL_PRC_CTRL_RTH_DISABLE;
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= XGE_HAL_PRC_CTRL_RC_ENABLED;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= vBIT((queue->buffer_mode >> 1),14,2);/* 1,3 or 5 => 0,1 or 2 */
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 &= ~XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(
a23fd118e437af0a7877dd313db8fdaa3537c675yl (hldev->config.pci_freq_mherz * queue->backoff_interval_us));
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Beware: no snoop by the bridge if (no_snoop_bits) */
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= XGE_HAL_PRC_CTRL_NO_SNOOP(queue->no_snoop_bits);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Herc: always use group_reads */
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC)
8347601bcb0a439f6e50fc36b4039a73d08700e1yl val64 |= XGE_HAL_PRC_CTRL_GROUP_READS;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl if (hldev->config.bimodal_interrupts)
8347601bcb0a439f6e50fc36b4039a73d08700e1yl if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC)
8347601bcb0a439f6e50fc36b4039a73d08700e1yl val64 |= XGE_HAL_PRC_CTRL_BIMODAL_INTERRUPT;
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0,
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64, &bar0->prc_ctrl_n[ring->channel.post_qid]);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Configure Receive Protocol Assist */
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 = xge_os_pio_mem_read64(ring->channel.pdev,
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->channel.regh0, &bar0->rx_pa_cfg);
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= XGE_HAL_RX_PA_CFG_SCATTER_MODE(ring->config->scatter_mode);
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= (XGE_HAL_RX_PA_CFG_IGNORE_SNAP_OUI | XGE_HAL_RX_PA_CFG_IGNORE_LLC_CTRL);
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Clean STRIP_VLAN_TAG bit and set as config from upper layer */
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 &= ~XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(1);
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(ring->config->strip_vlan_tag);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0,
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64, &bar0->rx_pa_cfg);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_debug_ring(XGE_TRACE, "ring%d enabled in buffer_mode %d",
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->channel.post_qid, queue->buffer_mode);
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_prc_disable(xge_hal_channel_h channelh)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ring_t *ring = (xge_hal_ring_t *)channelh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_pci_bar0_t *bar0;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u64 val64;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_assert(ring);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_assert(ring->channel.pdev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl bar0 = (xge_hal_pci_bar0_t *) (void *)
a23fd118e437af0a7877dd313db8fdaa3537c675yl ((xge_hal_device_t *)ring->channel.devh)->bar0;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 = xge_os_pio_mem_read64(ring->channel.pdev,
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->channel.regh0,
a23fd118e437af0a7877dd313db8fdaa3537c675yl &bar0->prc_ctrl_n[ring->channel.post_qid]);
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 &= ~((u64) XGE_HAL_PRC_CTRL_RC_ENABLED);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0,
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64, &bar0->prc_ctrl_n[ring->channel.post_qid]);
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_hw_initialize(xge_hal_device_h devh)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_device_t *hldev = (xge_hal_device_t *)devh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u64 val64;
a23fd118e437af0a7877dd313db8fdaa3537c675yl int i, j;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Rx DMA intialization. */
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 = 0;
a23fd118e437af0a7877dd313db8fdaa3537c675yl for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (!hldev->config.ring.queue[i].configured)
a23fd118e437af0a7877dd313db8fdaa3537c675yl continue;
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= vBIT(hldev->config.ring.queue[i].priority,
a23fd118e437af0a7877dd313db8fdaa3537c675yl (5 + (i * 8)), 3);
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
a23fd118e437af0a7877dd313db8fdaa3537c675yl &bar0->rx_queue_priority);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl xge_debug_ring(XGE_TRACE, "Rings priority configured to 0x"XGE_OS_LLXFMT,
a23fd118e437af0a7877dd313db8fdaa3537c675yl (unsigned long long)val64);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Configuring ring queues according to per-ring configuration */
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 = 0;
a23fd118e437af0a7877dd313db8fdaa3537c675yl for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (!hldev->config.ring.queue[i].configured)
a23fd118e437af0a7877dd313db8fdaa3537c675yl continue;
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= vBIT(hldev->config.ring.queue[i].dram_size_mb,(i*8),8);
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
a23fd118e437af0a7877dd313db8fdaa3537c675yl &bar0->rx_queue_cfg);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl xge_debug_ring(XGE_TRACE, "DRAM configured to 0x"XGE_OS_LLXFMT,
a23fd118e437af0a7877dd313db8fdaa3537c675yl (unsigned long long)val64);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
7eced415e5dd557aef2d78483b5a7785f0e13670xw if (!hldev->config.rts_qos_en &&
7eced415e5dd557aef2d78483b5a7785f0e13670xw !hldev->config.rts_port_en &&
7eced415e5dd557aef2d78483b5a7785f0e13670xw !hldev->config.rts_mac_en) {
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xw /*
7eced415e5dd557aef2d78483b5a7785f0e13670xw * Activate default (QoS-based) Rx steering
7eced415e5dd557aef2d78483b5a7785f0e13670xw */
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xw val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
7eced415e5dd557aef2d78483b5a7785f0e13670xw &bar0->rts_qos_steering);
7eced415e5dd557aef2d78483b5a7785f0e13670xw for (j = 0; j < 8 /* QoS max */; j++)
7eced415e5dd557aef2d78483b5a7785f0e13670xw {
7eced415e5dd557aef2d78483b5a7785f0e13670xw for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++)
7eced415e5dd557aef2d78483b5a7785f0e13670xw {
7eced415e5dd557aef2d78483b5a7785f0e13670xw if (!hldev->config.ring.queue[i].configured)
7eced415e5dd557aef2d78483b5a7785f0e13670xw continue;
7eced415e5dd557aef2d78483b5a7785f0e13670xw if (!hldev->config.ring.queue[i].rth_en)
7eced415e5dd557aef2d78483b5a7785f0e13670xw val64 |= (BIT(i) >> (j*8));
7eced415e5dd557aef2d78483b5a7785f0e13670xw }
7eced415e5dd557aef2d78483b5a7785f0e13670xw }
7eced415e5dd557aef2d78483b5a7785f0e13670xw xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
7eced415e5dd557aef2d78483b5a7785f0e13670xw &bar0->rts_qos_steering);
7eced415e5dd557aef2d78483b5a7785f0e13670xw xge_debug_ring(XGE_TRACE, "QoS steering configured to 0x"XGE_OS_LLXFMT,
7eced415e5dd557aef2d78483b5a7785f0e13670xw (unsigned long long)val64);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xw }
7eced415e5dd557aef2d78483b5a7785f0e13670xw
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Note: If a queue does not exist, it should be assigned a maximum
a23fd118e437af0a7877dd313db8fdaa3537c675yl * length of zero. Otherwise, packet loss could occur.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * P. 4-4 User guide.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * All configured rings will be properly set at device open time
a23fd118e437af0a7877dd313db8fdaa3537c675yl * by utilizing device_mtu_set() API call. */
a23fd118e437af0a7877dd313db8fdaa3537c675yl for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (hldev->config.ring.queue[i].configured)
a23fd118e437af0a7877dd313db8fdaa3537c675yl continue;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0ULL,
a23fd118e437af0a7877dd313db8fdaa3537c675yl &bar0->rts_frm_len_n[i]);
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#ifdef XGE_HAL_HERC_EMULATION
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
a23fd118e437af0a7877dd313db8fdaa3537c675yl ((u8 *)bar0 + 0x2e60)); /* mc_rldram_mrs_herc */
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= 0x0000000000010000;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
a23fd118e437af0a7877dd313db8fdaa3537c675yl ((u8 *)bar0 + 0x2e60));
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= 0x003a000000000000;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
a23fd118e437af0a7877dd313db8fdaa3537c675yl ((u8 *)bar0 + 0x2e40)); /* mc_rldram_ref_herc */
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_mdelay(2000);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* now enabling MC-RLDRAM after setting MC_QUEUE sizes */
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
a23fd118e437af0a7877dd313db8fdaa3537c675yl &bar0->mc_rldram_mrs);
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= XGE_HAL_MC_RLDRAM_QUEUE_SIZE_ENABLE |
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_MC_RLDRAM_MRS_ENABLE;
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, (u32)(val64>>32),
a23fd118e437af0a7877dd313db8fdaa3537c675yl &bar0->mc_rldram_mrs);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_wmb();
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_pio_mem_write32_lower(hldev->pdev, hldev->regh0, (u32)val64,
a23fd118e437af0a7877dd313db8fdaa3537c675yl &bar0->mc_rldram_mrs);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* RLDRAM initialization procedure require 500us to complete */
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_mdelay(1);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Temporary fixes for Herc RLDRAM */
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 = XGE_HAL_MC_RLDRAM_SET_REF_PERIOD(0x0279);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
a23fd118e437af0a7877dd313db8fdaa3537c675yl &bar0->mc_rldram_ref_per_herc);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
a23fd118e437af0a7877dd313db8fdaa3537c675yl &bar0->mc_rldram_mrs_herc);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl xge_debug_ring(XGE_TRACE, "default mc_rldram_mrs_herc 0x"XGE_OS_LLXFMT,
a23fd118e437af0a7877dd313db8fdaa3537c675yl (unsigned long long)val64);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 = 0x0003570003010300ULL;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
a23fd118e437af0a7877dd313db8fdaa3537c675yl &bar0->mc_rldram_mrs_herc);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_mdelay(1);
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xw if (hldev->config.intr_mode != XGE_HAL_INTR_MODE_MSIX)
7eced415e5dd557aef2d78483b5a7785f0e13670xw return;
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xw /*
7eced415e5dd557aef2d78483b5a7785f0e13670xw * Assign MSI-X vectors
7eced415e5dd557aef2d78483b5a7785f0e13670xw */
7eced415e5dd557aef2d78483b5a7785f0e13670xw for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
7eced415e5dd557aef2d78483b5a7785f0e13670xw xge_list_t *item;
7eced415e5dd557aef2d78483b5a7785f0e13670xw xge_hal_channel_t *channel = NULL;
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xw if (!hldev->config.ring.queue[i].configured ||
7eced415e5dd557aef2d78483b5a7785f0e13670xw !hldev->config.ring.queue[i].intr_vector)
7eced415e5dd557aef2d78483b5a7785f0e13670xw continue;
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xw /* find channel */
7eced415e5dd557aef2d78483b5a7785f0e13670xw xge_list_for_each(item, &hldev->free_channels) {
7eced415e5dd557aef2d78483b5a7785f0e13670xw xge_hal_channel_t *tmp;
7eced415e5dd557aef2d78483b5a7785f0e13670xw tmp = xge_container_of(item, xge_hal_channel_t,
7eced415e5dd557aef2d78483b5a7785f0e13670xw item);
7eced415e5dd557aef2d78483b5a7785f0e13670xw if (tmp->type == XGE_HAL_CHANNEL_TYPE_RING &&
7eced415e5dd557aef2d78483b5a7785f0e13670xw tmp->post_qid == i) {
7eced415e5dd557aef2d78483b5a7785f0e13670xw channel = tmp;
7eced415e5dd557aef2d78483b5a7785f0e13670xw break;
7eced415e5dd557aef2d78483b5a7785f0e13670xw }
7eced415e5dd557aef2d78483b5a7785f0e13670xw }
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xw if (channel) {
7eced415e5dd557aef2d78483b5a7785f0e13670xw (void) xge_hal_channel_msix_set(channel,
7eced415e5dd557aef2d78483b5a7785f0e13670xw hldev->config.ring.queue[i].intr_vector);
7eced415e5dd557aef2d78483b5a7785f0e13670xw }
7eced415e5dd557aef2d78483b5a7785f0e13670xw }
7eced415e5dd557aef2d78483b5a7785f0e13670xw
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_debug_ring(XGE_TRACE, "%s", "ring channels initialized");
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_mtu_set(xge_hal_device_h devh, int new_frmlen)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl int i;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_device_t *hldev = (xge_hal_device_t *)devh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (!hldev->config.ring.queue[i].configured)
a23fd118e437af0a7877dd313db8fdaa3537c675yl continue;
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (hldev->config.ring.queue[i].max_frm_len !=
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_RING_USE_MTU) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_MAC_RTS_FRM_LEN_SET(
a23fd118e437af0a7877dd313db8fdaa3537c675yl hldev->config.ring.queue[i].max_frm_len),
a23fd118e437af0a7877dd313db8fdaa3537c675yl &bar0->rts_frm_len_n[i]);
a23fd118e437af0a7877dd313db8fdaa3537c675yl } else {
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_MAC_RTS_FRM_LEN_SET(new_frmlen),
a23fd118e437af0a7877dd313db8fdaa3537c675yl &bar0->rts_frm_len_n[i]);
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_RMAC_MAX_PYLD_LEN(new_frmlen),
a23fd118e437af0a7877dd313db8fdaa3537c675yl &bar0->rmac_max_pyld_len);
a23fd118e437af0a7877dd313db8fdaa3537c675yl}