em.h revision c1d279fc0865b91a40b30eda02ed14f6533fe1a4
0N/A/** @file
0N/A * EM - Execution Monitor.
0N/A */
0N/A
0N/A/*
0N/A * Copyright (C) 2006-2015 Oracle Corporation
0N/A *
0N/A * This file is part of VirtualBox Open Source Edition (OSE), as
6983N/A * available from http://www.virtualbox.org. This file is free software;
6983N/A * you can redistribute it and/or modify it under the terms of the GNU
0N/A * General Public License (GPL) as published by the Free Software
0N/A * Foundation, in version 2 as it comes in the "COPYING" file of the
0N/A * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
0N/A * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
6983N/A *
6983N/A * The contents of this file may alternatively be used under the terms
6983N/A * of the Common Development and Distribution License Version 1.0
6983N/A * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
0N/A * VirtualBox OSE distribution, in which case the provisions of the
0N/A * CDDL are applicable instead of those of the GPL.
0N/A *
0N/A * You may elect to license modified versions of this file under the
0N/A * terms and conditions of either the GPL or the CDDL or both.
3220N/A */
6719N/A
0N/A#ifndef ___VBox_vmm_em_h
0N/A#define ___VBox_vmm_em_h
0N/A
0N/A#include <VBox/types.h>
0N/A#include <VBox/vmm/trpm.h>
0N/A
6967N/A
2086N/ART_C_DECLS_BEGIN
6967N/A
6967N/A/** @defgroup grp_em The Execution Monitor / Manager API
0N/A * @{
0N/A */
0N/A
0N/A/** Enable to allow V86 code to run in raw mode. */
0N/A#define VBOX_RAW_V86
0N/A
0N/A/**
0N/A * The Execution Manager State.
0N/A *
6967N/A * @remarks This is used in the saved state!
6967N/A */
6967N/Atypedef enum EMSTATE
0N/A{
0N/A /** Not yet started. */
6967N/A EMSTATE_NONE = 1,
6967N/A /** Raw-mode execution. */
6967N/A EMSTATE_RAW,
6967N/A /** Hardware accelerated raw-mode execution. */
0N/A EMSTATE_HM,
0N/A /** Executing in IEM. */
6967N/A EMSTATE_IEM,
6967N/A /** Recompiled mode execution. */
6967N/A EMSTATE_REM,
6967N/A /** Execution is halted. (waiting for interrupt) */
0N/A EMSTATE_HALTED,
0N/A /** Application processor execution is halted. (waiting for startup IPI (SIPI)) */
6967N/A EMSTATE_WAIT_SIPI,
0N/A /** Execution is suspended. */
0N/A EMSTATE_SUSPENDED,
6967N/A /** The VM is terminating. */
0N/A EMSTATE_TERMINATING,
0N/A /** Guest debug event from raw-mode is being processed. */
6967N/A EMSTATE_DEBUG_GUEST_RAW,
0N/A /** Guest debug event from hardware accelerated mode is being processed. */
0N/A EMSTATE_DEBUG_GUEST_HM,
6967N/A /** Guest debug event from interpreted execution mode is being processed. */
2086N/A EMSTATE_DEBUG_GUEST_IEM,
0N/A /** Guest debug event from recompiled-mode is being processed. */
6970N/A EMSTATE_DEBUG_GUEST_REM,
0N/A /** Hypervisor debug event being processed. */
0N/A EMSTATE_DEBUG_HYPER,
6967N/A /** The VM has encountered a fatal error. (And everyone is panicing....) */
0N/A EMSTATE_GURU_MEDITATION,
0N/A /** Executing in IEM, falling back on REM if we cannot switch back to HM or
6967N/A * RAW after a short while. */
0N/A EMSTATE_IEM_THEN_REM,
0N/A /** Just a hack to ensure that we get a 32-bit integer. */
6967N/A EMSTATE_MAKE_32BIT_HACK = 0x7fffffff
0N/A} EMSTATE;
0N/A
6967N/A
0N/A/**
0N/A * EMInterpretInstructionCPU execution modes.
6967N/A */
6967N/Atypedef enum
6970N/A{
6970N/A /** Only supervisor code (CPL=0). */
6967N/A EMCODETYPE_SUPERVISOR,
3220N/A /** User-level code only. */
0N/A EMCODETYPE_USER,
6967N/A /** Supervisor and user-level code (use with great care!). */
6967N/A EMCODETYPE_ALL,
6967N/A /** Just a hack to ensure that we get a 32-bit integer. */
6967N/A EMCODETYPE_32BIT_HACK = 0x7fffffff
2607N/A} EMCODETYPE;
0N/A
0N/AVMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu);
0N/AVMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState);
0N/A
0N/A/** @name Callback handlers for instruction emulation functions.
0N/A * These are placed here because IOM wants to use them as well.
0N/A * @{
0N/A */
0N/Atypedef DECLCALLBACK(uint32_t) FNEMULATEPARAM2UINT32(void *pvParam1, uint64_t val2);
0N/Atypedef FNEMULATEPARAM2UINT32 *PFNEMULATEPARAM2UINT32;
0N/Atypedef DECLCALLBACK(uint32_t) FNEMULATEPARAM2(void *pvParam1, size_t val2);
0N/Atypedef FNEMULATEPARAM2 *PFNEMULATEPARAM2;
0N/Atypedef DECLCALLBACK(uint32_t) FNEMULATEPARAM3(void *pvParam1, uint64_t val2, size_t val3);
0N/Atypedef FNEMULATEPARAM3 *PFNEMULATEPARAM3;
0N/Atypedef DECLCALLBACK(int) FNEMULATELOCKPARAM2(void *pvParam1, uint64_t val2, RTGCUINTREG32 *pf);
0N/Atypedef FNEMULATELOCKPARAM2 *PFNEMULATELOCKPARAM2;
0N/Atypedef DECLCALLBACK(int) FNEMULATELOCKPARAM3(void *pvParam1, uint64_t val2, size_t cb, RTGCUINTREG32 *pf);
0N/Atypedef FNEMULATELOCKPARAM3 *PFNEMULATELOCKPARAM3;
0N/A/** @} */
0N/A
0N/A
0N/A/**
0N/A * Checks if raw ring-3 execute mode is enabled.
0N/A *
0N/A * @returns true if enabled.
0N/A * @returns false if disabled.
0N/A * @param pVM The VM to operate on.
2086N/A */
0N/A#define EMIsRawRing3Enabled(pVM) (!(pVM)->fRecompileUser)
0N/A
0N/A/**
0N/A * Checks if raw ring-0 execute mode is enabled.
0N/A *
0N/A * @returns true if enabled.
0N/A * @returns false if disabled.
0N/A * @param pVM The VM to operate on.
3220N/A */
2086N/A#define EMIsRawRing0Enabled(pVM) (!(pVM)->fRecompileSupervisor)
2086N/A
0N/A#ifdef VBOX_WITH_RAW_RING1
0N/A/**
0N/A * Checks if raw ring-1 execute mode is enabled.
0N/A *
0N/A * @returns true if enabled.
0N/A * @returns false if disabled.
0N/A * @param pVM The VM to operate on.
0N/A */
0N/A# define EMIsRawRing1Enabled(pVM) ((pVM)->fRawRing1Enabled)
0N/A#else
0N/A# define EMIsRawRing1Enabled(pVM) false
2086N/A#endif
2607N/A
0N/A/**
6967N/A * Checks if execution with hardware assisted virtualization is enabled.
0N/A *
2086N/A * @returns true if enabled.
2086N/A * @returns false if disabled.
0N/A * @param pVM The VM to operate on.
0N/A */
6967N/A#define EMIsHwVirtExecutionEnabled(pVM) (!(pVM)->fRecompileSupervisor && !(pVM)->fRecompileUser)
0N/A
2086N/A/**
2086N/A * Checks if execution of supervisor code should be done in the
0N/A * recompiler or not.
0N/A *
0N/A * @returns true if enabled.
0N/A * @returns false if disabled.
0N/A * @param pVM The VM to operate on.
0N/A */
0N/A#define EMIsSupervisorCodeRecompiled(pVM) ((pVM)->fRecompileSupervisor)
0N/A
0N/AVMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC);
0N/AVMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu);
0N/AVMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pCpu, unsigned *pcbInstr);
0N/AVMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
0N/A PDISCPUSTATE pDISState, unsigned *pcbInstr);
0N/AVMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pCoreCtx, RTGCPTR pvFault);
0N/AVMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten);
0N/AVMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pCoreCtx,
0N/A RTGCPTR pvFault, EMCODETYPE enmCodeType);
0N/A
0N/A#ifdef IN_RC
0N/AVMM_INT_DECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
0N/A#endif
0N/A
0N/AVMM_INT_DECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
0N/AVMM_INT_DECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
0N/AVMM_INT_DECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
0N/AVMM_INT_DECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
0N/AVMM_INT_DECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC);
0N/AVMM_INT_DECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
0N/AVMM_INT_DECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
0N/AVMM_INT_DECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen);
0N/AVMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx);
0N/AVMM_INT_DECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen);
0N/AVMM_INT_DECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx);
0N/AVMM_INT_DECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data);
0N/AVMM_INT_DECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu);
0N/AVMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
0N/AVMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
0N/AVMM_INT_DECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx);
0N/AVMM_INT_DECL(bool) EMMonitorWaitShouldContinue(PVMCPU pVCpu, PCPUMCTX pCtx);
0N/AVMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx, RTGCPHYS GCPhys);
0N/AVMM_INT_DECL(int) EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx);
0N/A
0N/A/** @name Assembly routines
0N/A * @{ */
0N/AVMMDECL(uint32_t) EMEmulateCmp(uint32_t u32Param1, uint64_t u64Param2, size_t cb);
0N/AVMMDECL(uint32_t) EMEmulateAnd(void *pvParam1, uint64_t u64Param2, size_t cb);
0N/AVMMDECL(uint32_t) EMEmulateInc(void *pvParam1, size_t cb);
0N/AVMMDECL(uint32_t) EMEmulateDec(void *pvParam1, size_t cb);
0N/AVMMDECL(uint32_t) EMEmulateOr(void *pvParam1, uint64_t u64Param2, size_t cb);
0N/AVMMDECL(int) EMEmulateLockOr(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
0N/AVMMDECL(uint32_t) EMEmulateXor(void *pvParam1, uint64_t u64Param2, size_t cb);
0N/AVMMDECL(int) EMEmulateLockXor(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
0N/AVMMDECL(uint32_t) EMEmulateAdd(void *pvParam1, uint64_t u64Param2, size_t cb);
0N/AVMMDECL(int) EMEmulateLockAnd(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
0N/AVMMDECL(uint32_t) EMEmulateSub(void *pvParam1, uint64_t u64Param2, size_t cb);
0N/AVMMDECL(uint32_t) EMEmulateAdcWithCarrySet(void *pvParam1, uint64_t u64Param2, size_t cb);
0N/AVMMDECL(uint32_t) EMEmulateBtr(void *pvParam1, uint64_t u64Param2);
0N/AVMMDECL(int) EMEmulateLockBtr(void *pvParam1, uint64_t u64Param2, RTGCUINTREG32 *pf);
0N/AVMMDECL(uint32_t) EMEmulateBts(void *pvParam1, uint64_t u64Param2);
0N/AVMMDECL(uint32_t) EMEmulateBtc(void *pvParam1, uint64_t u64Param2);
0N/AVMMDECL(uint32_t) EMEmulateCmpXchg(void *pvParam1, uint64_t *pu32Param2, uint64_t u32Param3, size_t cbSize);
0N/AVMMDECL(uint32_t) EMEmulateLockCmpXchg(void *pvParam1, uint64_t *pu64Param2, uint64_t u64Param3, size_t cbSize);
0N/AVMMDECL(uint32_t) EMEmulateCmpXchg8b(void *pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
0N/AVMMDECL(uint32_t) EMEmulateLockCmpXchg8b(void *pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
0N/AVMMDECL(uint32_t) EMEmulateXAdd(void *pvParam1, void *pvParam2, size_t cbOp);
0N/AVMMDECL(uint32_t) EMEmulateLockXAdd(void *pvParam1, void *pvParam2, size_t cbOp);
0N/A/** @} */
0N/A
0N/A/** @name REM locking routines
0N/A * @{ */
0N/AVMMDECL(void) EMRemUnlock(PVM pVM);
0N/AVMMDECL(void) EMRemLock(PVM pVM);
0N/AVMMDECL(bool) EMRemIsLockOwner(PVM pVM);
0N/AVMM_INT_DECL(int) EMRemTryLock(PVM pVM);
0N/A/** @} */
0N/A
0N/A
0N/A/** @name EM_ONE_INS_FLAGS_XXX - flags for EMR3HmSingleInstruction (et al).
0N/A * @{ */
0N/A/** Return when CS:RIP changes or some other important event happens.
0N/A * This means running whole REP and LOOP $ sequences for instance. */
0N/A#define EM_ONE_INS_FLAGS_RIP_CHANGE RT_BIT_32(0)
0N/A/** Mask of valid flags. */
0N/A#define EM_ONE_INS_FLAGS_MASK UINT32_C(0x00000001)
0N/A/** @} */
0N/A
0N/A
0N/A#ifdef IN_RING3
0N/A/** @defgroup grp_em_r3 The EM Host Context Ring-3 API
0N/A * @{
0N/A */
0N/A
0N/A/**
0N/A * Command argument for EMR3RawSetMode().
0N/A *
0N/A * It's possible to extend this interface to change several
0N/A * execution modes at once should the need arise.
0N/A */
0N/Atypedef enum EMEXECPOLICY
0N/A{
0N/A /** The customary invalid zero entry. */
0N/A EMEXECPOLICY_INVALID = 0,
0N/A /** Whether to recompile ring-0 code or execute it in raw/hm. */
0N/A EMEXECPOLICY_RECOMPILE_RING0,
0N/A /** Whether to recompile ring-3 code or execute it in raw/hm. */
0N/A EMEXECPOLICY_RECOMPILE_RING3,
0N/A /** Whether to only use IEM for execution. */
0N/A EMEXECPOLICY_IEM_ALL,
0N/A /** End of valid value (not included). */
0N/A EMEXECPOLICY_END,
0N/A /** The customary 32-bit type blowup. */
0N/A EMEXECPOLICY_32BIT_HACK = 0x7fffffff
0N/A} EMEXECPOLICY;
0N/AVMMR3DECL(int) EMR3SetExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool fEnforce);
0N/AVMMR3DECL(int) EMR3QueryExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool *pfEnforced);
0N/A
0N/AVMMR3_INT_DECL(int) EMR3Init(PVM pVM);
0N/AVMMR3_INT_DECL(void) EMR3Relocate(PVM pVM);
0N/AVMMR3_INT_DECL(void) EMR3ResetCpu(PVMCPU pVCpu);
0N/AVMMR3_INT_DECL(void) EMR3Reset(PVM pVM);
0N/AVMMR3_INT_DECL(int) EMR3Term(PVM pVM);
0N/AVMMR3DECL(DECLNORETURN(void)) EMR3FatalError(PVMCPU pVCpu, int rc);
0N/AVMMR3_INT_DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu);
0N/AVMMR3_INT_DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu);
0N/AVMMR3_INT_DECL(int) EMR3NotifyResume(PVM pVM);
0N/AVMMR3_INT_DECL(int) EMR3NotifySuspend(PVM pVM);
0N/AVMMR3_INT_DECL(VBOXSTRICTRC) EMR3HmSingleInstruction(PVM pVM, PVMCPU pVCpu, uint32_t fFlags);
0N/A
0N/A/** @} */
0N/A#endif /* IN_RING3 */
0N/A
0N/A/** @} */
0N/A
0N/ART_C_DECLS_END
0N/A
0N/A#endif
0N/A
0N/A