SELMInternal.h revision 26f38400c03761b1934b05fa93a64188e88e9904
/* $Id$ */
/** @file
* SELM - Internal header file.
*/
/*
* Copyright (C) 2006-2007 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
#ifndef ___SELMInternal_h
#define ___SELMInternal_h
/** @defgroup grp_selm_int Internals
* @ingroup grp_selm
* @internal
* @{
*/
/** The number of GDTS allocated for our GDT. (full size) */
#define SELM_GDT_ELEMENTS 8192
/** aHyperSel index to retrieve hypervisor selectors */
/** The Flat CS selector used by the VMM inside the GC. */
#define SELM_HYPER_SEL_CS 0
/** The Flat DS selector used by the VMM inside the GC. */
#define SELM_HYPER_SEL_DS 1
/** The 64-bit mode CS selector used by the VMM inside the GC. */
#define SELM_HYPER_SEL_CS64 2
/** The TSS selector used by the VMM inside the GC. */
#define SELM_HYPER_SEL_TSS 3
/** The TSS selector for taking trap 08 (\#DF). */
#define SELM_HYPER_SEL_TSS_TRAP08 4
/** Number of GDTs we need for internal use */
/** Default GDT selectors we use for the hypervisor. */
/** The lowest value default we use. */
/**
* Converts a SELM pointer into a VM pointer.
* @returns Pointer to the VM structure the SELM is part of.
* @param pSELM Pointer to SELM instance data.
*/
/**
* SELM Data (part of VM)
*/
typedef struct SELM
{
/** Offset to the VM structure.
* See SELM2VM(). */
/** Flat CS, DS, 64 bit mode CS, TSS & trap 8 TSS. */
/** Pointer to the GCs - R3 Ptr.
* This size is governed by SELM_GDT_ELEMENTS. */
/** Pointer to the GCs - RC Ptr.
* This is not initialized until the first relocation because it's used to
* check if the shadow GDT virtual handler requires deregistration. */
/** Current (last) Guest's GDTR.
* The pGdt member is set to RTRCPTR_MAX if we're not monitoring the guest GDT. */
/** The current (last) effective Guest GDT size. */
/** R3 pointer to the LDT shadow area in HMA. */
/** RC pointer to the LDT shadow area in HMA. */
#if GC_ARCH_BITS == 64
#endif
/** The address of the guest LDT.
* RTRCPTR_MAX if not monitored. */
/** Current LDT limit, both Guest and Shadow. */
#endif
/** TSS. (This is 16 byte aligned!)
* @todo I/O bitmap & interrupt redirection table? */
/** TSS for trap 08 (\#DF). */
/** Monitored shadow TSS address. */
RCPTRTYPE(void *) pvMonShwTssRC;
#if GC_ARCH_BITS == 64
#endif
/** GC Pointer to the current Guest's TSS.
* RTRCPTR_MAX if not monitored. */
/** The size of the guest TSS. */
/** Set if it's a 32-bit TSS. */
bool fGuestTss32Bit;
/** The size of the Guest's TSS part we're monitoring. */
/** The guest TSS selector at last sync (part of monitoring).
* Contains RTSEL_MAX if not set. */
/** The last known offset of the I/O bitmap.
* This is only used if we monitor the bitmap. */
/** Indicates that the Guest GDT access handler have been registered. */
bool fGDTRangeRegistered;
bool fDisableMonitoring;
/** Indicates whether the TSS stack selector & base address need to be refreshed. */
bool fSyncTSSRing0Stack;
/** SELMR3UpdateFromCPUM() profiling. */
/** SELMR3SyncTSS() profiling. */
/** GC: The number of handled writes to the Guest's GDT. */
/** GC: The number of unhandled write to the Guest's GDT. */
/** GC: The number of times writes to Guest's LDT was detected. */
/** GC: The number of handled writes to the Guest's TSS. */
/** GC: The number of handled writes to the Guest's TSS where we detected a change. */
/** GC: The number of handled redir writes to the Guest's TSS where we detected a change. */
/** GC: The number of unhandled writes to the Guest's TSS. */
/** The number of times we had to relocate our hypervisor selectors. */
/** The number of times we had find free hypervisor selectors. */
/** Counts the times we detected state selectors in SELMR3UpdateFromCPUM. */
/** Counts the times we were called with already state selectors in
* SELMR3UpdateFromCPUM. */
/** Counts the times we found a stale selector becomming valid again. */
#ifdef VBOX_WITH_STATISTICS
/** Times we updated hidden selector registers in CPUMR3UpdateFromCPUM. */
#endif
VMMRCDECL(int) selmRCGuestGDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange);
VMMRCDECL(int) selmRCGuestLDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange);
VMMRCDECL(int) selmRCGuestTSSWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange);
VMMRCDECL(int) selmRCShadowGDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange);
VMMRCDECL(int) selmRCShadowLDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange);
VMMRCDECL(int) selmRCShadowTSSWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange);
#ifdef VBOX_WITH_RAW_MODE_NOT_R0
/**
* Checks if a shadow descriptor table entry is good for the given segment
* register.
*
* @returns @c true if good, @c false if not.
* @param pSReg The segment register.
* @param pShwDesc The shadow descriptor table entry.
* @param iSReg The segment register index (X86_SREG_XXX).
* @param uCpl The CPL.
*/
DECLINLINE(bool) selmIsShwDescGoodForSReg(PCCPUMSELREG pSReg, PCX86DESC pShwDesc, uint32_t iSReg, uint32_t uCpl)
{
/*
* See iemMiscValidateNewSS, iemCImpl_LoadSReg and intel+amd manuals.
*/
{
Log(("selmIsShwDescGoodForSReg: Not present\n"));
return false;
}
{
Log(("selmIsShwDescGoodForSReg: System descriptor\n"));
return false;
}
if (iSReg == X86_SREG_SS)
{
{
Log(("selmIsShwDescGoodForSReg: Stack must be writable\n"));
return false;
}
{
Log(("selmIsShwDescGoodForSReg: CPL(%d) > DPL(%d)\n", uCpl, pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available));
return false;
}
}
else
{
if (iSReg == X86_SREG_CS)
{
{
Log(("selmIsShwDescGoodForSReg: CS needs code segment\n"));
return false;
}
}
{
return false;
}
{
return false;
}
}
return true;
}
/**
* Checks if a guest descriptor table entry is good for the given segment
* register.
*
* @returns @c true if good, @c false if not.
* @param pVCpu The current virtual CPU.
* @param pSReg The segment register.
* @param pGstDesc The guest descriptor table entry.
* @param iSReg The segment register index (X86_SREG_XXX).
* @param uCpl The CPL.
*/
DECLINLINE(bool) selmIsGstDescGoodForSReg(PVMCPU pVCpu, PCCPUMSELREG pSReg, PCX86DESC pGstDesc, uint32_t iSReg, uint32_t uCpl)
{
/*
* See iemMiscValidateNewSS, iemCImpl_LoadSReg and intel+amd manuals.
*/
{
Log(("selmIsGstDescGoodForSReg: Not present\n"));
return false;
}
{
Log(("selmIsGstDescGoodForSReg: System descriptor\n"));
return false;
}
if (iSReg == X86_SREG_SS)
{
{
Log(("selmIsGstDescGoodForSReg: Stack must be writable\n"));
return false;
}
{
return false;
}
}
else
{
if (iSReg == X86_SREG_CS)
{
{
Log(("selmIsGstDescGoodForSReg: CS needs code segment\n"));
return false;
}
}
{
return false;
}
|| !CPUMIsGuestInRawMode(pVCpu) ) )
)
)
{
return false;
}
}
return true;
}
/**
* Converts a guest GDT or LDT entry to a shadow table entry.
*
* @param pDesc Guest entry on input, shadow entry on return.
*/
{
/*
* Code and data selectors are generally 1:1, with the
* 'little' adjustment we do for DPL 0 selectors.
*/
{
/*
* Hack for A-bit against Trap E on read-only GDT.
*/
/** @todo Fix this by loading ds and cs before turning off WP. */
/*
* All DPL 0 code and data segments are squeezed into DPL 1.
*
* We're skipping conforming segments here because those
* cannot give us any trouble.
*/
!= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) )
{
}
else
}
else
{
/*
* System type selectors are marked not present.
* Recompiler or special handling is required for these.
*/
/** @todo what about interrupt gates and rawr0? */
}
}
/**
* Checks if a segment register is stale given the shadow descriptor table
* entry.
*
* @returns @c true if stale, @c false if not.
* @param pSReg The segment register.
* @param pShwDesc The shadow descriptor entry.
* @param iSReg The segment register number (X86_SREG_XXX).
*/
{
{
Log(("selmIsSRegStale32: Attributes changed (%#x -> %#x)\n", pSReg->Attr.u, X86DESC_GET_HID_ATTR(pShwDesc)));
return true;
}
{
Log(("selmIsSRegStale32: base changed (%#llx -> %#llx)\n", pSReg->u64Base, X86DESC_BASE(pShwDesc)));
return true;
}
{
Log(("selmIsSRegStale32: limit changed (%#x -> %#x)\n", pSReg->u32Limit, X86DESC_LIMIT_G(pShwDesc)));
return true;
}
return false;
}
/**
* Loads the hidden bits of a selector register from a shadow descriptor table
* entry.
*
* @param pSReg The segment register in question.
* @param pShwDesc The shadow descriptor table entry.
*/
{
}
/**
* Loads the hidden bits of a selector register from a guest descriptor table
* entry.
*
* @param pVCpu The current virtual CPU.
* @param pSReg The segment register in question.
* @param pGstDesc The guest descriptor table entry.
*/
DECLINLINE(void) selmLoadHiddenSRegFromGuestDesc(PVMCPU pVCpu, PCPUMSELREG pSReg, PCX86DESC pGstDesc)
{
}
#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
/** @} */
#endif