/openjdk7/hotspot/src/cpu/x86/vm/ |
H A D | c1_Defs_x86.hpp | 63 pd_last_cpu_reg = NOT_LP64(5) LP64_ONLY(11), 64 pd_first_byte_reg = NOT_LP64(2) LP64_ONLY(0), 65 pd_last_byte_reg = NOT_LP64(5) LP64_ONLY(11),
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H A D | interpreter_x86.hpp | 30 return NOT_LP64(Address::times_4) LP64_ONLY(Address::times_8);
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H A D | c1_LIRAssembler_x86.hpp | 56 enum { call_stub_size = NOT_LP64(15) LP64_ONLY(28), 58 deopt_handler_size = NOT_LP64(10) LP64_ONLY(17)
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H A D | methodHandles_x86.hpp | 30 adapter_code_size = NOT_LP64(16000 DEBUG_ONLY(+ 25000)) LP64_ONLY(32000 DEBUG_ONLY(+ 150000)) 60 return LP64_ONLY(r13) NOT_LP64(rsi);
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H A D | assembler_x86.cpp | 468 NOT_LP64(assert(false, "64bit prefixes")); 479 NOT_LP64(assert(false, "64bit prefixes")); 518 NOT_LP64(assert(false, "64bit prefix found")); 683 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); 746 NOT_LP64(assert(false, "found 64bit prefix")); 1001 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1006 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1011 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1016 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1129 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operan [all...] |
H A D | assembler_x86.hpp | 161 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) 188 NOT_LP64(Address(address loc, RelocationHolder spec);) 444 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); 726 bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); 817 static bool is_polling_page_far() NOT_LP64({ return false;}); 1902 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } 1903 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } 2395 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } 2398 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } 2407 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(and [all...] |
H A D | c1_MacroAssembler_x86.cpp | 226 NOT_LP64(movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - 2*BytesPerWord), t1);) 280 NOT_LP64(movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - (2*BytesPerWord)), 347 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
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H A D | c1_Runtime1_x86.cpp | 46 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); // is callee-saved register (Visual C++ calling conventions) 100 NOT_LP64(addptr(rsp, num_rt_args()*BytesPerWord)); 650 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); 683 const int frame_size = 2 /*BP, return address*/ NOT_LP64(+ 1 /*thread*/) WIN64_ONLY(+ frame::arg_reg_save_area_bytes / BytesPerWord); 705 NOT_LP64(__ get_thread(thread);) 762 NOT_LP64(__ get_thread(thread);) 778 const Register exception_oop_callee_saved = NOT_LP64(rsi) LP64_ONLY(r14); 782 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); 789 NOT_LP64(__ get_thread(thread);) 810 NOT_LP64(_ [all...] |
H A D | cppInterpreter_x86.cpp | 76 const Register state = NOT_LP64(rsi) LP64_ONLY(r13); 77 const Register sender_sp_on_entry = NOT_LP64(rsi) LP64_ONLY(r13); 340 NOT_LP64(__ movl(rdx, Address(rdx, 2*wordSize));) // get result high word 677 const Register thread = LP64_ONLY(r15_thread) NOT_LP64(rsi); 679 NOT_LP64(__ get_thread(thread)); 751 const Register monitor = NOT_LP64(rdx) LP64_ONLY(c_rarg1); 1033 const Register unlock_thread = LP64_ONLY(r15_thread) NOT_LP64(rax); 1034 NOT_LP64(__ movptr(unlock_thread, STATE(_thread));) // get thread 1077 NOT_LP64(__ movl(rax, STATE(_thread));) // get thread 1108 const Register thread = LP64_ONLY(r15_thread) NOT_LP64(rd [all...] |
H A D | nativeInst_x86.cpp | 243 NOT_LP64(assert((0xC0 & ubyte_at(1)) == 0xC0, "shouldn't have LDS and LES instructions")); 248 NOT_LP64(assert((0xC0 & ubyte_at(1)) == 0xC0, "shouldn't have LDS and LES instructions"));
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H A D | templateTable_x86_32.cpp | 492 NOT_LP64(__ movptr(rdx, Address(rcx, rbx, Address::times_ptr, base_offset + 1 * wordSize))); 565 NOT_LP64(__ movl(rdx, haddress(rbx))); 609 NOT_LP64(__ movl(rdx, haddress(rbx))); 673 NOT_LP64(__ movl(rdx, Address(rdx, rbx, Address::times_8, arrayOopDesc::base_offset_in_bytes(T_LONG) + 1 * wordSize))); 759 NOT_LP64(__ movptr(rdx, haddress(n))); 858 NOT_LP64(__ movptr(haddress(rbx), rdx)); 897 NOT_LP64(__ movl(haddress(rbx), rdx)); 939 NOT_LP64(__ movl(Address(rcx, rbx, Address::times_8, arrayOopDesc::base_offset_in_bytes(T_LONG) + 1 * wordSize), rdx)); 1054 NOT_LP64(__ movptr(haddress(n), rdx)); 2592 NOT_LP64(_ [all...] |
H A D | c1_FrameMap_x86.cpp | 145 assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers");
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H A D | c1_LIRAssembler_x86.cpp | 193 NOT_LP64(__ push_reg(opr->as_register_hi())); 342 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 946 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 1114 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1549 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); 1927 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1930 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 2019 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 2024 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 2100 NOT_LP64(assert_different_register [all...] |
H A D | sharedRuntime_x86_32.cpp | 664 NOT_LP64(ShouldNotReachHere()); 864 const int offset = (NOT_LP64(true ||) sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)? 882 const int offset = (NOT_LP64(true ||) sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)? 1131 NOT_LP64(__ movptr(rbx, Address(rbp, reg2offset_in(src.second())))); 1133 NOT_LP64(__ movptr(Address(rsp, reg2offset_out(dst.second())), rbx)); 1155 NOT_LP64(__ movptr(rbx, Address(rbp, reg2offset_in(src.second())))); 1157 NOT_LP64(__ movptr(Address(rsp, reg2offset_out(dst.second())), rbx)); 1179 NOT_LP64(__ movptr(Address(rbp, -2*wordSize), rdx)); 1199 NOT_LP64(__ movptr(rdx, Address(rbp, -2*wordSize)));
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/openjdk7/hotspot/src/cpu/sparc/vm/ |
H A D | methodHandles_sparc.hpp | 30 adapter_code_size = NOT_LP64(23000 DEBUG_ONLY(+ 40000)) LP64_ONLY(35000 DEBUG_ONLY(+ 50000))
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/openjdk7/hotspot/src/share/vm/services/ |
H A D | memoryUsage.hpp | 72 NOT_LP64(ret = val;)
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/openjdk7/hotspot/src/share/vm/runtime/ |
H A D | fieldDescriptor.cpp | 167 NOT_LP64(as_int = obj->int_field(offset())); 172 NOT_LP64(as_int = obj->int_field(offset()));
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H A D | globals.hpp | 1657 product(uintx, MarkStackSize, NOT_LP64(32*K) LP64_ONLY(4*M), \ 1660 product(uintx, MarkStackSizeMax, NOT_LP64(4*M) LP64_ONLY(512*M), \ 3547 product(uintx, SharedReadWriteSize, NOT_LP64(12*M) LP64_ONLY(13*M), \ 3553 product(uintx, SharedMiscDataSize, NOT_LP64(4*M) LP64_ONLY(5*M) NOT_PRODUCT(+1*M), \ 3623 product(uintx, StringTableSize, NOT_LP64(1009) LP64_ONLY(60013), \
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/openjdk7/hotspot/src/share/vm/utilities/ |
H A D | macros.hpp | 114 #define NOT_LP64(code) macro 117 #define NOT_LP64(code) code macro
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H A D | taskqueue.hpp | 139 typedef NOT_LP64(uint16_t) LP64_ONLY(uint32_t) idx_t;
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/openjdk7/hotspot/src/share/vm/oops/ |
H A D | markOop.hpp | 116 cms_bits = LP64_ONLY(1) NOT_LP64(0), 382 NOT_LP64(0);
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/openjdk7/hotspot/src/share/vm/gc_implementation/parallelScavenge/ |
H A D | psCompactionManager.hpp | 68 #define QUEUE_SIZE (1 << NOT_LP64(12) LP64_ONLY(13))
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/openjdk7/hotspot/src/os_cpu/solaris_x86/vm/ |
H A D | assembler_solaris_x86.cpp | 114 int segment = NOT_LP64(Assembler::GS_segment) LP64_ONLY(Assembler::FS_segment);
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/openjdk7/hotspot/src/share/vm/shark/ |
H A D | sharkContext.hpp | 112 return LP64_ONLY(jlong_type()) NOT_LP64(jint_type());
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H A D | sharkBuilder.cpp | 401 "llvm.atomic.cmp.swap.i" LP64_ONLY("64") NOT_LP64("32") ".p0i" LP64_ONLY("64") NOT_LP64("32"),
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