0N/A/*
1988N/A * Copyright (c) 1999, 2011, Oracle and/or its affiliates. All rights reserved.
0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A *
0N/A * This code is free software; you can redistribute it and/or modify it
0N/A * under the terms of the GNU General Public License version 2 only, as
0N/A * published by the Free Software Foundation.
0N/A *
0N/A * This code is distributed in the hope that it will be useful, but WITHOUT
0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A * version 2 for more details (a copy is included in the LICENSE file that
0N/A * accompanied this code).
0N/A *
0N/A * You should have received a copy of the GNU General Public License version
0N/A * 2 along with this work; if not, write to the Free Software Foundation,
0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0N/A *
1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1472N/A * or visit www.oracle.com if you need additional information or have any
1472N/A * questions.
0N/A *
0N/A */
0N/A
1879N/A#include "precompiled.hpp"
2262N/A#include "asm/assembler.hpp"
1879N/A#include "c1/c1_Defs.hpp"
1879N/A#include "c1/c1_MacroAssembler.hpp"
1879N/A#include "c1/c1_Runtime1.hpp"
1879N/A#include "interpreter/interpreter.hpp"
1879N/A#include "nativeInst_x86.hpp"
1879N/A#include "oops/compiledICHolderOop.hpp"
1879N/A#include "oops/oop.inline.hpp"
1879N/A#include "prims/jvmtiExport.hpp"
1879N/A#include "register_x86.hpp"
1879N/A#include "runtime/sharedRuntime.hpp"
1879N/A#include "runtime/signature.hpp"
1879N/A#include "runtime/vframeArray.hpp"
1879N/A#include "vmreg_x86.inline.hpp"
0N/A
0N/A
0N/A// Implementation of StubAssembler
0N/A
0N/Aint StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, int args_size) {
0N/A // setup registers
304N/A const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); // is callee-saved register (Visual C++ calling conventions)
0N/A assert(!(oop_result1->is_valid() || oop_result2->is_valid()) || oop_result1 != oop_result2, "registers must be different");
0N/A assert(oop_result1 != thread && oop_result2 != thread, "registers must be different");
0N/A assert(args_size >= 0, "illegal args_size");
3575N/A bool align_stack = false;
3575N/A#ifdef _LP64
3575N/A // At a method handle call, the stack may not be properly aligned
3575N/A // when returning with an exception.
3575N/A align_stack = (stub_id() == Runtime1::handle_exception_from_callee_id);
3575N/A#endif
0N/A
304N/A#ifdef _LP64
304N/A mov(c_rarg0, thread);
304N/A set_num_rt_args(0); // Nothing on stack
304N/A#else
0N/A set_num_rt_args(1 + args_size);
0N/A
0N/A // push java thread (becomes first argument of C function)
0N/A get_thread(thread);
304N/A push(thread);
304N/A#endif // _LP64
0N/A
3575N/A int call_offset;
3575N/A if (!align_stack) {
3575N/A set_last_Java_frame(thread, noreg, rbp, NULL);
3575N/A } else {
3575N/A address the_pc = pc();
3575N/A call_offset = offset();
3575N/A set_last_Java_frame(thread, noreg, rbp, the_pc);
3575N/A andptr(rsp, -(StackAlignmentInBytes)); // Align stack
3575N/A }
304N/A
0N/A // do the call
0N/A call(RuntimeAddress(entry));
3575N/A if (!align_stack) {
3575N/A call_offset = offset();
3575N/A }
0N/A // verify callee-saved register
0N/A#ifdef ASSERT
0N/A guarantee(thread != rax, "change this code");
304N/A push(rax);
0N/A { Label L;
0N/A get_thread(rax);
304N/A cmpptr(thread, rax);
0N/A jcc(Assembler::equal, L);
0N/A int3();
0N/A stop("StubAssembler::call_RT: rdi not callee saved?");
0N/A bind(L);
0N/A }
304N/A pop(rax);
0N/A#endif
3575N/A reset_last_Java_frame(thread, true, align_stack);
0N/A
0N/A // discard thread and arguments
304N/A NOT_LP64(addptr(rsp, num_rt_args()*BytesPerWord));
0N/A
0N/A // check for pending exceptions
0N/A { Label L;
304N/A cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
0N/A jcc(Assembler::equal, L);
0N/A // exception pending => remove activation and forward to exception handler
304N/A movptr(rax, Address(thread, Thread::pending_exception_offset()));
0N/A // make sure that the vm_results are cleared
0N/A if (oop_result1->is_valid()) {
512N/A movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
0N/A }
0N/A if (oop_result2->is_valid()) {
512N/A movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
0N/A }
0N/A if (frame_size() == no_frame_size) {
0N/A leave();
0N/A jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
0N/A } else if (_stub_id == Runtime1::forward_exception_id) {
0N/A should_not_reach_here();
0N/A } else {
0N/A jump(RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id)));
0N/A }
0N/A bind(L);
0N/A }
0N/A // get oop results if there are any and reset the values in the thread
0N/A if (oop_result1->is_valid()) {
304N/A movptr(oop_result1, Address(thread, JavaThread::vm_result_offset()));
512N/A movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
0N/A verify_oop(oop_result1);
0N/A }
0N/A if (oop_result2->is_valid()) {
304N/A movptr(oop_result2, Address(thread, JavaThread::vm_result_2_offset()));
512N/A movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
0N/A verify_oop(oop_result2);
0N/A }
0N/A return call_offset;
0N/A}
0N/A
0N/A
0N/Aint StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1) {
304N/A#ifdef _LP64
304N/A mov(c_rarg1, arg1);
304N/A#else
304N/A push(arg1);
304N/A#endif // _LP64
0N/A return call_RT(oop_result1, oop_result2, entry, 1);
0N/A}
0N/A
0N/A
0N/Aint StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1, Register arg2) {
304N/A#ifdef _LP64
304N/A if (c_rarg1 == arg2) {
304N/A if (c_rarg2 == arg1) {
304N/A xchgq(arg1, arg2);
304N/A } else {
304N/A mov(c_rarg2, arg2);
304N/A mov(c_rarg1, arg1);
304N/A }
304N/A } else {
304N/A mov(c_rarg1, arg1);
304N/A mov(c_rarg2, arg2);
304N/A }
304N/A#else
304N/A push(arg2);
304N/A push(arg1);
304N/A#endif // _LP64
0N/A return call_RT(oop_result1, oop_result2, entry, 2);
0N/A}
0N/A
0N/A
0N/Aint StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1, Register arg2, Register arg3) {
304N/A#ifdef _LP64
304N/A // if there is any conflict use the stack
304N/A if (arg1 == c_rarg2 || arg1 == c_rarg3 ||
304N/A arg2 == c_rarg1 || arg1 == c_rarg3 ||
304N/A arg3 == c_rarg1 || arg1 == c_rarg2) {
304N/A push(arg3);
304N/A push(arg2);
304N/A push(arg1);
304N/A pop(c_rarg1);
304N/A pop(c_rarg2);
304N/A pop(c_rarg3);
304N/A } else {
304N/A mov(c_rarg1, arg1);
304N/A mov(c_rarg2, arg2);
304N/A mov(c_rarg3, arg3);
304N/A }
304N/A#else
304N/A push(arg3);
304N/A push(arg2);
304N/A push(arg1);
304N/A#endif // _LP64
0N/A return call_RT(oop_result1, oop_result2, entry, 3);
0N/A}
0N/A
0N/A
0N/A// Implementation of StubFrame
0N/A
0N/Aclass StubFrame: public StackObj {
0N/A private:
0N/A StubAssembler* _sasm;
0N/A
0N/A public:
0N/A StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments);
0N/A void load_argument(int offset_in_words, Register reg);
0N/A
0N/A ~StubFrame();
0N/A};
0N/A
0N/A
0N/A#define __ _sasm->
0N/A
0N/AStubFrame::StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments) {
0N/A _sasm = sasm;
0N/A __ set_info(name, must_gc_arguments);
0N/A __ enter();
0N/A}
0N/A
0N/A// load parameters that were stored with LIR_Assembler::store_parameter
0N/A// Note: offsets for store_parameter and load_argument must match
0N/Avoid StubFrame::load_argument(int offset_in_words, Register reg) {
0N/A // rbp, + 0: link
0N/A // + 1: return address
0N/A // + 2: argument with offset 0
0N/A // + 3: argument with offset 1
0N/A // + 4: ...
0N/A
304N/A __ movptr(reg, Address(rbp, (offset_in_words + 2) * BytesPerWord));
0N/A}
0N/A
0N/A
0N/AStubFrame::~StubFrame() {
0N/A __ leave();
0N/A __ ret(0);
0N/A}
0N/A
0N/A#undef __
0N/A
0N/A
0N/A// Implementation of Runtime1
0N/A
0N/A#define __ sasm->
0N/A
304N/Aconst int float_regs_as_doubles_size_in_slots = pd_nof_fpu_regs_frame_map * 2;
304N/Aconst int xmm_regs_as_doubles_size_in_slots = FrameMap::nof_xmm_regs * 2;
0N/A
0N/A// Stack layout for saving/restoring all the registers needed during a runtime
0N/A// call (this includes deoptimization)
0N/A// Note: note that users of this frame may well have arguments to some runtime
0N/A// while these values are on the stack. These positions neglect those arguments
0N/A// but the code in save_live_registers will take the argument count into
0N/A// account.
0N/A//
304N/A#ifdef _LP64
304N/A #define SLOT2(x) x,
304N/A #define SLOT_PER_WORD 2
304N/A#else
304N/A #define SLOT2(x)
304N/A #define SLOT_PER_WORD 1
304N/A#endif // _LP64
304N/A
0N/Aenum reg_save_layout {
304N/A // 64bit needs to keep stack 16 byte aligned. So we add some alignment dummies to make that
304N/A // happen and will assert if the stack size we create is misaligned
304N/A#ifdef _LP64
304N/A align_dummy_0, align_dummy_1,
304N/A#endif // _LP64
2168N/A#ifdef _WIN64
2168N/A // Windows always allocates space for it's argument registers (see
2168N/A // frame::arg_reg_save_area_bytes).
2168N/A arg_reg_save_1, arg_reg_save_1H, // 0, 4
2168N/A arg_reg_save_2, arg_reg_save_2H, // 8, 12
2168N/A arg_reg_save_3, arg_reg_save_3H, // 16, 20
2168N/A arg_reg_save_4, arg_reg_save_4H, // 24, 28
2168N/A#endif // _WIN64
304N/A xmm_regs_as_doubles_off, // 32
304N/A float_regs_as_doubles_off = xmm_regs_as_doubles_off + xmm_regs_as_doubles_size_in_slots, // 160
304N/A fpu_state_off = float_regs_as_doubles_off + float_regs_as_doubles_size_in_slots, // 224
304N/A // fpu_state_end_off is exclusive
304N/A fpu_state_end_off = fpu_state_off + (FPUStateSizeInWords / SLOT_PER_WORD), // 352
304N/A marker = fpu_state_end_off, SLOT2(markerH) // 352, 356
304N/A extra_space_offset, // 360
304N/A#ifdef _LP64
304N/A r15_off = extra_space_offset, r15H_off, // 360, 364
304N/A r14_off, r14H_off, // 368, 372
304N/A r13_off, r13H_off, // 376, 380
304N/A r12_off, r12H_off, // 384, 388
304N/A r11_off, r11H_off, // 392, 396
304N/A r10_off, r10H_off, // 400, 404
304N/A r9_off, r9H_off, // 408, 412
304N/A r8_off, r8H_off, // 416, 420
304N/A rdi_off, rdiH_off, // 424, 428
304N/A#else
0N/A rdi_off = extra_space_offset,
304N/A#endif // _LP64
304N/A rsi_off, SLOT2(rsiH_off) // 432, 436
304N/A rbp_off, SLOT2(rbpH_off) // 440, 444
304N/A rsp_off, SLOT2(rspH_off) // 448, 452
304N/A rbx_off, SLOT2(rbxH_off) // 456, 460
304N/A rdx_off, SLOT2(rdxH_off) // 464, 468
304N/A rcx_off, SLOT2(rcxH_off) // 472, 476
304N/A rax_off, SLOT2(raxH_off) // 480, 484
304N/A saved_rbp_off, SLOT2(saved_rbpH_off) // 488, 492
304N/A return_off, SLOT2(returnH_off) // 496, 500
2168N/A reg_save_frame_size // As noted: neglects any parameters to runtime // 504
0N/A};
0N/A
0N/A
0N/A
0N/A// Save off registers which might be killed by calls into the runtime.
0N/A// Tries to smart of about FP registers. In particular we separate
0N/A// saving and describing the FPU registers for deoptimization since we
0N/A// have to save the FPU registers twice if we describe them and on P4
0N/A// saving FPU registers which don't contain anything appears
0N/A// expensive. The deopt blob is the only thing which needs to
0N/A// describe FPU registers. In all other cases it should be sufficient
0N/A// to simply save their current value.
0N/A
0N/Astatic OopMap* generate_oop_map(StubAssembler* sasm, int num_rt_args,
0N/A bool save_fpu_registers = true) {
304N/A
304N/A // In 64bit all the args are in regs so there are no additional stack slots
304N/A LP64_ONLY(num_rt_args = 0);
304N/A LP64_ONLY(assert((reg_save_frame_size * VMRegImpl::stack_slot_size) % 16 == 0, "must be 16 byte aligned");)
304N/A int frame_size_in_slots = reg_save_frame_size + num_rt_args; // args + thread
304N/A sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word );
0N/A
0N/A // record saved value locations in an OopMap
0N/A // locations are offsets from sp after runtime call; num_rt_args is number of arguments in call, including thread
304N/A OopMap* map = new OopMap(frame_size_in_slots, 0);
0N/A map->set_callee_saved(VMRegImpl::stack2reg(rax_off + num_rt_args), rax->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(rcx_off + num_rt_args), rcx->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(rdx_off + num_rt_args), rdx->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(rbx_off + num_rt_args), rbx->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(rsi_off + num_rt_args), rsi->as_VMReg());
0N/A map->set_callee_saved(VMRegImpl::stack2reg(rdi_off + num_rt_args), rdi->as_VMReg());
304N/A#ifdef _LP64
304N/A map->set_callee_saved(VMRegImpl::stack2reg(r8_off + num_rt_args), r8->as_VMReg());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(r9_off + num_rt_args), r9->as_VMReg());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(r10_off + num_rt_args), r10->as_VMReg());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(r11_off + num_rt_args), r11->as_VMReg());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(r12_off + num_rt_args), r12->as_VMReg());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(r13_off + num_rt_args), r13->as_VMReg());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(r14_off + num_rt_args), r14->as_VMReg());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(r15_off + num_rt_args), r15->as_VMReg());
304N/A
304N/A // This is stupid but needed.
304N/A map->set_callee_saved(VMRegImpl::stack2reg(raxH_off + num_rt_args), rax->as_VMReg()->next());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(rcxH_off + num_rt_args), rcx->as_VMReg()->next());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(rdxH_off + num_rt_args), rdx->as_VMReg()->next());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(rbxH_off + num_rt_args), rbx->as_VMReg()->next());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(rsiH_off + num_rt_args), rsi->as_VMReg()->next());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(rdiH_off + num_rt_args), rdi->as_VMReg()->next());
304N/A
304N/A map->set_callee_saved(VMRegImpl::stack2reg(r8H_off + num_rt_args), r8->as_VMReg()->next());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(r9H_off + num_rt_args), r9->as_VMReg()->next());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(r10H_off + num_rt_args), r10->as_VMReg()->next());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(r11H_off + num_rt_args), r11->as_VMReg()->next());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(r12H_off + num_rt_args), r12->as_VMReg()->next());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(r13H_off + num_rt_args), r13->as_VMReg()->next());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(r14H_off + num_rt_args), r14->as_VMReg()->next());
304N/A map->set_callee_saved(VMRegImpl::stack2reg(r15H_off + num_rt_args), r15->as_VMReg()->next());
304N/A#endif // _LP64
0N/A
0N/A if (save_fpu_registers) {
0N/A if (UseSSE < 2) {
0N/A int fpu_off = float_regs_as_doubles_off;
0N/A for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
0N/A VMReg fpu_name_0 = FrameMap::fpu_regname(n);
0N/A map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + num_rt_args), fpu_name_0);
0N/A // %%% This is really a waste but we'll keep things as they were for now
0N/A if (true) {
0N/A map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + 1 + num_rt_args), fpu_name_0->next());
0N/A }
0N/A fpu_off += 2;
0N/A }
0N/A assert(fpu_off == fpu_state_off, "incorrect number of fpu stack slots");
0N/A }
0N/A
0N/A if (UseSSE >= 2) {
0N/A int xmm_off = xmm_regs_as_doubles_off;
0N/A for (int n = 0; n < FrameMap::nof_xmm_regs; n++) {
0N/A VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg();
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0);
0N/A // %%% This is really a waste but we'll keep things as they were for now
0N/A if (true) {
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + 1 + num_rt_args), xmm_name_0->next());
0N/A }
0N/A xmm_off += 2;
0N/A }
0N/A assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers");
0N/A
0N/A } else if (UseSSE == 1) {
0N/A int xmm_off = xmm_regs_as_doubles_off;
0N/A for (int n = 0; n < FrameMap::nof_xmm_regs; n++) {
0N/A VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg();
0N/A map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0);
0N/A xmm_off += 2;
0N/A }
0N/A assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers");
0N/A }
0N/A }
0N/A
0N/A return map;
0N/A}
0N/A
0N/Astatic OopMap* save_live_registers(StubAssembler* sasm, int num_rt_args,
0N/A bool save_fpu_registers = true) {
0N/A __ block_comment("save_live_registers");
0N/A
304N/A __ pusha(); // integer registers
0N/A
0N/A // assert(float_regs_as_doubles_off % 2 == 0, "misaligned offset");
0N/A // assert(xmm_regs_as_doubles_off % 2 == 0, "misaligned offset");
0N/A
304N/A __ subptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
0N/A
0N/A#ifdef ASSERT
304N/A __ movptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
0N/A#endif
0N/A
0N/A if (save_fpu_registers) {
0N/A if (UseSSE < 2) {
0N/A // save FPU stack
304N/A __ fnsave(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
0N/A __ fwait();
0N/A
0N/A#ifdef ASSERT
0N/A Label ok;
304N/A __ cmpw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std());
0N/A __ jccb(Assembler::equal, ok);
0N/A __ stop("corrupted control word detected");
0N/A __ bind(ok);
0N/A#endif
0N/A
0N/A // Reset the control word to guard against exceptions being unmasked
0N/A // since fstp_d can cause FPU stack underflow exceptions. Write it
0N/A // into the on stack copy and then reload that to make sure that the
0N/A // current and future values are correct.
304N/A __ movw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std());
304N/A __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
0N/A
0N/A // Save the FPU registers in de-opt-able form
304N/A __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0));
304N/A __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8));
304N/A __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
304N/A __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
304N/A __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
304N/A __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
304N/A __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
304N/A __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
0N/A }
0N/A
0N/A if (UseSSE >= 2) {
0N/A // save XMM registers
0N/A // XMM registers can contain float or double values, but this is not known here,
0N/A // so always save them as doubles.
0N/A // note that float values are _not_ converted automatically, so for float values
0N/A // the second word contains only garbage data.
304N/A __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0), xmm0);
304N/A __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8), xmm1);
304N/A __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16), xmm2);
304N/A __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24), xmm3);
304N/A __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32), xmm4);
304N/A __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40), xmm5);
304N/A __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48), xmm6);
304N/A __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56), xmm7);
304N/A#ifdef _LP64
304N/A __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 64), xmm8);
304N/A __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 72), xmm9);
304N/A __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 80), xmm10);
304N/A __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 88), xmm11);
304N/A __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 96), xmm12);
304N/A __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 104), xmm13);
304N/A __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 112), xmm14);
304N/A __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 120), xmm15);
304N/A#endif // _LP64
0N/A } else if (UseSSE == 1) {
0N/A // save XMM registers as float because double not supported without SSE2
304N/A __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0), xmm0);
304N/A __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8), xmm1);
304N/A __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16), xmm2);
304N/A __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24), xmm3);
304N/A __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32), xmm4);
304N/A __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40), xmm5);
304N/A __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48), xmm6);
304N/A __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56), xmm7);
0N/A }
0N/A }
0N/A
0N/A // FPU stack must be empty now
0N/A __ verify_FPU(0, "save_live_registers");
0N/A
0N/A return generate_oop_map(sasm, num_rt_args, save_fpu_registers);
0N/A}
0N/A
0N/A
0N/Astatic void restore_fpu(StubAssembler* sasm, bool restore_fpu_registers = true) {
0N/A if (restore_fpu_registers) {
0N/A if (UseSSE >= 2) {
0N/A // restore XMM registers
304N/A __ movdbl(xmm0, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0));
304N/A __ movdbl(xmm1, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8));
304N/A __ movdbl(xmm2, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
304N/A __ movdbl(xmm3, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
304N/A __ movdbl(xmm4, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
304N/A __ movdbl(xmm5, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
304N/A __ movdbl(xmm6, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
304N/A __ movdbl(xmm7, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
304N/A#ifdef _LP64
304N/A __ movdbl(xmm8, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 64));
304N/A __ movdbl(xmm9, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 72));
304N/A __ movdbl(xmm10, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 80));
304N/A __ movdbl(xmm11, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 88));
304N/A __ movdbl(xmm12, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 96));
304N/A __ movdbl(xmm13, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 104));
304N/A __ movdbl(xmm14, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 112));
304N/A __ movdbl(xmm15, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 120));
304N/A#endif // _LP64
0N/A } else if (UseSSE == 1) {
0N/A // restore XMM registers
304N/A __ movflt(xmm0, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0));
304N/A __ movflt(xmm1, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8));
304N/A __ movflt(xmm2, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
304N/A __ movflt(xmm3, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
304N/A __ movflt(xmm4, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
304N/A __ movflt(xmm5, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
304N/A __ movflt(xmm6, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
304N/A __ movflt(xmm7, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
0N/A }
0N/A
0N/A if (UseSSE < 2) {
304N/A __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
0N/A } else {
0N/A // check that FPU stack is really empty
0N/A __ verify_FPU(0, "restore_live_registers");
0N/A }
0N/A
0N/A } else {
0N/A // check that FPU stack is really empty
0N/A __ verify_FPU(0, "restore_live_registers");
0N/A }
0N/A
0N/A#ifdef ASSERT
0N/A {
0N/A Label ok;
304N/A __ cmpptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
0N/A __ jcc(Assembler::equal, ok);
0N/A __ stop("bad offsets in frame");
0N/A __ bind(ok);
0N/A }
304N/A#endif // ASSERT
0N/A
304N/A __ addptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
0N/A}
0N/A
0N/A
0N/Astatic void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = true) {
0N/A __ block_comment("restore_live_registers");
0N/A
0N/A restore_fpu(sasm, restore_fpu_registers);
304N/A __ popa();
0N/A}
0N/A
0N/A
0N/Astatic void restore_live_registers_except_rax(StubAssembler* sasm, bool restore_fpu_registers = true) {
0N/A __ block_comment("restore_live_registers_except_rax");
0N/A
0N/A restore_fpu(sasm, restore_fpu_registers);
0N/A
304N/A#ifdef _LP64
304N/A __ movptr(r15, Address(rsp, 0));
304N/A __ movptr(r14, Address(rsp, wordSize));
304N/A __ movptr(r13, Address(rsp, 2 * wordSize));
304N/A __ movptr(r12, Address(rsp, 3 * wordSize));
304N/A __ movptr(r11, Address(rsp, 4 * wordSize));
304N/A __ movptr(r10, Address(rsp, 5 * wordSize));
304N/A __ movptr(r9, Address(rsp, 6 * wordSize));
304N/A __ movptr(r8, Address(rsp, 7 * wordSize));
304N/A __ movptr(rdi, Address(rsp, 8 * wordSize));
304N/A __ movptr(rsi, Address(rsp, 9 * wordSize));
304N/A __ movptr(rbp, Address(rsp, 10 * wordSize));
304N/A // skip rsp
304N/A __ movptr(rbx, Address(rsp, 12 * wordSize));
304N/A __ movptr(rdx, Address(rsp, 13 * wordSize));
304N/A __ movptr(rcx, Address(rsp, 14 * wordSize));
304N/A
304N/A __ addptr(rsp, 16 * wordSize);
304N/A#else
304N/A
304N/A __ pop(rdi);
304N/A __ pop(rsi);
304N/A __ pop(rbp);
304N/A __ pop(rbx); // skip this value
304N/A __ pop(rbx);
304N/A __ pop(rdx);
304N/A __ pop(rcx);
304N/A __ addptr(rsp, BytesPerWord);
304N/A#endif // _LP64
0N/A}
0N/A
0N/A
0N/Avoid Runtime1::initialize_pd() {
0N/A // nothing to do
0N/A}
0N/A
0N/A
0N/A// target: the entry point of the method that creates and posts the exception oop
0N/A// has_argument: true if the exception needs an argument (passed on stack because registers must be preserved)
0N/A
0N/AOopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) {
0N/A // preserve all registers
0N/A int num_rt_args = has_argument ? 2 : 1;
0N/A OopMap* oop_map = save_live_registers(sasm, num_rt_args);
0N/A
0N/A // now all registers are saved and can be used freely
0N/A // verify that no old value is used accidentally
0N/A __ invalidate_registers(true, true, true, true, true, true);
0N/A
0N/A // registers used by this stub
0N/A const Register temp_reg = rbx;
0N/A
0N/A // load argument for exception that is passed as an argument into the stub
0N/A if (has_argument) {
304N/A#ifdef _LP64
304N/A __ movptr(c_rarg1, Address(rbp, 2*BytesPerWord));
304N/A#else
304N/A __ movptr(temp_reg, Address(rbp, 2*BytesPerWord));
304N/A __ push(temp_reg);
304N/A#endif // _LP64
0N/A }
0N/A int call_offset = __ call_RT(noreg, noreg, target, num_rt_args - 1);
0N/A
0N/A OopMapSet* oop_maps = new OopMapSet();
0N/A oop_maps->add_gc_map(call_offset, oop_map);
0N/A
0N/A __ stop("should not reach here");
0N/A
0N/A return oop_maps;
0N/A}
0N/A
0N/A
2168N/AOopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler *sasm) {
2168N/A __ block_comment("generate_handle_exception");
2168N/A
0N/A // incoming parameters
0N/A const Register exception_oop = rax;
2168N/A const Register exception_pc = rdx;
0N/A // other registers used in this stub
304N/A const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
0N/A
2168N/A // Save registers, if required.
2168N/A OopMapSet* oop_maps = new OopMapSet();
2168N/A OopMap* oop_map = NULL;
2168N/A switch (id) {
2168N/A case forward_exception_id:
2168N/A // We're handling an exception in the context of a compiled frame.
2168N/A // The registers have been saved in the standard places. Perform
2168N/A // an exception lookup in the caller and dispatch to the handler
2168N/A // if found. Otherwise unwind and dispatch to the callers
2168N/A // exception handler.
2168N/A oop_map = generate_oop_map(sasm, 1 /*thread*/);
2168N/A
2168N/A // load and clear pending exception oop into RAX
2168N/A __ movptr(exception_oop, Address(thread, Thread::pending_exception_offset()));
2168N/A __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
2168N/A
2168N/A // load issuing PC (the return address for this stub) into rdx
2168N/A __ movptr(exception_pc, Address(rbp, 1*BytesPerWord));
2168N/A
2168N/A // make sure that the vm_results are cleared (may be unnecessary)
2168N/A __ movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
2168N/A __ movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2168N/A break;
2168N/A case handle_exception_nofpu_id:
2168N/A case handle_exception_id:
2168N/A // At this point all registers MAY be live.
2168N/A oop_map = save_live_registers(sasm, 1 /*thread*/, id == handle_exception_nofpu_id);
2168N/A break;
2168N/A case handle_exception_from_callee_id: {
2168N/A // At this point all registers except exception oop (RAX) and
2168N/A // exception pc (RDX) are dead.
2168N/A const int frame_size = 2 /*BP, return address*/ NOT_LP64(+ 1 /*thread*/) WIN64_ONLY(+ frame::arg_reg_save_area_bytes / BytesPerWord);
2168N/A oop_map = new OopMap(frame_size * VMRegImpl::slots_per_word, 0);
2168N/A sasm->set_frame_size(frame_size);
2168N/A WIN64_ONLY(__ subq(rsp, frame::arg_reg_save_area_bytes));
2168N/A break;
2168N/A }
2168N/A default: ShouldNotReachHere();
2168N/A }
0N/A
0N/A#ifdef TIERED
0N/A // C2 can leave the fpu stack dirty
2168N/A if (UseSSE < 2) {
0N/A __ empty_FPU_stack();
0N/A }
0N/A#endif // TIERED
0N/A
0N/A // verify that only rax, and rdx is valid at this time
0N/A __ invalidate_registers(false, true, true, false, true, true);
0N/A // verify that rax, contains a valid exception
0N/A __ verify_not_null_oop(exception_oop);
0N/A
0N/A // load address of JavaThread object for thread-local data
304N/A NOT_LP64(__ get_thread(thread);)
0N/A
0N/A#ifdef ASSERT
0N/A // check that fields in JavaThread for exception oop and issuing pc are
0N/A // empty before writing to them
0N/A Label oop_empty;
304N/A __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t) NULL_WORD);
0N/A __ jcc(Assembler::equal, oop_empty);
0N/A __ stop("exception oop already set");
0N/A __ bind(oop_empty);
0N/A
0N/A Label pc_empty;
304N/A __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
0N/A __ jcc(Assembler::equal, pc_empty);
0N/A __ stop("exception pc already set");
0N/A __ bind(pc_empty);
0N/A#endif
0N/A
0N/A // save exception oop and issuing pc into JavaThread
0N/A // (exception handler will load it from here)
304N/A __ movptr(Address(thread, JavaThread::exception_oop_offset()), exception_oop);
2168N/A __ movptr(Address(thread, JavaThread::exception_pc_offset()), exception_pc);
0N/A
0N/A // patch throwing pc into return address (has bci & oop map)
304N/A __ movptr(Address(rbp, 1*BytesPerWord), exception_pc);
0N/A
0N/A // compute the exception handler.
0N/A // the exception oop and the throwing pc are read from the fields in JavaThread
0N/A int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc));
0N/A oop_maps->add_gc_map(call_offset, oop_map);
0N/A
2168N/A // rax: handler address
0N/A // will be the deopt blob if nmethod was deoptimized while we looked up
0N/A // handler regardless of whether handler existed in the nmethod.
0N/A
0N/A // only rax, is valid at this time, all other registers have been destroyed by the runtime call
0N/A __ invalidate_registers(false, true, true, true, true, true);
0N/A
2168N/A // patch the return address, this stub will directly return to the exception handler
304N/A __ movptr(Address(rbp, 1*BytesPerWord), rax);
0N/A
2168N/A switch (id) {
2168N/A case forward_exception_id:
2168N/A case handle_exception_nofpu_id:
2168N/A case handle_exception_id:
2168N/A // Restore the registers that were saved at the beginning.
2168N/A restore_live_registers(sasm, id == handle_exception_nofpu_id);
2168N/A break;
2168N/A case handle_exception_from_callee_id:
2168N/A // WIN64_ONLY: No need to add frame::arg_reg_save_area_bytes to SP
2168N/A // since we do a leave anyway.
0N/A
2168N/A // Pop the return address since we are possibly changing SP (restoring from BP).
2168N/A __ leave();
2168N/A __ pop(rcx);
0N/A
2168N/A // Restore SP from BP if the exception PC is a method handle call site.
2168N/A NOT_LP64(__ get_thread(thread);)
2168N/A __ cmpl(Address(thread, JavaThread::is_method_handle_return_offset()), 0);
2168N/A __ cmovptr(Assembler::notEqual, rsp, rbp_mh_SP_save);
2168N/A __ jmp(rcx); // jump to exception handler
2168N/A break;
2168N/A default: ShouldNotReachHere();
2168N/A }
2168N/A
2168N/A return oop_maps;
0N/A}
0N/A
0N/A
0N/Avoid Runtime1::generate_unwind_exception(StubAssembler *sasm) {
0N/A // incoming parameters
0N/A const Register exception_oop = rax;
1295N/A // callee-saved copy of exception_oop during runtime call
1295N/A const Register exception_oop_callee_saved = NOT_LP64(rsi) LP64_ONLY(r14);
0N/A // other registers used in this stub
0N/A const Register exception_pc = rdx;
0N/A const Register handler_addr = rbx;
304N/A const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
0N/A
0N/A // verify that only rax, is valid at this time
0N/A __ invalidate_registers(false, true, true, true, true, true);
0N/A
0N/A#ifdef ASSERT
0N/A // check that fields in JavaThread for exception oop and issuing pc are empty
304N/A NOT_LP64(__ get_thread(thread);)
0N/A Label oop_empty;
304N/A __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), 0);
0N/A __ jcc(Assembler::equal, oop_empty);
0N/A __ stop("exception oop must be empty");
0N/A __ bind(oop_empty);
0N/A
0N/A Label pc_empty;
304N/A __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
0N/A __ jcc(Assembler::equal, pc_empty);
0N/A __ stop("exception pc must be empty");
0N/A __ bind(pc_empty);
0N/A#endif
0N/A
0N/A // clear the FPU stack in case any FPU results are left behind
0N/A __ empty_FPU_stack();
0N/A
1295N/A // save exception_oop in callee-saved register to preserve it during runtime calls
1295N/A __ verify_not_null_oop(exception_oop);
1295N/A __ movptr(exception_oop_callee_saved, exception_oop);
1295N/A
1295N/A NOT_LP64(__ get_thread(thread);)
1295N/A // Get return address (is on top of stack after leave).
304N/A __ movptr(exception_pc, Address(rsp, 0));
0N/A
1295N/A // search the exception handler address of the caller (using the return address)
1295N/A __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), thread, exception_pc);
1295N/A // rax: exception handler address of the caller
0N/A
1295N/A // Only RAX and RSI are valid at this time, all other registers have been destroyed by the call.
1295N/A __ invalidate_registers(false, true, true, true, false, true);
0N/A
0N/A // move result of call into correct register
304N/A __ movptr(handler_addr, rax);
0N/A
1295N/A // Restore exception oop to RAX (required convention of exception handler).
1295N/A __ movptr(exception_oop, exception_oop_callee_saved);
0N/A
1295N/A // verify that there is really a valid exception in rax
1295N/A __ verify_not_null_oop(exception_oop);
0N/A
0N/A // get throwing pc (= return address).
0N/A // rdx has been destroyed by the call, so it must be set again
0N/A // the pop is also necessary to simulate the effect of a ret(0)
304N/A __ pop(exception_pc);
0N/A
2168N/A // Restore SP from BP if the exception PC is a method handle call site.
1295N/A NOT_LP64(__ get_thread(thread);)
1368N/A __ cmpl(Address(thread, JavaThread::is_method_handle_return_offset()), 0);
1484N/A __ cmovptr(Assembler::notEqual, rsp, rbp_mh_SP_save);
0N/A
0N/A // continue at exception handler (return address removed)
0N/A // note: do *not* remove arguments when unwinding the
0N/A // activation since the caller assumes having
0N/A // all arguments on the stack when entering the
0N/A // runtime to determine the exception handler
0N/A // (GC happens at call site with arguments!)
1295N/A // rax: exception oop
0N/A // rdx: throwing pc
1295N/A // rbx: exception handler
0N/A __ jmp(handler_addr);
0N/A}
0N/A
0N/A
0N/AOopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
0N/A // use the maximum number of runtime-arguments here because it is difficult to
0N/A // distinguish each RT-Call.
0N/A // Note: This number affects also the RT-Call in generate_handle_exception because
0N/A // the oop-map is shared for all calls.
0N/A const int num_rt_args = 2; // thread + dummy
0N/A
0N/A DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
0N/A assert(deopt_blob != NULL, "deoptimization blob must have been created");
0N/A
0N/A OopMap* oop_map = save_live_registers(sasm, num_rt_args);
0N/A
304N/A#ifdef _LP64
304N/A const Register thread = r15_thread;
304N/A // No need to worry about dummy
304N/A __ mov(c_rarg0, thread);
304N/A#else
304N/A __ push(rax); // push dummy
0N/A
0N/A const Register thread = rdi; // is callee-saved register (Visual C++ calling conventions)
0N/A // push java thread (becomes first argument of C function)
0N/A __ get_thread(thread);
304N/A __ push(thread);
304N/A#endif // _LP64
0N/A __ set_last_Java_frame(thread, noreg, rbp, NULL);
0N/A // do the call
0N/A __ call(RuntimeAddress(target));
0N/A OopMapSet* oop_maps = new OopMapSet();
0N/A oop_maps->add_gc_map(__ offset(), oop_map);
0N/A // verify callee-saved register
0N/A#ifdef ASSERT
0N/A guarantee(thread != rax, "change this code");
304N/A __ push(rax);
0N/A { Label L;
0N/A __ get_thread(rax);
304N/A __ cmpptr(thread, rax);
0N/A __ jcc(Assembler::equal, L);
304N/A __ stop("StubAssembler::call_RT: rdi/r15 not callee saved?");
0N/A __ bind(L);
0N/A }
304N/A __ pop(rax);
0N/A#endif
0N/A __ reset_last_Java_frame(thread, true, false);
304N/A#ifndef _LP64
304N/A __ pop(rcx); // discard thread arg
304N/A __ pop(rcx); // discard dummy
304N/A#endif // _LP64
0N/A
0N/A // check for pending exceptions
0N/A { Label L;
304N/A __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
0N/A __ jcc(Assembler::equal, L);
0N/A // exception pending => remove activation and forward to exception handler
0N/A
304N/A __ testptr(rax, rax); // have we deoptimized?
0N/A __ jump_cc(Assembler::equal,
0N/A RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id)));
0N/A
0N/A // the deopt blob expects exceptions in the special fields of
0N/A // JavaThread, so copy and clear pending exception.
0N/A
0N/A // load and clear pending exception
304N/A __ movptr(rax, Address(thread, Thread::pending_exception_offset()));
512N/A __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
0N/A
0N/A // check that there is really a valid exception
0N/A __ verify_not_null_oop(rax);
0N/A
0N/A // load throwing pc: this is the return address of the stub
304N/A __ movptr(rdx, Address(rsp, return_off * VMRegImpl::stack_slot_size));
0N/A
0N/A#ifdef ASSERT
0N/A // check that fields in JavaThread for exception oop and issuing pc are empty
0N/A Label oop_empty;
304N/A __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
0N/A __ jcc(Assembler::equal, oop_empty);
0N/A __ stop("exception oop must be empty");
0N/A __ bind(oop_empty);
0N/A
0N/A Label pc_empty;
304N/A __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
0N/A __ jcc(Assembler::equal, pc_empty);
0N/A __ stop("exception pc must be empty");
0N/A __ bind(pc_empty);
0N/A#endif
0N/A
0N/A // store exception oop and throwing pc to JavaThread
304N/A __ movptr(Address(thread, JavaThread::exception_oop_offset()), rax);
304N/A __ movptr(Address(thread, JavaThread::exception_pc_offset()), rdx);
0N/A
0N/A restore_live_registers(sasm);
0N/A
0N/A __ leave();
304N/A __ addptr(rsp, BytesPerWord); // remove return address from stack
0N/A
0N/A // Forward the exception directly to deopt blob. We can blow no
0N/A // registers and must leave throwing pc on the stack. A patch may
0N/A // have values live in registers so the entry point with the
0N/A // exception in tls.
0N/A __ jump(RuntimeAddress(deopt_blob->unpack_with_exception_in_tls()));
0N/A
0N/A __ bind(L);
0N/A }
0N/A
0N/A
0N/A // Runtime will return true if the nmethod has been deoptimized during
0N/A // the patching process. In that case we must do a deopt reexecute instead.
0N/A
0N/A Label reexecuteEntry, cont;
0N/A
304N/A __ testptr(rax, rax); // have we deoptimized?
0N/A __ jcc(Assembler::equal, cont); // no
0N/A
0N/A // Will reexecute. Proper return address is already on the stack we just restore
0N/A // registers, pop all of our frame but the return address and jump to the deopt blob
0N/A restore_live_registers(sasm);
0N/A __ leave();
0N/A __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution()));
0N/A
0N/A __ bind(cont);
0N/A restore_live_registers(sasm);
0N/A __ leave();
0N/A __ ret(0);
0N/A
0N/A return oop_maps;
0N/A}
0N/A
0N/A
0N/AOopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
0N/A
0N/A // for better readability
0N/A const bool must_gc_arguments = true;
0N/A const bool dont_gc_arguments = false;
0N/A
0N/A // default value; overwritten for some optimized stubs that are called from methods that do not use the fpu
0N/A bool save_fpu_registers = true;
0N/A
0N/A // stub code & info for the different stubs
0N/A OopMapSet* oop_maps = NULL;
0N/A switch (id) {
0N/A case forward_exception_id:
0N/A {
2168N/A oop_maps = generate_handle_exception(id, sasm);
2168N/A __ leave();
2168N/A __ ret(0);
0N/A }
0N/A break;
0N/A
0N/A case new_instance_id:
0N/A case fast_new_instance_id:
0N/A case fast_new_instance_init_check_id:
0N/A {
0N/A Register klass = rdx; // Incoming
0N/A Register obj = rax; // Result
0N/A
0N/A if (id == new_instance_id) {
0N/A __ set_info("new_instance", dont_gc_arguments);
0N/A } else if (id == fast_new_instance_id) {
0N/A __ set_info("fast new_instance", dont_gc_arguments);
0N/A } else {
0N/A assert(id == fast_new_instance_init_check_id, "bad StubID");
0N/A __ set_info("fast new_instance init check", dont_gc_arguments);
0N/A }
0N/A
0N/A if ((id == fast_new_instance_id || id == fast_new_instance_init_check_id) &&
0N/A UseTLAB && FastTLABRefill) {
0N/A Label slow_path;
0N/A Register obj_size = rcx;
0N/A Register t1 = rbx;
0N/A Register t2 = rsi;
0N/A assert_different_registers(klass, obj, obj_size, t1, t2);
0N/A
304N/A __ push(rdi);
304N/A __ push(rbx);
0N/A
0N/A if (id == fast_new_instance_init_check_id) {
0N/A // make sure the klass is initialized
3051N/A __ cmpb(Address(klass, instanceKlass::init_state_offset()), instanceKlass::fully_initialized);
0N/A __ jcc(Assembler::notEqual, slow_path);
0N/A }
0N/A
0N/A#ifdef ASSERT
0N/A // assert object can be fast path allocated
0N/A {
0N/A Label ok, not_ok;
3042N/A __ movl(obj_size, Address(klass, Klass::layout_helper_offset()));
0N/A __ cmpl(obj_size, 0); // make sure it's an instance (LH > 0)
0N/A __ jcc(Assembler::lessEqual, not_ok);
0N/A __ testl(obj_size, Klass::_lh_instance_slow_path_bit);
0N/A __ jcc(Assembler::zero, ok);
0N/A __ bind(not_ok);
0N/A __ stop("assert(can be fast path allocated)");
0N/A __ should_not_reach_here();
0N/A __ bind(ok);
0N/A }
0N/A#endif // ASSERT
0N/A
0N/A // if we got here then the TLAB allocation failed, so try
0N/A // refilling the TLAB or allocating directly from eden.
0N/A Label retry_tlab, try_eden;
1988N/A const Register thread =
1988N/A __ tlab_refill(retry_tlab, try_eden, slow_path); // does not destroy rdx (klass), returns rdi
0N/A
0N/A __ bind(retry_tlab);
0N/A
304N/A // get the instance size (size is postive so movl is fine for 64bit)
3042N/A __ movl(obj_size, Address(klass, Klass::layout_helper_offset()));
1988N/A
0N/A __ tlab_allocate(obj, obj_size, 0, t1, t2, slow_path);
1988N/A
0N/A __ initialize_object(obj, klass, obj_size, 0, t1, t2);
0N/A __ verify_oop(obj);
304N/A __ pop(rbx);
304N/A __ pop(rdi);
0N/A __ ret(0);
0N/A
0N/A __ bind(try_eden);
304N/A // get the instance size (size is postive so movl is fine for 64bit)
3042N/A __ movl(obj_size, Address(klass, Klass::layout_helper_offset()));
1988N/A
0N/A __ eden_allocate(obj, obj_size, 0, t1, slow_path);
1988N/A __ incr_allocated_bytes(thread, obj_size, 0);
1988N/A
0N/A __ initialize_object(obj, klass, obj_size, 0, t1, t2);
0N/A __ verify_oop(obj);
304N/A __ pop(rbx);
304N/A __ pop(rdi);
0N/A __ ret(0);
0N/A
0N/A __ bind(slow_path);
304N/A __ pop(rbx);
304N/A __ pop(rdi);
0N/A }
0N/A
0N/A __ enter();
0N/A OopMap* map = save_live_registers(sasm, 2);
0N/A int call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_instance), klass);
0N/A oop_maps = new OopMapSet();
0N/A oop_maps->add_gc_map(call_offset, map);
0N/A restore_live_registers_except_rax(sasm);
0N/A __ verify_oop(obj);
0N/A __ leave();
0N/A __ ret(0);
0N/A
0N/A // rax,: new instance
0N/A }
0N/A
0N/A break;
0N/A
0N/A case counter_overflow_id:
0N/A {
1703N/A Register bci = rax, method = rbx;
0N/A __ enter();
1703N/A OopMap* map = save_live_registers(sasm, 3);
0N/A // Retrieve bci
0N/A __ movl(bci, Address(rbp, 2*BytesPerWord));
1703N/A // And a pointer to the methodOop
1703N/A __ movptr(method, Address(rbp, 3*BytesPerWord));
1703N/A int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), bci, method);
0N/A oop_maps = new OopMapSet();
0N/A oop_maps->add_gc_map(call_offset, map);
0N/A restore_live_registers(sasm);
0N/A __ leave();
0N/A __ ret(0);
0N/A }
0N/A break;
0N/A
0N/A case new_type_array_id:
0N/A case new_object_array_id:
0N/A {
0N/A Register length = rbx; // Incoming
0N/A Register klass = rdx; // Incoming
0N/A Register obj = rax; // Result
0N/A
0N/A if (id == new_type_array_id) {
0N/A __ set_info("new_type_array", dont_gc_arguments);
0N/A } else {
0N/A __ set_info("new_object_array", dont_gc_arguments);
0N/A }
0N/A
0N/A#ifdef ASSERT
0N/A // assert object type is really an array of the proper kind
0N/A {
0N/A Label ok;
0N/A Register t0 = obj;
3042N/A __ movl(t0, Address(klass, Klass::layout_helper_offset()));
0N/A __ sarl(t0, Klass::_lh_array_tag_shift);
0N/A int tag = ((id == new_type_array_id)
0N/A ? Klass::_lh_array_tag_type_value
0N/A : Klass::_lh_array_tag_obj_value);
0N/A __ cmpl(t0, tag);
0N/A __ jcc(Assembler::equal, ok);
0N/A __ stop("assert(is an array klass)");
0N/A __ should_not_reach_here();
0N/A __ bind(ok);
0N/A }
0N/A#endif // ASSERT
0N/A
0N/A if (UseTLAB && FastTLABRefill) {
0N/A Register arr_size = rsi;
0N/A Register t1 = rcx; // must be rcx for use as shift count
0N/A Register t2 = rdi;
0N/A Label slow_path;
0N/A assert_different_registers(length, klass, obj, arr_size, t1, t2);
0N/A
0N/A // check that array length is small enough for fast path.
0N/A __ cmpl(length, C1_MacroAssembler::max_array_allocation_length);
0N/A __ jcc(Assembler::above, slow_path);
0N/A
0N/A // if we got here then the TLAB allocation failed, so try
0N/A // refilling the TLAB or allocating directly from eden.
0N/A Label retry_tlab, try_eden;
1988N/A const Register thread =
1988N/A __ tlab_refill(retry_tlab, try_eden, slow_path); // preserves rbx & rdx, returns rdi
0N/A
0N/A __ bind(retry_tlab);
0N/A
0N/A // get the allocation size: round_up(hdr + length << (layout_helper & 0x1F))
1988N/A // since size is positive movl does right thing on 64bit
3042N/A __ movl(t1, Address(klass, Klass::layout_helper_offset()));
304N/A // since size is postive movl does right thing on 64bit
0N/A __ movl(arr_size, length);
0N/A assert(t1 == rcx, "fixed register usage");
304N/A __ shlptr(arr_size /* by t1=rcx, mod 32 */);
304N/A __ shrptr(t1, Klass::_lh_header_size_shift);
304N/A __ andptr(t1, Klass::_lh_header_size_mask);
304N/A __ addptr(arr_size, t1);
304N/A __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up
304N/A __ andptr(arr_size, ~MinObjAlignmentInBytesMask);
0N/A
0N/A __ tlab_allocate(obj, arr_size, 0, t1, t2, slow_path); // preserves arr_size
0N/A
0N/A __ initialize_header(obj, klass, length, t1, t2);
3042N/A __ movb(t1, Address(klass, in_bytes(Klass::layout_helper_offset()) + (Klass::_lh_header_size_shift / BitsPerByte)));
0N/A assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
0N/A assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise");
304N/A __ andptr(t1, Klass::_lh_header_size_mask);
304N/A __ subptr(arr_size, t1); // body length
304N/A __ addptr(t1, obj); // body start
0N/A __ initialize_body(t1, arr_size, 0, t2);
0N/A __ verify_oop(obj);
0N/A __ ret(0);
0N/A
0N/A __ bind(try_eden);
0N/A // get the allocation size: round_up(hdr + length << (layout_helper & 0x1F))
1988N/A // since size is positive movl does right thing on 64bit
3042N/A __ movl(t1, Address(klass, Klass::layout_helper_offset()));
304N/A // since size is postive movl does right thing on 64bit
0N/A __ movl(arr_size, length);
0N/A assert(t1 == rcx, "fixed register usage");
304N/A __ shlptr(arr_size /* by t1=rcx, mod 32 */);
304N/A __ shrptr(t1, Klass::_lh_header_size_shift);
304N/A __ andptr(t1, Klass::_lh_header_size_mask);
304N/A __ addptr(arr_size, t1);
304N/A __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up
304N/A __ andptr(arr_size, ~MinObjAlignmentInBytesMask);
0N/A
0N/A __ eden_allocate(obj, arr_size, 0, t1, slow_path); // preserves arr_size
1988N/A __ incr_allocated_bytes(thread, arr_size, 0);
0N/A
0N/A __ initialize_header(obj, klass, length, t1, t2);
3042N/A __ movb(t1, Address(klass, in_bytes(Klass::layout_helper_offset()) + (Klass::_lh_header_size_shift / BitsPerByte)));
0N/A assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
0N/A assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise");
304N/A __ andptr(t1, Klass::_lh_header_size_mask);
304N/A __ subptr(arr_size, t1); // body length
304N/A __ addptr(t1, obj); // body start
0N/A __ initialize_body(t1, arr_size, 0, t2);
0N/A __ verify_oop(obj);
0N/A __ ret(0);
0N/A
0N/A __ bind(slow_path);
0N/A }
0N/A
0N/A __ enter();
0N/A OopMap* map = save_live_registers(sasm, 3);
0N/A int call_offset;
0N/A if (id == new_type_array_id) {
0N/A call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_type_array), klass, length);
0N/A } else {
0N/A call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_object_array), klass, length);
0N/A }
0N/A
0N/A oop_maps = new OopMapSet();
0N/A oop_maps->add_gc_map(call_offset, map);
0N/A restore_live_registers_except_rax(sasm);
0N/A
0N/A __ verify_oop(obj);
0N/A __ leave();
0N/A __ ret(0);
0N/A
0N/A // rax,: new array
0N/A }
0N/A break;
0N/A
0N/A case new_multi_array_id:
0N/A { StubFrame f(sasm, "new_multi_array", dont_gc_arguments);
0N/A // rax,: klass
0N/A // rbx,: rank
0N/A // rcx: address of 1st dimension
0N/A OopMap* map = save_live_registers(sasm, 4);
0N/A int call_offset = __ call_RT(rax, noreg, CAST_FROM_FN_PTR(address, new_multi_array), rax, rbx, rcx);
0N/A
0N/A oop_maps = new OopMapSet();
0N/A oop_maps->add_gc_map(call_offset, map);
0N/A restore_live_registers_except_rax(sasm);
0N/A
0N/A // rax,: new multi array
0N/A __ verify_oop(rax);
0N/A }
0N/A break;
0N/A
0N/A case register_finalizer_id:
0N/A {
0N/A __ set_info("register_finalizer", dont_gc_arguments);
0N/A
304N/A // This is called via call_runtime so the arguments
304N/A // will be place in C abi locations
304N/A
304N/A#ifdef _LP64
304N/A __ verify_oop(c_rarg0);
304N/A __ mov(rax, c_rarg0);
304N/A#else
0N/A // The object is passed on the stack and we haven't pushed a
0N/A // frame yet so it's one work away from top of stack.
304N/A __ movptr(rax, Address(rsp, 1 * BytesPerWord));
0N/A __ verify_oop(rax);
304N/A#endif // _LP64
0N/A
0N/A // load the klass and check the has finalizer flag
0N/A Label register_finalizer;
0N/A Register t = rsi;
1909N/A __ load_klass(t, rax);
3042N/A __ movl(t, Address(t, Klass::access_flags_offset()));
0N/A __ testl(t, JVM_ACC_HAS_FINALIZER);
0N/A __ jcc(Assembler::notZero, register_finalizer);
0N/A __ ret(0);
0N/A
0N/A __ bind(register_finalizer);
0N/A __ enter();
0N/A OopMap* oop_map = save_live_registers(sasm, 2 /*num_rt_args */);
0N/A int call_offset = __ call_RT(noreg, noreg,
0N/A CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), rax);
0N/A oop_maps = new OopMapSet();
0N/A oop_maps->add_gc_map(call_offset, oop_map);
0N/A
0N/A // Now restore all the live registers
0N/A restore_live_registers(sasm);
0N/A
0N/A __ leave();
0N/A __ ret(0);
0N/A }
0N/A break;
0N/A
0N/A case throw_range_check_failed_id:
0N/A { StubFrame f(sasm, "range_check_failed", dont_gc_arguments);
0N/A oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true);
0N/A }
0N/A break;
0N/A
0N/A case throw_index_exception_id:
0N/A { StubFrame f(sasm, "index_range_check_failed", dont_gc_arguments);
0N/A oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true);
0N/A }
0N/A break;
0N/A
0N/A case throw_div0_exception_id:
0N/A { StubFrame f(sasm, "throw_div0_exception", dont_gc_arguments);
0N/A oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false);
0N/A }
0N/A break;
0N/A
0N/A case throw_null_pointer_exception_id:
0N/A { StubFrame f(sasm, "throw_null_pointer_exception", dont_gc_arguments);
0N/A oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false);
0N/A }
0N/A break;
0N/A
0N/A case handle_exception_nofpu_id:
0N/A case handle_exception_id:
0N/A { StubFrame f(sasm, "handle_exception", dont_gc_arguments);
2168N/A oop_maps = generate_handle_exception(id, sasm);
2168N/A }
2168N/A break;
2168N/A
2168N/A case handle_exception_from_callee_id:
2168N/A { StubFrame f(sasm, "handle_exception_from_callee", dont_gc_arguments);
2168N/A oop_maps = generate_handle_exception(id, sasm);
0N/A }
0N/A break;
0N/A
0N/A case unwind_exception_id:
0N/A { __ set_info("unwind_exception", dont_gc_arguments);
0N/A // note: no stubframe since we are about to leave the current
0N/A // activation and we are calling a leaf VM function only.
0N/A generate_unwind_exception(sasm);
0N/A }
0N/A break;
0N/A
0N/A case throw_array_store_exception_id:
0N/A { StubFrame f(sasm, "throw_array_store_exception", dont_gc_arguments);
0N/A // tos + 0: link
0N/A // + 1: return address
2053N/A oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true);
0N/A }
0N/A break;
0N/A
0N/A case throw_class_cast_exception_id:
0N/A { StubFrame f(sasm, "throw_class_cast_exception", dont_gc_arguments);
0N/A oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true);
0N/A }
0N/A break;
0N/A
0N/A case throw_incompatible_class_change_error_id:
0N/A { StubFrame f(sasm, "throw_incompatible_class_cast_exception", dont_gc_arguments);
0N/A oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false);
0N/A }
0N/A break;
0N/A
0N/A case slow_subtype_check_id:
0N/A {
644N/A // Typical calling sequence:
644N/A // __ push(klass_RInfo); // object klass or other subclass
644N/A // __ push(sup_k_RInfo); // array element klass or other superclass
644N/A // __ call(slow_subtype_check);
644N/A // Note that the subclass is pushed first, and is therefore deepest.
644N/A // Previous versions of this code reversed the names 'sub' and 'super'.
644N/A // This was operationally harmless but made the code unreadable.
0N/A enum layout {
304N/A rax_off, SLOT2(raxH_off)
304N/A rcx_off, SLOT2(rcxH_off)
304N/A rsi_off, SLOT2(rsiH_off)
304N/A rdi_off, SLOT2(rdiH_off)
304N/A // saved_rbp_off, SLOT2(saved_rbpH_off)
304N/A return_off, SLOT2(returnH_off)
644N/A sup_k_off, SLOT2(sup_kH_off)
644N/A klass_off, SLOT2(superH_off)
644N/A framesize,
644N/A result_off = klass_off // deepest argument is also the return value
0N/A };
0N/A
0N/A __ set_info("slow_subtype_check", dont_gc_arguments);
304N/A __ push(rdi);
304N/A __ push(rsi);
304N/A __ push(rcx);
304N/A __ push(rax);
0N/A
304N/A // This is called by pushing args and not with C abi
644N/A __ movptr(rsi, Address(rsp, (klass_off) * VMRegImpl::stack_slot_size)); // subclass
644N/A __ movptr(rax, Address(rsp, (sup_k_off) * VMRegImpl::stack_slot_size)); // superclass
0N/A
0N/A Label miss;
644N/A __ check_klass_subtype_slow_path(rsi, rax, rcx, rdi, NULL, &miss);
644N/A
644N/A // fallthrough on success:
644N/A __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), 1); // result
304N/A __ pop(rax);
304N/A __ pop(rcx);
304N/A __ pop(rsi);
304N/A __ pop(rdi);
0N/A __ ret(0);
0N/A
0N/A __ bind(miss);
644N/A __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), NULL_WORD); // result
304N/A __ pop(rax);
304N/A __ pop(rcx);
304N/A __ pop(rsi);
304N/A __ pop(rdi);
0N/A __ ret(0);
0N/A }
0N/A break;
0N/A
0N/A case monitorenter_nofpu_id:
0N/A save_fpu_registers = false;
0N/A // fall through
0N/A case monitorenter_id:
0N/A {
0N/A StubFrame f(sasm, "monitorenter", dont_gc_arguments);
0N/A OopMap* map = save_live_registers(sasm, 3, save_fpu_registers);
0N/A
304N/A // Called with store_parameter and not C abi
304N/A
0N/A f.load_argument(1, rax); // rax,: object
0N/A f.load_argument(0, rbx); // rbx,: lock address
0N/A
0N/A int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), rax, rbx);
0N/A
0N/A oop_maps = new OopMapSet();
0N/A oop_maps->add_gc_map(call_offset, map);
0N/A restore_live_registers(sasm, save_fpu_registers);
0N/A }
0N/A break;
0N/A
0N/A case monitorexit_nofpu_id:
0N/A save_fpu_registers = false;
0N/A // fall through
0N/A case monitorexit_id:
0N/A {
0N/A StubFrame f(sasm, "monitorexit", dont_gc_arguments);
0N/A OopMap* map = save_live_registers(sasm, 2, save_fpu_registers);
0N/A
304N/A // Called with store_parameter and not C abi
304N/A
0N/A f.load_argument(0, rax); // rax,: lock address
0N/A
0N/A // note: really a leaf routine but must setup last java sp
0N/A // => use call_RT for now (speed can be improved by
0N/A // doing last java sp setup manually)
0N/A int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), rax);
0N/A
0N/A oop_maps = new OopMapSet();
0N/A oop_maps->add_gc_map(call_offset, map);
0N/A restore_live_registers(sasm, save_fpu_registers);
2886N/A }
2886N/A break;
0N/A
2886N/A case deoptimize_id:
2886N/A {
2886N/A StubFrame f(sasm, "deoptimize", dont_gc_arguments);
2886N/A const int num_rt_args = 1; // thread
2886N/A OopMap* oop_map = save_live_registers(sasm, num_rt_args);
2886N/A int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize));
2886N/A oop_maps = new OopMapSet();
2886N/A oop_maps->add_gc_map(call_offset, oop_map);
2886N/A restore_live_registers(sasm);
2886N/A DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
2886N/A assert(deopt_blob != NULL, "deoptimization blob must have been created");
2886N/A __ leave();
2886N/A __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution()));
0N/A }
0N/A break;
0N/A
0N/A case access_field_patching_id:
0N/A { StubFrame f(sasm, "access_field_patching", dont_gc_arguments);
0N/A // we should set up register map
0N/A oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching));
0N/A }
0N/A break;
0N/A
0N/A case load_klass_patching_id:
0N/A { StubFrame f(sasm, "load_klass_patching", dont_gc_arguments);
0N/A // we should set up register map
0N/A oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching));
0N/A }
0N/A break;
0N/A
0N/A case dtrace_object_alloc_id:
0N/A { // rax,: object
0N/A StubFrame f(sasm, "dtrace_object_alloc", dont_gc_arguments);
0N/A // we can't gc here so skip the oopmap but make sure that all
0N/A // the live registers get saved.
0N/A save_live_registers(sasm, 1);
0N/A
304N/A __ NOT_LP64(push(rax)) LP64_ONLY(mov(c_rarg0, rax));
0N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_object_alloc)));
304N/A NOT_LP64(__ pop(rax));
0N/A
0N/A restore_live_registers(sasm);
0N/A }
0N/A break;
0N/A
0N/A case fpu2long_stub_id:
0N/A {
0N/A // rax, and rdx are destroyed, but should be free since the result is returned there
0N/A // preserve rsi,ecx
304N/A __ push(rsi);
304N/A __ push(rcx);
304N/A LP64_ONLY(__ push(rdx);)
0N/A
0N/A // check for NaN
0N/A Label return0, do_return, return_min_jlong, do_convert;
0N/A
304N/A Address value_high_word(rsp, wordSize + 4);
304N/A Address value_low_word(rsp, wordSize);
304N/A Address result_high_word(rsp, 3*wordSize + 4);
304N/A Address result_low_word(rsp, 3*wordSize);
0N/A
304N/A __ subptr(rsp, 32); // more than enough on 32bit
0N/A __ fst_d(value_low_word);
0N/A __ movl(rax, value_high_word);
0N/A __ andl(rax, 0x7ff00000);
0N/A __ cmpl(rax, 0x7ff00000);
0N/A __ jcc(Assembler::notEqual, do_convert);
0N/A __ movl(rax, value_high_word);
0N/A __ andl(rax, 0xfffff);
0N/A __ orl(rax, value_low_word);
0N/A __ jcc(Assembler::notZero, return0);
0N/A
0N/A __ bind(do_convert);
0N/A __ fnstcw(Address(rsp, 0));
304N/A __ movzwl(rax, Address(rsp, 0));
0N/A __ orl(rax, 0xc00);
0N/A __ movw(Address(rsp, 2), rax);
0N/A __ fldcw(Address(rsp, 2));
0N/A __ fwait();
0N/A __ fistp_d(result_low_word);
0N/A __ fldcw(Address(rsp, 0));
0N/A __ fwait();
304N/A // This gets the entire long in rax on 64bit
304N/A __ movptr(rax, result_low_word);
304N/A // testing of high bits
0N/A __ movl(rdx, result_high_word);
304N/A __ mov(rcx, rax);
0N/A // What the heck is the point of the next instruction???
0N/A __ xorl(rcx, 0x0);
0N/A __ movl(rsi, 0x80000000);
0N/A __ xorl(rsi, rdx);
0N/A __ orl(rcx, rsi);
0N/A __ jcc(Assembler::notEqual, do_return);
0N/A __ fldz();
0N/A __ fcomp_d(value_low_word);
0N/A __ fnstsw_ax();
304N/A#ifdef _LP64
304N/A __ testl(rax, 0x4100); // ZF & CF == 0
304N/A __ jcc(Assembler::equal, return_min_jlong);
304N/A#else
0N/A __ sahf();
0N/A __ jcc(Assembler::above, return_min_jlong);
304N/A#endif // _LP64
0N/A // return max_jlong
304N/A#ifndef _LP64
0N/A __ movl(rdx, 0x7fffffff);
0N/A __ movl(rax, 0xffffffff);
304N/A#else
304N/A __ mov64(rax, CONST64(0x7fffffffffffffff));
304N/A#endif // _LP64
0N/A __ jmp(do_return);
0N/A
0N/A __ bind(return_min_jlong);
304N/A#ifndef _LP64
0N/A __ movl(rdx, 0x80000000);
0N/A __ xorl(rax, rax);
304N/A#else
304N/A __ mov64(rax, CONST64(0x8000000000000000));
304N/A#endif // _LP64
0N/A __ jmp(do_return);
0N/A
0N/A __ bind(return0);
0N/A __ fpop();
304N/A#ifndef _LP64
304N/A __ xorptr(rdx,rdx);
304N/A __ xorptr(rax,rax);
304N/A#else
304N/A __ xorptr(rax, rax);
304N/A#endif // _LP64
0N/A
0N/A __ bind(do_return);
304N/A __ addptr(rsp, 32);
304N/A LP64_ONLY(__ pop(rdx);)
304N/A __ pop(rcx);
304N/A __ pop(rsi);
0N/A __ ret(0);
0N/A }
0N/A break;
0N/A
342N/A#ifndef SERIALGC
342N/A case g1_pre_barrier_slow_id:
342N/A {
342N/A StubFrame f(sasm, "g1_pre_barrier", dont_gc_arguments);
342N/A // arg0 : previous value of memory
342N/A
342N/A BarrierSet* bs = Universe::heap()->barrier_set();
342N/A if (bs->kind() != BarrierSet::G1SATBCTLogging) {
362N/A __ movptr(rax, (int)id);
342N/A __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax);
342N/A __ should_not_reach_here();
342N/A break;
342N/A }
362N/A __ push(rax);
362N/A __ push(rdx);
342N/A
342N/A const Register pre_val = rax;
362N/A const Register thread = NOT_LP64(rax) LP64_ONLY(r15_thread);
342N/A const Register tmp = rdx;
342N/A
362N/A NOT_LP64(__ get_thread(thread);)
342N/A
342N/A Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
342N/A PtrQueue::byte_offset_of_active()));
342N/A
342N/A Address queue_index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
342N/A PtrQueue::byte_offset_of_index()));
342N/A Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
342N/A PtrQueue::byte_offset_of_buf()));
342N/A
342N/A
342N/A Label done;
342N/A Label runtime;
342N/A
342N/A // Can we store original value in the thread's buffer?
342N/A
362N/A#ifdef _LP64
1492N/A __ movslq(tmp, queue_index);
362N/A __ cmpq(tmp, 0);
362N/A#else
342N/A __ cmpl(queue_index, 0);
362N/A#endif
342N/A __ jcc(Assembler::equal, runtime);
362N/A#ifdef _LP64
362N/A __ subq(tmp, wordSize);
362N/A __ movl(queue_index, tmp);
362N/A __ addq(tmp, buffer);
362N/A#else
342N/A __ subl(queue_index, wordSize);
342N/A __ movl(tmp, buffer);
342N/A __ addl(tmp, queue_index);
362N/A#endif
362N/A
342N/A // prev_val (rax)
342N/A f.load_argument(0, pre_val);
362N/A __ movptr(Address(tmp, 0), pre_val);
342N/A __ jmp(done);
342N/A
342N/A __ bind(runtime);
1492N/A __ push(rcx);
1492N/A#ifdef _LP64
1492N/A __ push(r8);
1492N/A __ push(r9);
1492N/A __ push(r10);
1492N/A __ push(r11);
1492N/A# ifndef _WIN64
1492N/A __ push(rdi);
1492N/A __ push(rsi);
1492N/A# endif
1492N/A#endif
342N/A // load the pre-value
342N/A f.load_argument(0, rcx);
342N/A __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), rcx, thread);
1492N/A#ifdef _LP64
1492N/A# ifndef _WIN64
1492N/A __ pop(rsi);
1492N/A __ pop(rdi);
1492N/A# endif
1492N/A __ pop(r11);
1492N/A __ pop(r10);
1492N/A __ pop(r9);
1492N/A __ pop(r8);
1492N/A#endif
362N/A __ pop(rcx);
1492N/A __ bind(done);
342N/A
362N/A __ pop(rdx);
362N/A __ pop(rax);
342N/A }
342N/A break;
342N/A
342N/A case g1_post_barrier_slow_id:
342N/A {
342N/A StubFrame f(sasm, "g1_post_barrier", dont_gc_arguments);
342N/A
342N/A
342N/A // arg0: store_address
342N/A Address store_addr(rbp, 2*BytesPerWord);
342N/A
342N/A BarrierSet* bs = Universe::heap()->barrier_set();
342N/A CardTableModRefBS* ct = (CardTableModRefBS*)bs;
342N/A Label done;
342N/A Label runtime;
342N/A
342N/A // At this point we know new_value is non-NULL and the new_value crosses regsion.
342N/A // Must check to see if card is already dirty
342N/A
362N/A const Register thread = NOT_LP64(rax) LP64_ONLY(r15_thread);
342N/A
342N/A Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
342N/A PtrQueue::byte_offset_of_index()));
342N/A Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
342N/A PtrQueue::byte_offset_of_buf()));
342N/A
362N/A __ push(rax);
1492N/A __ push(rcx);
342N/A
362N/A NOT_LP64(__ get_thread(thread);)
362N/A ExternalAddress cardtable((address)ct->byte_map_base);
342N/A assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
342N/A
1492N/A const Register card_addr = rcx;
362N/A#ifdef _LP64
362N/A const Register tmp = rscratch1;
362N/A f.load_argument(0, card_addr);
362N/A __ shrq(card_addr, CardTableModRefBS::card_shift);
362N/A __ lea(tmp, cardtable);
362N/A // get the address of the card
362N/A __ addq(card_addr, tmp);
362N/A#else
1492N/A const Register card_index = rcx;
362N/A f.load_argument(0, card_index);
362N/A __ shrl(card_index, CardTableModRefBS::card_shift);
362N/A
342N/A Address index(noreg, card_index, Address::times_1);
342N/A __ leal(card_addr, __ as_Address(ArrayAddress(cardtable, index)));
362N/A#endif
362N/A
342N/A __ cmpb(Address(card_addr, 0), 0);
342N/A __ jcc(Assembler::equal, done);
342N/A
342N/A // storing region crossing non-NULL, card is clean.
342N/A // dirty card and log.
342N/A
342N/A __ movb(Address(card_addr, 0), 0);
342N/A
342N/A __ cmpl(queue_index, 0);
342N/A __ jcc(Assembler::equal, runtime);
342N/A __ subl(queue_index, wordSize);
342N/A
342N/A const Register buffer_addr = rbx;
362N/A __ push(rbx);
362N/A
362N/A __ movptr(buffer_addr, buffer);
342N/A
362N/A#ifdef _LP64
362N/A __ movslq(rscratch1, queue_index);
362N/A __ addptr(buffer_addr, rscratch1);
362N/A#else
362N/A __ addptr(buffer_addr, queue_index);
362N/A#endif
362N/A __ movptr(Address(buffer_addr, 0), card_addr);
362N/A
362N/A __ pop(rbx);
342N/A __ jmp(done);
342N/A
342N/A __ bind(runtime);
1492N/A __ push(rdx);
1492N/A#ifdef _LP64
1492N/A __ push(r8);
1492N/A __ push(r9);
1492N/A __ push(r10);
1492N/A __ push(r11);
1492N/A# ifndef _WIN64
1492N/A __ push(rdi);
1492N/A __ push(rsi);
1492N/A# endif
1492N/A#endif
342N/A __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
1492N/A#ifdef _LP64
1492N/A# ifndef _WIN64
1492N/A __ pop(rsi);
1492N/A __ pop(rdi);
1492N/A# endif
1492N/A __ pop(r11);
1492N/A __ pop(r10);
1492N/A __ pop(r9);
1492N/A __ pop(r8);
1492N/A#endif
1492N/A __ pop(rdx);
1492N/A __ bind(done);
342N/A
1492N/A __ pop(rcx);
362N/A __ pop(rax);
342N/A
342N/A }
342N/A break;
342N/A#endif // !SERIALGC
342N/A
0N/A default:
0N/A { StubFrame f(sasm, "unimplemented entry", dont_gc_arguments);
304N/A __ movptr(rax, (int)id);
0N/A __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax);
0N/A __ should_not_reach_here();
0N/A }
0N/A break;
0N/A }
0N/A return oop_maps;
0N/A}
0N/A
0N/A#undef __
1601N/A
1601N/Aconst char *Runtime1::pd_name_for_address(address entry) {
1601N/A return "<unknown function>";
1601N/A}