0N/A/*
1879N/A * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A *
0N/A * This code is free software; you can redistribute it and/or modify it
0N/A * under the terms of the GNU General Public License version 2 only, as
0N/A * published by the Free Software Foundation.
0N/A *
0N/A * This code is distributed in the hope that it will be useful, but WITHOUT
0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A * version 2 for more details (a copy is included in the LICENSE file that
0N/A * accompanied this code).
0N/A *
0N/A * You should have received a copy of the GNU General Public License version
0N/A * 2 along with this work; if not, write to the Free Software Foundation,
0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0N/A *
1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1472N/A * or visit www.oracle.com if you need additional information or have any
1472N/A * questions.
0N/A *
0N/A */
0N/A
1879N/A#ifndef CPU_X86_VM_C1_DEFS_X86_HPP
1879N/A#define CPU_X86_VM_C1_DEFS_X86_HPP
1879N/A
0N/A// native word offsets from memory address (little endian)
0N/Aenum {
0N/A pd_lo_word_offset_in_bytes = 0,
0N/A pd_hi_word_offset_in_bytes = BytesPerWord
0N/A};
0N/A
0N/A// explicit rounding operations are required to implement the strictFP mode
0N/Aenum {
0N/A pd_strict_fp_requires_explicit_rounding = true
0N/A};
0N/A
0N/A
0N/A// registers
0N/Aenum {
304N/A pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers, // number of registers used during code emission
304N/A pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers, // number of registers used during code emission
304N/A pd_nof_xmm_regs_frame_map = XMMRegisterImpl::number_of_registers, // number of registers used during code emission
0N/A
304N/A#ifdef _LP64
304N/A #define UNALLOCATED 4 // rsp, rbp, r15, r10
304N/A#else
304N/A #define UNALLOCATED 2 // rsp, rbp
304N/A#endif // LP64
304N/A
304N/A pd_nof_caller_save_cpu_regs_frame_map = pd_nof_cpu_regs_frame_map - UNALLOCATED, // number of registers killed by calls
304N/A pd_nof_caller_save_fpu_regs_frame_map = pd_nof_fpu_regs_frame_map, // number of registers killed by calls
304N/A pd_nof_caller_save_xmm_regs_frame_map = pd_nof_xmm_regs_frame_map, // number of registers killed by calls
304N/A
304N/A pd_nof_cpu_regs_reg_alloc = pd_nof_caller_save_cpu_regs_frame_map, // number of registers that are visible to register allocator
0N/A pd_nof_fpu_regs_reg_alloc = 6, // number of registers that are visible to register allocator
0N/A
304N/A pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map, // number of registers visible to linear scan
304N/A pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan
304N/A pd_nof_xmm_regs_linearscan = pd_nof_xmm_regs_frame_map, // number of registers visible to linear scan
0N/A pd_first_cpu_reg = 0,
304N/A pd_last_cpu_reg = NOT_LP64(5) LP64_ONLY(11),
1909N/A pd_first_byte_reg = NOT_LP64(2) LP64_ONLY(0),
1909N/A pd_last_byte_reg = NOT_LP64(5) LP64_ONLY(11),
0N/A pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
0N/A pd_last_fpu_reg = pd_first_fpu_reg + 7,
0N/A pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map,
304N/A pd_last_xmm_reg = pd_first_xmm_reg + pd_nof_xmm_regs_frame_map - 1
0N/A};
0N/A
0N/A
0N/A// encoding of float value in debug info:
0N/Aenum {
0N/A pd_float_saved_as_double = true
0N/A};
1879N/A
1879N/A#endif // CPU_X86_VM_C1_DEFS_X86_HPP