0N/A/*
1499N/A * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A *
0N/A * This code is free software; you can redistribute it and/or modify it
0N/A * under the terms of the GNU General Public License version 2 only, as
0N/A * published by the Free Software Foundation.
0N/A *
0N/A * This code is distributed in the hope that it will be useful, but WITHOUT
0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A * version 2 for more details (a copy is included in the LICENSE file that
0N/A * accompanied this code).
0N/A *
0N/A * You should have received a copy of the GNU General Public License version
0N/A * 2 along with this work; if not, write to the Free Software Foundation,
0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0N/A *
1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1472N/A * or visit www.oracle.com if you need additional information or have any
1472N/A * questions.
0N/A *
0N/A */
0N/A
1879N/A#include "precompiled.hpp"
1879N/A#include "c1/c1_FrameMap.hpp"
1879N/A#include "c1/c1_LIR.hpp"
1879N/A#include "runtime/sharedRuntime.hpp"
1879N/A#include "vmreg_x86.inline.hpp"
0N/A
0N/Aconst int FrameMap::pd_c_runtime_reserved_arg_size = 0;
0N/A
0N/ALIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) {
0N/A LIR_Opr opr = LIR_OprFact::illegalOpr;
0N/A VMReg r_1 = reg->first();
0N/A VMReg r_2 = reg->second();
0N/A if (r_1->is_stack()) {
0N/A // Convert stack slot to an SP offset
0N/A // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
0N/A // so we must add it in here.
0N/A int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
0N/A opr = LIR_OprFact::address(new LIR_Address(rsp_opr, st_off, type));
0N/A } else if (r_1->is_Register()) {
0N/A Register reg = r_1->as_Register();
304N/A if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
0N/A Register reg2 = r_2->as_Register();
304N/A#ifdef _LP64
304N/A assert(reg2 == reg, "must be same register");
304N/A opr = as_long_opr(reg);
304N/A#else
0N/A opr = as_long_opr(reg2, reg);
304N/A#endif // _LP64
304N/A } else if (type == T_OBJECT || type == T_ARRAY) {
0N/A opr = as_oop_opr(reg);
0N/A } else {
0N/A opr = as_opr(reg);
0N/A }
0N/A } else if (r_1->is_FloatRegister()) {
0N/A assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
0N/A int num = r_1->as_FloatRegister()->encoding();
0N/A if (type == T_FLOAT) {
0N/A opr = LIR_OprFact::single_fpu(num);
0N/A } else {
0N/A opr = LIR_OprFact::double_fpu(num);
0N/A }
0N/A } else if (r_1->is_XMMRegister()) {
0N/A assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
0N/A int num = r_1->as_XMMRegister()->encoding();
0N/A if (type == T_FLOAT) {
0N/A opr = LIR_OprFact::single_xmm(num);
0N/A } else {
0N/A opr = LIR_OprFact::double_xmm(num);
0N/A }
0N/A } else {
0N/A ShouldNotReachHere();
0N/A }
0N/A return opr;
0N/A}
0N/A
0N/A
0N/ALIR_Opr FrameMap::rsi_opr;
0N/ALIR_Opr FrameMap::rdi_opr;
0N/ALIR_Opr FrameMap::rbx_opr;
0N/ALIR_Opr FrameMap::rax_opr;
0N/ALIR_Opr FrameMap::rdx_opr;
0N/ALIR_Opr FrameMap::rcx_opr;
0N/ALIR_Opr FrameMap::rsp_opr;
0N/ALIR_Opr FrameMap::rbp_opr;
0N/A
0N/ALIR_Opr FrameMap::receiver_opr;
0N/A
0N/ALIR_Opr FrameMap::rsi_oop_opr;
0N/ALIR_Opr FrameMap::rdi_oop_opr;
0N/ALIR_Opr FrameMap::rbx_oop_opr;
0N/ALIR_Opr FrameMap::rax_oop_opr;
0N/ALIR_Opr FrameMap::rdx_oop_opr;
0N/ALIR_Opr FrameMap::rcx_oop_opr;
0N/A
304N/ALIR_Opr FrameMap::long0_opr;
304N/ALIR_Opr FrameMap::long1_opr;
0N/ALIR_Opr FrameMap::fpu0_float_opr;
0N/ALIR_Opr FrameMap::fpu0_double_opr;
0N/ALIR_Opr FrameMap::xmm0_float_opr;
0N/ALIR_Opr FrameMap::xmm0_double_opr;
0N/A
304N/A#ifdef _LP64
304N/A
304N/ALIR_Opr FrameMap::r8_opr;
304N/ALIR_Opr FrameMap::r9_opr;
304N/ALIR_Opr FrameMap::r10_opr;
304N/ALIR_Opr FrameMap::r11_opr;
304N/ALIR_Opr FrameMap::r12_opr;
304N/ALIR_Opr FrameMap::r13_opr;
304N/ALIR_Opr FrameMap::r14_opr;
304N/ALIR_Opr FrameMap::r15_opr;
304N/A
304N/A// r10 and r15 can never contain oops since they aren't available to
304N/A// the allocator
304N/ALIR_Opr FrameMap::r8_oop_opr;
304N/ALIR_Opr FrameMap::r9_oop_opr;
304N/ALIR_Opr FrameMap::r11_oop_opr;
304N/ALIR_Opr FrameMap::r12_oop_opr;
304N/ALIR_Opr FrameMap::r13_oop_opr;
304N/ALIR_Opr FrameMap::r14_oop_opr;
304N/A#endif // _LP64
304N/A
0N/ALIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
0N/ALIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
0N/ALIR_Opr FrameMap::_caller_save_xmm_regs[] = { 0, };
0N/A
304N/AXMMRegister FrameMap::_xmm_regs [] = { 0, };
0N/A
0N/AXMMRegister FrameMap::nr2xmmreg(int rnr) {
0N/A assert(_init_done, "tables not initialized");
0N/A return _xmm_regs[rnr];
0N/A}
0N/A
0N/A//--------------------------------------------------------
0N/A// FrameMap
0N/A//--------------------------------------------------------
0N/A
1504N/Avoid FrameMap::initialize() {
1504N/A assert(!_init_done, "once");
0N/A
304N/A assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers");
304N/A map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0);
304N/A map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1);
304N/A map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2);
304N/A map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3);
304N/A map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4);
304N/A map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5);
0N/A
304N/A#ifndef _LP64
304N/A // The unallocatable registers are at the end
304N/A map_register(6, rsp);
304N/A map_register(7, rbp);
304N/A#else
304N/A map_register( 6, r8); r8_opr = LIR_OprFact::single_cpu(6);
304N/A map_register( 7, r9); r9_opr = LIR_OprFact::single_cpu(7);
304N/A map_register( 8, r11); r11_opr = LIR_OprFact::single_cpu(8);
1909N/A map_register( 9, r13); r13_opr = LIR_OprFact::single_cpu(9);
1909N/A map_register(10, r14); r14_opr = LIR_OprFact::single_cpu(10);
1909N/A // r12 is allocated conditionally. With compressed oops it holds
1909N/A // the heapbase value and is not visible to the allocator.
1909N/A map_register(11, r12); r12_opr = LIR_OprFact::single_cpu(11);
304N/A // The unallocatable registers are at the end
304N/A map_register(12, r10); r10_opr = LIR_OprFact::single_cpu(12);
304N/A map_register(13, r15); r15_opr = LIR_OprFact::single_cpu(13);
304N/A map_register(14, rsp);
304N/A map_register(15, rbp);
304N/A#endif // _LP64
304N/A
304N/A#ifdef _LP64
304N/A long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/);
304N/A long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/);
304N/A#else
304N/A long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
304N/A long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
304N/A#endif // _LP64
0N/A fpu0_float_opr = LIR_OprFact::single_fpu(0);
0N/A fpu0_double_opr = LIR_OprFact::double_fpu(0);
0N/A xmm0_float_opr = LIR_OprFact::single_xmm(0);
0N/A xmm0_double_opr = LIR_OprFact::double_xmm(0);
0N/A
0N/A _caller_save_cpu_regs[0] = rsi_opr;
0N/A _caller_save_cpu_regs[1] = rdi_opr;
0N/A _caller_save_cpu_regs[2] = rbx_opr;
0N/A _caller_save_cpu_regs[3] = rax_opr;
0N/A _caller_save_cpu_regs[4] = rdx_opr;
0N/A _caller_save_cpu_regs[5] = rcx_opr;
0N/A
304N/A#ifdef _LP64
304N/A _caller_save_cpu_regs[6] = r8_opr;
304N/A _caller_save_cpu_regs[7] = r9_opr;
304N/A _caller_save_cpu_regs[8] = r11_opr;
1909N/A _caller_save_cpu_regs[9] = r13_opr;
1909N/A _caller_save_cpu_regs[10] = r14_opr;
1909N/A _caller_save_cpu_regs[11] = r12_opr;
304N/A#endif // _LP64
304N/A
0N/A
0N/A _xmm_regs[0] = xmm0;
0N/A _xmm_regs[1] = xmm1;
0N/A _xmm_regs[2] = xmm2;
0N/A _xmm_regs[3] = xmm3;
0N/A _xmm_regs[4] = xmm4;
0N/A _xmm_regs[5] = xmm5;
0N/A _xmm_regs[6] = xmm6;
0N/A _xmm_regs[7] = xmm7;
0N/A
304N/A#ifdef _LP64
304N/A _xmm_regs[8] = xmm8;
304N/A _xmm_regs[9] = xmm9;
304N/A _xmm_regs[10] = xmm10;
304N/A _xmm_regs[11] = xmm11;
304N/A _xmm_regs[12] = xmm12;
304N/A _xmm_regs[13] = xmm13;
304N/A _xmm_regs[14] = xmm14;
304N/A _xmm_regs[15] = xmm15;
304N/A#endif // _LP64
304N/A
0N/A for (int i = 0; i < 8; i++) {
0N/A _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
304N/A }
304N/A
304N/A for (int i = 0; i < nof_caller_save_xmm_regs ; i++) {
0N/A _caller_save_xmm_regs[i] = LIR_OprFact::single_xmm(i);
0N/A }
0N/A
0N/A _init_done = true;
0N/A
304N/A rsi_oop_opr = as_oop_opr(rsi);
304N/A rdi_oop_opr = as_oop_opr(rdi);
304N/A rbx_oop_opr = as_oop_opr(rbx);
304N/A rax_oop_opr = as_oop_opr(rax);
304N/A rdx_oop_opr = as_oop_opr(rdx);
304N/A rcx_oop_opr = as_oop_opr(rcx);
304N/A
304N/A rsp_opr = as_pointer_opr(rsp);
304N/A rbp_opr = as_pointer_opr(rbp);
304N/A
304N/A#ifdef _LP64
304N/A r8_oop_opr = as_oop_opr(r8);
304N/A r9_oop_opr = as_oop_opr(r9);
304N/A r11_oop_opr = as_oop_opr(r11);
304N/A r12_oop_opr = as_oop_opr(r12);
304N/A r13_oop_opr = as_oop_opr(r13);
304N/A r14_oop_opr = as_oop_opr(r14);
304N/A#endif // _LP64
304N/A
0N/A VMRegPair regs;
0N/A BasicType sig_bt = T_OBJECT;
0N/A SharedRuntime::java_calling_convention(&sig_bt, &regs, 1, true);
0N/A receiver_opr = as_oop_opr(regs.first()->as_Register());
304N/A
0N/A}
0N/A
0N/A
0N/AAddress FrameMap::make_new_address(ByteSize sp_offset) const {
0N/A // for rbp, based address use this:
0N/A // return Address(rbp, in_bytes(sp_offset) - (framesize() - 2) * 4);
0N/A return Address(rsp, in_bytes(sp_offset));
0N/A}
0N/A
0N/A
0N/A// ----------------mapping-----------------------
0N/A// all mapping is based on rbp, addressing, except for simple leaf methods where we access
0N/A// the locals rsp based (and no frame is built)
0N/A
0N/A
0N/A// Frame for simple leaf methods (quick entries)
0N/A//
0N/A// +----------+
0N/A// | ret addr | <- TOS
0N/A// +----------+
0N/A// | args |
0N/A// | ...... |
0N/A
0N/A// Frame for standard methods
0N/A//
0N/A// | .........| <- TOS
0N/A// | locals |
0N/A// +----------+
0N/A// | old rbp, | <- EBP
0N/A// +----------+
0N/A// | ret addr |
0N/A// +----------+
0N/A// | args |
0N/A// | .........|
0N/A
0N/A
0N/A// For OopMaps, map a local variable or spill index to an VMRegImpl name.
0N/A// This is the offset from sp() in the frame of the slot for the index,
0N/A// skewed by VMRegImpl::stack0 to indicate a stack location (vs.a register.)
0N/A//
0N/A// framesize +
0N/A// stack0 stack0 0 <- VMReg
0N/A// | | <registers> |
0N/A// ...........|..............|.............|
0N/A// 0 1 2 3 x x 4 5 6 ... | <- local indices
0N/A// ^ ^ sp() ( x x indicate link
0N/A// | | and return addr)
0N/A// arguments non-argument locals
0N/A
0N/A
0N/AVMReg FrameMap::fpu_regname (int n) {
0N/A // Return the OptoReg name for the fpu stack slot "n"
0N/A // A spilled fpu stack slot comprises to two single-word OptoReg's.
0N/A return as_FloatRegister(n)->as_VMReg();
0N/A}
0N/A
0N/ALIR_Opr FrameMap::stack_pointer() {
0N/A return FrameMap::rsp_opr;
0N/A}
0N/A
0N/A
1484N/A// JSR 292
1484N/ALIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {
1484N/A assert(rbp == rbp_mh_SP_save, "must be same register");
1484N/A return rbp_opr;
1484N/A}
1484N/A
1484N/A
0N/Abool FrameMap::validate_frame() {
0N/A return true;
0N/A}