/*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
#include "precompiled.hpp"
#include "assembler_x86.inline.hpp"
#include "memory/resourceArea.hpp"
#include "nativeInst_x86.hpp"
#include "oops/oop.inline.hpp"
#include "runtime/handles.hpp"
#include "runtime/sharedRuntime.hpp"
#include "runtime/stubRoutines.hpp"
#include "utilities/ostream.hpp"
#ifdef COMPILER1
#include "c1/c1_Runtime1.hpp"
#endif
}
// Make sure code pattern is actually a call imm32 instruction.
if (inst != instruction_code) {
inst);
fatal("not a call disp32");
}
}
// Getting the destination of a call isn't safe because that call can
// be getting patched while you're calling this. There's only special
// places where this can be called but not automatically verifiable by
// checking which locks are held. The solution is true atomic patching
// on x86, nyi.
return return_address() + displacement();
}
instruction_address(), destination());
}
// Inserts a native call instruction at a given pc
#ifdef AMD64
#endif // AMD64
}
// MT-safe patching of a call instruction.
// First patches first word of instruction to two jmp's that jmps to them
// selfs (spinlock). Then patches the last byte, and then atomicly replaces
// the jmp's with the first 4 byte of the new instruction.
}
// First patch dummy jmp in place
// First patch dummy jmp in place
// Invalidate. Opteron requires a flush after every write.
// Patch 4th byte
// Patch bytes 0-3
#ifdef ASSERT
// verify patching
for ( int i = 0; i < instruction_size; i++) {
}
#endif
}
// Similar to replace_mt_safe, but just changes the destination. The
// important thing is that free-running threads are able to execute this
// call instruction at all times. If the displacement field is aligned
// we can simply rely on atomicity of 32-bit writes to make sure other threads
// will see no intermediate states. Otherwise, the first two bytes of the
// call are guaranteed to be aligned, and can be atomically patched to a
// self-loop to guard the instruction while we change the other bytes.
// We cannot rely on locks here, since the free-running threads must run at
// full speed.
//
// Used in the runtime linkage of calls; see class CompiledIC.
// (Cf. 4506997 and 4479829, where threads witnessed garbage displacements.)
debug_only(verify());
// Make sure patching code is locked. No two threads can patch at the same
// time but one may be executing this code.
// Both C1 and C2 should now be generating code which aligns the patched address
// to be within a single cache line except that C1 does not do the alignment on
// uniprocessor systems.
if (is_aligned) {
// Simple case: The destination lies within a single cache line.
// Tricky case: The instruction prefix lies within a single cache line.
#ifdef AMD64
#endif // AMD64
// First patch dummy jump in place:
{
*(short*)instruction_address() = *(short*)patch_jump;
}
// Invalidate. Opteron requires a flush after every write.
wrote(0);
// (Note: We assume any reader which has already started to read
// the unpatched call will completely read the whole unpatched call
// without seeing the next writes we are about to make.)
// Next, patch the last three bytes:
patch_disp[0] = call_opcode;
for (int i = sizeof(short); i < instruction_size; i++)
instruction_address()[i] = patch_disp[i];
// Invalidate. Opteron requires a flush after every write.
wrote(sizeof(short));
// (Note: We assume that any reader which reads the opcode we are
// about to repatch will also read the writes we just made.)
// Finally, overwrite the jump:
*(short*)instruction_address() = *(short*)patch_disp;
// Invalidate. Opteron requires a flush after every write.
wrote(0);
debug_only(verify());
} else {
// Impossible: One or the other must be atomically writable.
}
}
#ifdef AMD64
// make sure code pattern is actually a mov reg64, imm64 instruction
print();
fatal("not a REX.W[B] mov reg64, imm64");
}
#else
// make sure code pattern is actually a mov reg, imm32 instruction
#endif // AMD64
}
instruction_address(), data());
}
//-------------------------------------------------------------------
int off = 0;
// See comment in Assembler::locate_operand() about VEX prefixes.
if (instr_0 == instruction_VEX_prefix_2bytes) {
return 2;
}
if (instr_0 == instruction_VEX_prefix_3bytes) {
return 3;
}
// First check to see if we have a (prefixed or not) xor
off++;
}
if (instr_0 == instruction_code_xor) {
off += 2;
}
off++; // Not SSE instructions
}
off++;
}
off++;
}
off++;
}
return off;
}
return addr_at(instruction_start());
}
switch (instr_0) {
fatal("should have skipped instruction_operandsize_prefix");
break;
fatal("should have skipped instruction_extended_prefix");
break;
case instruction_code_mem2reg_movslq: // 0x63
case instruction_code_mem2reg_movzxb: // 0xB6
case instruction_code_mem2reg_movsxb: // 0xBE
case instruction_code_mem2reg_movzxw: // 0xB7
case instruction_code_mem2reg_movsxw: // 0xBF
case instruction_code_reg2mem: // 0x89 (q/l)
case instruction_code_mem2reg: // 0x8B (q/l)
case instruction_code_reg2memb: // 0x88
case instruction_code_mem2regb: // 0x8a
case instruction_code_float_s: // 0xd9 fld_s a
case instruction_code_float_d: // 0xdd fld_d a
case instruction_code_xmm_load: // 0x10
case instruction_code_xmm_store: // 0x11
case instruction_code_xmm_lpd: // 0x12
{
// If there is an SIB then instruction is longer than expected
ret++;
}
}
case instruction_code_xor:
fatal("should have skipped xor lead in");
break;
default:
fatal("not a NativeMovRegMem");
}
return ret;
}
// the encoding to use an SIB byte. Which will have the nnnn
// field off by one byte
off++;
}
}
// the encoding to use an SIB byte. Which will have the nnnn
// field off by one byte
off++;
}
set_int_at(off, x);
}
// make sure code pattern is actually a mov [reg+offset], reg instruction
switch (test_byte) {
case instruction_code_reg2memb: // 0x88 movb a, r
case instruction_code_reg2mem: // 0x89 movl a, r (can be movq in 64bit)
case instruction_code_mem2regb: // 0x8a movb r, a
case instruction_code_mem2reg: // 0x8b movl r, a (can be movq in 64bit)
break;
case instruction_code_mem2reg_movslq: // 0x63 movsql r, a
case instruction_code_mem2reg_movzxb: // 0xb6 movzbl r, a (movzxb)
case instruction_code_mem2reg_movzxw: // 0xb7 movzwl r, a (movzxw)
case instruction_code_mem2reg_movsxb: // 0xbe movsbl r, a (movsxb)
case instruction_code_mem2reg_movsxw: // 0xbf movswl r, a (movsxw)
break;
case instruction_code_float_s: // 0xd9 fld_s a
case instruction_code_float_d: // 0xdd fld_d a
case instruction_code_xmm_load: // 0x10 movsd xmm, a
case instruction_code_xmm_store: // 0x11 movsd a, xmm
case instruction_code_xmm_lpd: // 0x12 movlpd xmm, a
break;
default:
fatal ("not a mov [reg+offs], reg instruction");
}
}
}
//-------------------------------------------------------------------
// make sure code pattern is actually a mov [reg+offset], reg instruction
#ifdef _LP64
if ( (test_byte == instruction_prefix_wide ||
}
#endif // _LP64
if ( ! ((test_byte == lea_instruction_code)
fatal ("not a lea reg, [reg+offs] instruction");
}
}
}
//--------------------------------------------------------------------------------
fatal("not a jump instruction");
}
}
#ifdef AMD64
#endif // AMD64
}
// Patching to not_entrant can happen while activations of the method are
// in use. The patching in that instance must happen only when certain
// alignment restrictions are true. These guarantees check those
// conditions.
#ifdef AMD64
#else
const int linesize = 32;
#endif // AMD64
// Must be wordSize aligned
"illegal address for code patching 2");
// First 5 bytes must be within the same cache line - 4827828
"illegal address for code patching 3");
}
// MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie)
// The problem: jmp <dest> is a 5-byte instruction. Atomical write can be only with 4 bytes.
// First patches the first word atomically to be a jump to itself.
// Then patches the last byte and then atomically patches the first word (4-bytes),
// thus inserting the desired jump
// This code is mt-safe with the following conditions: entry point is 4 byte aligned,
// entry point is in same cache line as unverified entry point, and the instruction being
// patched is >= 5 byte (size of patch).
//
// In C2 the 5+ byte sized instruction is enforced by code in MachPrologNode::emit.
// In C1 the restriction is enforced by CodeEmitter::method_entry
//
// complete jump instruction (to be inserted) is in code_buffer;
code_buffer[0] = instruction_code;
#ifdef AMD64
#endif // AMD64
// Can't call nativeJump_at() because it's asserts jump exists
//First patch dummy jmp in place
// First patch dummy jmp in place
// Patch 5th byte (from jump instruction)
// Patch bytes 0-3 (from jump instruction)
// Invalidate. Opteron requires a flush after every write.
}
}
assert(NativeIllegalInstruction::instruction_size == sizeof(short), "right address unit for update");
*(short *)code_pos = instruction_code;
}
}
#ifdef AMD64
#endif // AMD64
}
// MT-safe patching of a long jump instruction.
// First patches first word of instruction to two jmp's that jmps to them
// selfs (spinlock). Then patches the last byte, and then atomicly replaces
// the jmp's with the first 4 byte of the new instruction.
// Temporary code
// First patch dummy jmp in place
// Patch 4th byte
// Patch bytes 0-3
#ifdef ASSERT
// verify patching
for ( int i = 0; i < instruction_size; i++) {
}
#endif
}
if (is_rel32off)
else
}
}