1879N/A * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. 0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 0N/A * This code is free software; you can redistribute it and/or modify it 0N/A * under the terms of the GNU General Public License version 2 only, as 0N/A * published by the Free Software Foundation. 0N/A * This code is distributed in the hope that it will be useful, but WITHOUT 0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 0N/A * version 2 for more details (a copy is included in the LICENSE file that 0N/A * accompanied this code). 0N/A * You should have received a copy of the GNU General Public License version 0N/A * 2 along with this work; if not, write to the Free Software Foundation, 0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 0N/A // Make sure code pattern is actually a call imm32 instruction. 0N/A // Getting the destination of a call isn't safe because that call can 0N/A // be getting patched while you're calling this. There's only special 0N/A // places where this can be called but not automatically verifiable by 0N/A // checking which locks are held. The solution is true atomic patching 0N/A// Inserts a native call instruction at a given pc 0N/A// MT-safe patching of a call instruction. 0N/A// First patches first word of instruction to two jmp's that jmps to them 0N/A// selfs (spinlock). Then patches the last byte, and then atomicly replaces 0N/A// the jmp's with the first 4 byte of the new instruction. 0N/A // First patch dummy jmp in place 0N/A // First patch dummy jmp in place 0N/A // Invalidate. Opteron requires a flush after every write. 0N/A// Similar to replace_mt_safe, but just changes the destination. The 0N/A// important thing is that free-running threads are able to execute this 0N/A// call instruction at all times. If the displacement field is aligned 0N/A// we can simply rely on atomicity of 32-bit writes to make sure other threads 0N/A// will see no intermediate states. Otherwise, the first two bytes of the 0N/A// call are guaranteed to be aligned, and can be atomically patched to a 0N/A// self-loop to guard the instruction while we change the other bytes. 0N/A// We cannot rely on locks here, since the free-running threads must run at 0N/A// Used in the runtime linkage of calls; see class CompiledIC. 0N/A// (Cf. 4506997 and 4479829, where threads witnessed garbage displacements.) 0N/A // Make sure patching code is locked. No two threads can patch at the same 0N/A // time but one may be executing this code. 0N/A // Both C1 and C2 should now be generating code which aligns the patched address 0N/A // to be within a single cache line except that C1 does not do the alignment on 0N/A // uniprocessor systems. 0N/A // Simple case: The destination lies within a single cache line. 0N/A // Tricky case: The instruction prefix lies within a single cache line. 0N/A // First patch dummy jump in place: 0N/A // Invalidate. Opteron requires a flush after every write. 0N/A // (Note: We assume any reader which has already started to read 0N/A // the unpatched call will completely read the whole unpatched call 0N/A // without seeing the next writes we are about to make.) 0N/A // Next, patch the last three bytes: 0N/A // Invalidate. Opteron requires a flush after every write. 0N/A // (Note: We assume that any reader which reads the opcode we are 0N/A // about to repatch will also read the writes we just made.) 0N/A // Finally, overwrite the jump: 0N/A // Invalidate. Opteron requires a flush after every write. 0N/A // Impossible: One or the other must be atomically writable. 0N/A // make sure code pattern is actually a mov reg64, imm64 instruction 0N/A fatal(
"not a REX.W[B] mov reg64, imm64");
0N/A // make sure code pattern is actually a mov reg, imm32 instruction 0N/A//------------------------------------------------------------------- 3039N/A // See comment in Assembler::locate_operand() about VEX prefixes. 304N/A // First check to see if we have a (prefixed or not) xor 304N/A // Now look for the real instruction and the many prefix/size specifiers. 304N/A fatal(
"should have skipped instruction_operandsize_prefix");
304N/A fatal(
"should have skipped instruction_extended_prefix");
304N/A // If there is an SIB then instruction is longer than expected 304N/A // nnnn(r12|rsp) isn't coded as simple mod/rm since that is 304N/A // the encoding to use an SIB byte. Which will have the nnnn 304N/A // field off by one byte 304N/A // nnnn(r12|rsp) isn't coded as simple mod/rm since that is 304N/A // the encoding to use an SIB byte. Which will have the nnnn 304N/A // field off by one byte 0N/A // make sure code pattern is actually a mov [reg+offset], reg instruction 0N/A fatal (
"not a mov [reg+offs], reg instruction");
0N/A//------------------------------------------------------------------- 0N/A // make sure code pattern is actually a mov [reg+offset], reg instruction 0N/A fatal (
"not a lea reg, [reg+offs] instruction");
0N/A//-------------------------------------------------------------------------------- 0N/A // Patching to not_entrant can happen while activations of the method are 0N/A // in use. The patching in that instance must happen only when certain 0N/A // alignment restrictions are true. These guarantees check those 0N/A // Must be wordSize aligned 0N/A "illegal address for code patching 2");
0N/A // First 5 bytes must be within the same cache line - 4827828 0N/A "illegal address for code patching 3");
0N/A// MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie) 0N/A// The problem: jmp <dest> is a 5-byte instruction. Atomical write can be only with 4 bytes. 0N/A// First patches the first word atomically to be a jump to itself. 0N/A// Then patches the last byte and then atomically patches the first word (4-bytes), 0N/A// thus inserting the desired jump 0N/A// This code is mt-safe with the following conditions: entry point is 4 byte aligned, 0N/A// entry point is in same cache line as unverified entry point, and the instruction being 0N/A// patched is >= 5 byte (size of patch). 0N/A// In C2 the 5+ byte sized instruction is enforced by code in MachPrologNode::emit. 0N/A// In C1 the restriction is enforced by CodeEmitter::method_entry 0N/A // complete jump instruction (to be inserted) is in code_buffer; 0N/A // Can't call nativeJump_at() because it's asserts jump exists 0N/A //First patch dummy jmp in place 0N/A // First patch dummy jmp in place 0N/A // Patch 5th byte (from jump instruction) 0N/A // Patch bytes 0-3 (from jump instruction) 0N/A // Invalidate. Opteron requires a flush after every write. 0N/A// MT-safe patching of a long jump instruction. 0N/A// First patches first word of instruction to two jmp's that jmps to them 0N/A// selfs (spinlock). Then patches the last byte, and then atomicly replaces 0N/A// the jmp's with the first 4 byte of the new instruction. 0N/A // First patch dummy jmp in place