0N/A/*
3158N/A * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A *
0N/A * This code is free software; you can redistribute it and/or modify it
0N/A * under the terms of the GNU General Public License version 2 only, as
0N/A * published by the Free Software Foundation.
0N/A *
0N/A * This code is distributed in the hope that it will be useful, but WITHOUT
0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A * version 2 for more details (a copy is included in the LICENSE file that
0N/A * accompanied this code).
0N/A *
0N/A * You should have received a copy of the GNU General Public License version
0N/A * 2 along with this work; if not, write to the Free Software Foundation,
0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0N/A *
1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1472N/A * or visit www.oracle.com if you need additional information or have any
1472N/A * questions.
0N/A *
0N/A */
0N/A
1879N/A#include "precompiled.hpp"
1879N/A#include "asm/assembler.hpp"
1879N/A#include "assembler_x86.inline.hpp"
1879N/A#include "code/debugInfoRec.hpp"
1879N/A#include "code/icBuffer.hpp"
1879N/A#include "code/vtableStubs.hpp"
1879N/A#include "interpreter/interpreter.hpp"
1879N/A#include "oops/compiledICHolderOop.hpp"
1879N/A#include "prims/jvmtiRedefineClassesTrace.hpp"
1879N/A#include "runtime/sharedRuntime.hpp"
1879N/A#include "runtime/vframeArray.hpp"
1879N/A#include "vmreg_x86.inline.hpp"
1879N/A#ifdef COMPILER1
1879N/A#include "c1/c1_Runtime1.hpp"
1879N/A#endif
1879N/A#ifdef COMPILER2
1879N/A#include "opto/runtime.hpp"
1879N/A#endif
0N/A
0N/A#define __ masm->
0N/A
524N/Aconst int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size;
524N/A
0N/Aclass RegisterSaver {
0N/A // Capture info about frame layout
4012N/A#define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off
0N/A enum layout {
0N/A fpu_state_off = 0,
4012N/A fpu_state_end = fpu_state_off+FPUStateSizeInWords,
0N/A st0_off, st0H_off,
0N/A st1_off, st1H_off,
0N/A st2_off, st2H_off,
0N/A st3_off, st3H_off,
0N/A st4_off, st4H_off,
0N/A st5_off, st5H_off,
0N/A st6_off, st6H_off,
0N/A st7_off, st7H_off,
4012N/A xmm_off,
4012N/A DEF_XMM_OFFS(0),
4012N/A DEF_XMM_OFFS(1),
4012N/A DEF_XMM_OFFS(2),
4012N/A DEF_XMM_OFFS(3),
4012N/A DEF_XMM_OFFS(4),
4012N/A DEF_XMM_OFFS(5),
4012N/A DEF_XMM_OFFS(6),
4012N/A DEF_XMM_OFFS(7),
4012N/A flags_off = xmm7_off + 16/BytesPerInt + 1, // 16-byte stack alignment fill word
0N/A rdi_off,
0N/A rsi_off,
0N/A ignore_off, // extra copy of rbp,
0N/A rsp_off,
0N/A rbx_off,
0N/A rdx_off,
0N/A rcx_off,
0N/A rax_off,
0N/A // The frame sender code expects that rbp will be in the "natural" place and
0N/A // will override any oopMap setting for it. We must therefore force the layout
0N/A // so that it agrees with the frame sender code.
0N/A rbp_off,
0N/A return_off, // slot for return address
0N/A reg_save_size };
4012N/A enum { FPU_regs_live = flags_off - fpu_state_end };
0N/A
0N/A public:
0N/A
0N/A static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words,
4012N/A int* total_frame_words, bool verify_fpu = true, bool save_vectors = false);
4012N/A static void restore_live_registers(MacroAssembler* masm, bool restore_vectors = false);
0N/A
0N/A static int rax_offset() { return rax_off; }
0N/A static int rbx_offset() { return rbx_off; }
0N/A
0N/A // Offsets into the register save area
0N/A // Used by deoptimization when it is managing result register
0N/A // values on its own
0N/A
0N/A static int raxOffset(void) { return rax_off; }
0N/A static int rdxOffset(void) { return rdx_off; }
0N/A static int rbxOffset(void) { return rbx_off; }
0N/A static int xmm0Offset(void) { return xmm0_off; }
0N/A // This really returns a slot in the fp save area, which one is not important
0N/A static int fpResultOffset(void) { return st0_off; }
0N/A
0N/A // During deoptimization only the result register need to be restored
0N/A // all the other values have already been extracted.
0N/A
0N/A static void restore_result_registers(MacroAssembler* masm);
0N/A
0N/A};
0N/A
0N/AOopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words,
4012N/A int* total_frame_words, bool verify_fpu, bool save_vectors) {
4012N/A int vect_words = 0;
4012N/A#ifdef COMPILER2
4012N/A if (save_vectors) {
4012N/A assert(UseAVX > 0, "256bit vectors are supported only with AVX");
4012N/A assert(MaxVectorSize == 32, "only 256bit vectors are supported now");
4012N/A // Save upper half of YMM registes
4012N/A vect_words = 8 * 16 / wordSize;
4012N/A additional_frame_words += vect_words;
4012N/A }
4012N/A#else
4012N/A assert(!save_vectors, "vectors are generated only by C2");
4012N/A#endif
4012N/A int frame_size_in_bytes = (reg_save_size + additional_frame_words) * wordSize;
0N/A int frame_words = frame_size_in_bytes / wordSize;
0N/A *total_frame_words = frame_words;
0N/A
0N/A assert(FPUStateSizeInWords == 27, "update stack layout");
0N/A
0N/A // save registers, fpu state, and flags
0N/A // We assume caller has already has return address slot on the stack
0N/A // We push epb twice in this sequence because we want the real rbp,
304N/A // to be under the return like a normal enter and we want to use pusha
0N/A // We push by hand instead of pusing push
0N/A __ enter();
304N/A __ pusha();
304N/A __ pushf();
4012N/A __ subptr(rsp,FPU_regs_live*wordSize); // Push FPU registers space
0N/A __ push_FPU_state(); // Save FPU state & init
0N/A
0N/A if (verify_fpu) {
0N/A // Some stubs may have non standard FPU control word settings so
0N/A // only check and reset the value when it required to be the
0N/A // standard value. The safepoint blob in particular can be used
0N/A // in methods which are using the 24 bit control word for
0N/A // optimized float math.
0N/A
0N/A#ifdef ASSERT
0N/A // Make sure the control word has the expected value
0N/A Label ok;
0N/A __ cmpw(Address(rsp, 0), StubRoutines::fpu_cntrl_wrd_std());
0N/A __ jccb(Assembler::equal, ok);
0N/A __ stop("corrupted control word detected");
0N/A __ bind(ok);
0N/A#endif
0N/A
0N/A // Reset the control word to guard against exceptions being unmasked
0N/A // since fstp_d can cause FPU stack underflow exceptions. Write it
0N/A // into the on stack copy and then reload that to make sure that the
0N/A // current and future values are correct.
0N/A __ movw(Address(rsp, 0), StubRoutines::fpu_cntrl_wrd_std());
0N/A }
0N/A
0N/A __ frstor(Address(rsp, 0));
0N/A if (!verify_fpu) {
0N/A // Set the control word so that exceptions are masked for the
0N/A // following code.
0N/A __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
0N/A }
0N/A
0N/A // Save the FPU registers in de-opt-able form
0N/A
0N/A __ fstp_d(Address(rsp, st0_off*wordSize)); // st(0)
0N/A __ fstp_d(Address(rsp, st1_off*wordSize)); // st(1)
0N/A __ fstp_d(Address(rsp, st2_off*wordSize)); // st(2)
0N/A __ fstp_d(Address(rsp, st3_off*wordSize)); // st(3)
0N/A __ fstp_d(Address(rsp, st4_off*wordSize)); // st(4)
0N/A __ fstp_d(Address(rsp, st5_off*wordSize)); // st(5)
0N/A __ fstp_d(Address(rsp, st6_off*wordSize)); // st(6)
0N/A __ fstp_d(Address(rsp, st7_off*wordSize)); // st(7)
0N/A
0N/A if( UseSSE == 1 ) { // Save the XMM state
0N/A __ movflt(Address(rsp,xmm0_off*wordSize),xmm0);
0N/A __ movflt(Address(rsp,xmm1_off*wordSize),xmm1);
0N/A __ movflt(Address(rsp,xmm2_off*wordSize),xmm2);
0N/A __ movflt(Address(rsp,xmm3_off*wordSize),xmm3);
0N/A __ movflt(Address(rsp,xmm4_off*wordSize),xmm4);
0N/A __ movflt(Address(rsp,xmm5_off*wordSize),xmm5);
0N/A __ movflt(Address(rsp,xmm6_off*wordSize),xmm6);
0N/A __ movflt(Address(rsp,xmm7_off*wordSize),xmm7);
0N/A } else if( UseSSE >= 2 ) {
4012N/A // Save whole 128bit (16 bytes) XMM regiters
4012N/A __ movdqu(Address(rsp,xmm0_off*wordSize),xmm0);
4012N/A __ movdqu(Address(rsp,xmm1_off*wordSize),xmm1);
4012N/A __ movdqu(Address(rsp,xmm2_off*wordSize),xmm2);
4012N/A __ movdqu(Address(rsp,xmm3_off*wordSize),xmm3);
4012N/A __ movdqu(Address(rsp,xmm4_off*wordSize),xmm4);
4012N/A __ movdqu(Address(rsp,xmm5_off*wordSize),xmm5);
4012N/A __ movdqu(Address(rsp,xmm6_off*wordSize),xmm6);
4012N/A __ movdqu(Address(rsp,xmm7_off*wordSize),xmm7);
4012N/A }
4012N/A
4012N/A if (vect_words > 0) {
4012N/A assert(vect_words*wordSize == 128, "");
4012N/A __ subptr(rsp, 128); // Save upper half of YMM registes
4012N/A __ vextractf128h(Address(rsp, 0),xmm0);
4012N/A __ vextractf128h(Address(rsp, 16),xmm1);
4012N/A __ vextractf128h(Address(rsp, 32),xmm2);
4012N/A __ vextractf128h(Address(rsp, 48),xmm3);
4012N/A __ vextractf128h(Address(rsp, 64),xmm4);
4012N/A __ vextractf128h(Address(rsp, 80),xmm5);
4012N/A __ vextractf128h(Address(rsp, 96),xmm6);
4012N/A __ vextractf128h(Address(rsp,112),xmm7);
0N/A }
0N/A
0N/A // Set an oopmap for the call site. This oopmap will map all
0N/A // oop-registers and debug-info registers as callee-saved. This
0N/A // will allow deoptimization at this safepoint to find all possible
0N/A // debug-info recordings, as well as let GC find all oops.
0N/A
0N/A OopMapSet *oop_maps = new OopMapSet();
0N/A OopMap* map = new OopMap( frame_words, 0 );
0N/A
0N/A#define STACK_OFFSET(x) VMRegImpl::stack2reg((x) + additional_frame_words)
0N/A
0N/A map->set_callee_saved(STACK_OFFSET( rax_off), rax->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET( rcx_off), rcx->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET( rdx_off), rdx->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET( rbx_off), rbx->as_VMReg());
0N/A // rbp, location is known implicitly, no oopMap
0N/A map->set_callee_saved(STACK_OFFSET( rsi_off), rsi->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET( rdi_off), rdi->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET(st0_off), as_FloatRegister(0)->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET(st1_off), as_FloatRegister(1)->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET(st2_off), as_FloatRegister(2)->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET(st3_off), as_FloatRegister(3)->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET(st4_off), as_FloatRegister(4)->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET(st5_off), as_FloatRegister(5)->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET(st6_off), as_FloatRegister(6)->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET(st7_off), as_FloatRegister(7)->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET(xmm0_off), xmm0->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET(xmm1_off), xmm1->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET(xmm2_off), xmm2->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET(xmm3_off), xmm3->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET(xmm4_off), xmm4->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET(xmm5_off), xmm5->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET(xmm6_off), xmm6->as_VMReg());
0N/A map->set_callee_saved(STACK_OFFSET(xmm7_off), xmm7->as_VMReg());
0N/A // %%% This is really a waste but we'll keep things as they were for now
0N/A if (true) {
0N/A#define NEXTREG(x) (x)->as_VMReg()->next()
0N/A map->set_callee_saved(STACK_OFFSET(st0H_off), NEXTREG(as_FloatRegister(0)));
0N/A map->set_callee_saved(STACK_OFFSET(st1H_off), NEXTREG(as_FloatRegister(1)));
0N/A map->set_callee_saved(STACK_OFFSET(st2H_off), NEXTREG(as_FloatRegister(2)));
0N/A map->set_callee_saved(STACK_OFFSET(st3H_off), NEXTREG(as_FloatRegister(3)));
0N/A map->set_callee_saved(STACK_OFFSET(st4H_off), NEXTREG(as_FloatRegister(4)));
0N/A map->set_callee_saved(STACK_OFFSET(st5H_off), NEXTREG(as_FloatRegister(5)));
0N/A map->set_callee_saved(STACK_OFFSET(st6H_off), NEXTREG(as_FloatRegister(6)));
0N/A map->set_callee_saved(STACK_OFFSET(st7H_off), NEXTREG(as_FloatRegister(7)));
0N/A map->set_callee_saved(STACK_OFFSET(xmm0H_off), NEXTREG(xmm0));
0N/A map->set_callee_saved(STACK_OFFSET(xmm1H_off), NEXTREG(xmm1));
0N/A map->set_callee_saved(STACK_OFFSET(xmm2H_off), NEXTREG(xmm2));
0N/A map->set_callee_saved(STACK_OFFSET(xmm3H_off), NEXTREG(xmm3));
0N/A map->set_callee_saved(STACK_OFFSET(xmm4H_off), NEXTREG(xmm4));
0N/A map->set_callee_saved(STACK_OFFSET(xmm5H_off), NEXTREG(xmm5));
0N/A map->set_callee_saved(STACK_OFFSET(xmm6H_off), NEXTREG(xmm6));
0N/A map->set_callee_saved(STACK_OFFSET(xmm7H_off), NEXTREG(xmm7));
0N/A#undef NEXTREG
0N/A#undef STACK_OFFSET
0N/A }
0N/A
0N/A return map;
0N/A
0N/A}
0N/A
4012N/Avoid RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_vectors) {
0N/A // Recover XMM & FPU state
4012N/A int additional_frame_bytes = 0;
4012N/A#ifdef COMPILER2
4012N/A if (restore_vectors) {
4012N/A assert(UseAVX > 0, "256bit vectors are supported only with AVX");
4012N/A assert(MaxVectorSize == 32, "only 256bit vectors are supported now");
4012N/A additional_frame_bytes = 128;
4012N/A }
4012N/A#else
4012N/A assert(!restore_vectors, "vectors are generated only by C2");
4012N/A#endif
4012N/A if (UseSSE == 1) {
4012N/A assert(additional_frame_bytes == 0, "");
0N/A __ movflt(xmm0,Address(rsp,xmm0_off*wordSize));
0N/A __ movflt(xmm1,Address(rsp,xmm1_off*wordSize));
0N/A __ movflt(xmm2,Address(rsp,xmm2_off*wordSize));
0N/A __ movflt(xmm3,Address(rsp,xmm3_off*wordSize));
0N/A __ movflt(xmm4,Address(rsp,xmm4_off*wordSize));
0N/A __ movflt(xmm5,Address(rsp,xmm5_off*wordSize));
0N/A __ movflt(xmm6,Address(rsp,xmm6_off*wordSize));
0N/A __ movflt(xmm7,Address(rsp,xmm7_off*wordSize));
4012N/A } else if (UseSSE >= 2) {
4012N/A#define STACK_ADDRESS(x) Address(rsp,(x)*wordSize + additional_frame_bytes)
4012N/A __ movdqu(xmm0,STACK_ADDRESS(xmm0_off));
4012N/A __ movdqu(xmm1,STACK_ADDRESS(xmm1_off));
4012N/A __ movdqu(xmm2,STACK_ADDRESS(xmm2_off));
4012N/A __ movdqu(xmm3,STACK_ADDRESS(xmm3_off));
4012N/A __ movdqu(xmm4,STACK_ADDRESS(xmm4_off));
4012N/A __ movdqu(xmm5,STACK_ADDRESS(xmm5_off));
4012N/A __ movdqu(xmm6,STACK_ADDRESS(xmm6_off));
4012N/A __ movdqu(xmm7,STACK_ADDRESS(xmm7_off));
4012N/A#undef STACK_ADDRESS
4012N/A }
4012N/A if (restore_vectors) {
4012N/A // Restore upper half of YMM registes.
4012N/A assert(additional_frame_bytes == 128, "");
4012N/A __ vinsertf128h(xmm0, Address(rsp, 0));
4012N/A __ vinsertf128h(xmm1, Address(rsp, 16));
4012N/A __ vinsertf128h(xmm2, Address(rsp, 32));
4012N/A __ vinsertf128h(xmm3, Address(rsp, 48));
4012N/A __ vinsertf128h(xmm4, Address(rsp, 64));
4012N/A __ vinsertf128h(xmm5, Address(rsp, 80));
4012N/A __ vinsertf128h(xmm6, Address(rsp, 96));
4012N/A __ vinsertf128h(xmm7, Address(rsp,112));
4012N/A __ addptr(rsp, additional_frame_bytes);
0N/A }
0N/A __ pop_FPU_state();
4012N/A __ addptr(rsp, FPU_regs_live*wordSize); // Pop FPU registers
304N/A
304N/A __ popf();
304N/A __ popa();
0N/A // Get the rbp, described implicitly by the frame sender code (no oopMap)
304N/A __ pop(rbp);
0N/A
0N/A}
0N/A
0N/Avoid RegisterSaver::restore_result_registers(MacroAssembler* masm) {
0N/A
0N/A // Just restore result register. Only used by deoptimization. By
0N/A // now any callee save register that needs to be restore to a c2
0N/A // caller of the deoptee has been extracted into the vframeArray
0N/A // and will be stuffed into the c2i adapter we create for later
0N/A // restoration so only result registers need to be restored here.
0N/A //
0N/A
0N/A __ frstor(Address(rsp, 0)); // Restore fpu state
0N/A
0N/A // Recover XMM & FPU state
0N/A if( UseSSE == 1 ) {
0N/A __ movflt(xmm0, Address(rsp, xmm0_off*wordSize));
0N/A } else if( UseSSE >= 2 ) {
0N/A __ movdbl(xmm0, Address(rsp, xmm0_off*wordSize));
0N/A }
304N/A __ movptr(rax, Address(rsp, rax_off*wordSize));
304N/A __ movptr(rdx, Address(rsp, rdx_off*wordSize));
0N/A // Pop all of the register save are off the stack except the return address
304N/A __ addptr(rsp, return_off * wordSize);
0N/A}
0N/A
4012N/A// Is vector's size (in bytes) bigger than a size saved by default?
4012N/A// 16 bytes XMM registers are saved by default using SSE2 movdqu instructions.
4012N/A// Note, MaxVectorSize == 0 with UseSSE < 2 and vectors are not generated.
4012N/Abool SharedRuntime::is_wide_vector(int size) {
4012N/A return size > 16;
4012N/A}
4012N/A
0N/A// The java_calling_convention describes stack locations as ideal slots on
0N/A// a frame with no abi restrictions. Since we must observe abi restrictions
0N/A// (like the placement of the register window) the slots must be biased by
0N/A// the following value.
0N/Astatic int reg2offset_in(VMReg r) {
0N/A // Account for saved rbp, and return address
0N/A // This should really be in_preserve_stack_slots
0N/A return (r->reg2stack() + 2) * VMRegImpl::stack_slot_size;
0N/A}
0N/A
0N/Astatic int reg2offset_out(VMReg r) {
0N/A return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
0N/A}
0N/A
0N/A// ---------------------------------------------------------------------------
0N/A// Read the array of BasicTypes from a signature, and compute where the
0N/A// arguments should go. Values in the VMRegPair regs array refer to 4-byte
0N/A// quantities. Values less than SharedInfo::stack0 are registers, those above
0N/A// refer to 4-byte stack slots. All stack slots are based off of the stack pointer
0N/A// as framesizes are fixed.
0N/A// VMRegImpl::stack0 refers to the first slot 0(sp).
0N/A// and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
0N/A// up to RegisterImpl::number_of_registers) are the 32-bit
0N/A// integer registers.
0N/A
0N/A// Pass first two oop/int args in registers ECX and EDX.
0N/A// Pass first two float/double args in registers XMM0 and XMM1.
0N/A// Doubles have precedence, so if you pass a mix of floats and doubles
0N/A// the doubles will grab the registers before the floats will.
0N/A
0N/A// Note: the INPUTS in sig_bt are in units of Java argument words, which are
0N/A// either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
0N/A// units regardless of build. Of course for i486 there is no 64 bit build
0N/A
0N/A
0N/A// ---------------------------------------------------------------------------
0N/A// The compiled Java calling convention.
0N/A// Pass first two oop/int args in registers ECX and EDX.
0N/A// Pass first two float/double args in registers XMM0 and XMM1.
0N/A// Doubles have precedence, so if you pass a mix of floats and doubles
0N/A// the doubles will grab the registers before the floats will.
0N/Aint SharedRuntime::java_calling_convention(const BasicType *sig_bt,
0N/A VMRegPair *regs,
0N/A int total_args_passed,
0N/A int is_outgoing) {
0N/A uint stack = 0; // Starting stack position for args on stack
0N/A
0N/A
0N/A // Pass first two oop/int args in registers ECX and EDX.
0N/A uint reg_arg0 = 9999;
0N/A uint reg_arg1 = 9999;
0N/A
0N/A // Pass first two float/double args in registers XMM0 and XMM1.
0N/A // Doubles have precedence, so if you pass a mix of floats and doubles
0N/A // the doubles will grab the registers before the floats will.
0N/A // CNC - TURNED OFF FOR non-SSE.
0N/A // On Intel we have to round all doubles (and most floats) at
0N/A // call sites by storing to the stack in any case.
0N/A // UseSSE=0 ==> Don't Use ==> 9999+0
0N/A // UseSSE=1 ==> Floats only ==> 9999+1
0N/A // UseSSE>=2 ==> Floats or doubles ==> 9999+2
0N/A enum { fltarg_dontuse = 9999+0, fltarg_float_only = 9999+1, fltarg_flt_dbl = 9999+2 };
0N/A uint fargs = (UseSSE>=2) ? 2 : UseSSE;
0N/A uint freg_arg0 = 9999+fargs;
0N/A uint freg_arg1 = 9999+fargs;
0N/A
0N/A // Pass doubles & longs aligned on the stack. First count stack slots for doubles
0N/A int i;
0N/A for( i = 0; i < total_args_passed; i++) {
0N/A if( sig_bt[i] == T_DOUBLE ) {
0N/A // first 2 doubles go in registers
0N/A if( freg_arg0 == fltarg_flt_dbl ) freg_arg0 = i;
0N/A else if( freg_arg1 == fltarg_flt_dbl ) freg_arg1 = i;
0N/A else // Else double is passed low on the stack to be aligned.
0N/A stack += 2;
0N/A } else if( sig_bt[i] == T_LONG ) {
0N/A stack += 2;
0N/A }
0N/A }
0N/A int dstack = 0; // Separate counter for placing doubles
0N/A
0N/A // Now pick where all else goes.
0N/A for( i = 0; i < total_args_passed; i++) {
0N/A // From the type and the argument number (count) compute the location
0N/A switch( sig_bt[i] ) {
0N/A case T_SHORT:
0N/A case T_CHAR:
0N/A case T_BYTE:
0N/A case T_BOOLEAN:
0N/A case T_INT:
0N/A case T_ARRAY:
0N/A case T_OBJECT:
0N/A case T_ADDRESS:
0N/A if( reg_arg0 == 9999 ) {
0N/A reg_arg0 = i;
0N/A regs[i].set1(rcx->as_VMReg());
0N/A } else if( reg_arg1 == 9999 ) {
0N/A reg_arg1 = i;
0N/A regs[i].set1(rdx->as_VMReg());
0N/A } else {
0N/A regs[i].set1(VMRegImpl::stack2reg(stack++));
0N/A }
0N/A break;
0N/A case T_FLOAT:
0N/A if( freg_arg0 == fltarg_flt_dbl || freg_arg0 == fltarg_float_only ) {
0N/A freg_arg0 = i;
0N/A regs[i].set1(xmm0->as_VMReg());
0N/A } else if( freg_arg1 == fltarg_flt_dbl || freg_arg1 == fltarg_float_only ) {
0N/A freg_arg1 = i;
0N/A regs[i].set1(xmm1->as_VMReg());
0N/A } else {
0N/A regs[i].set1(VMRegImpl::stack2reg(stack++));
0N/A }
0N/A break;
0N/A case T_LONG:
0N/A assert(sig_bt[i+1] == T_VOID, "missing Half" );
0N/A regs[i].set2(VMRegImpl::stack2reg(dstack));
0N/A dstack += 2;
0N/A break;
0N/A case T_DOUBLE:
0N/A assert(sig_bt[i+1] == T_VOID, "missing Half" );
0N/A if( freg_arg0 == (uint)i ) {
0N/A regs[i].set2(xmm0->as_VMReg());
0N/A } else if( freg_arg1 == (uint)i ) {
0N/A regs[i].set2(xmm1->as_VMReg());
0N/A } else {
0N/A regs[i].set2(VMRegImpl::stack2reg(dstack));
0N/A dstack += 2;
0N/A }
0N/A break;
0N/A case T_VOID: regs[i].set_bad(); break;
0N/A break;
0N/A default:
0N/A ShouldNotReachHere();
0N/A break;
0N/A }
0N/A }
0N/A
0N/A // return value can be odd number of VMRegImpl stack slots make multiple of 2
0N/A return round_to(stack, 2);
0N/A}
0N/A
0N/A// Patch the callers callsite with entry to compiled code if it exists.
0N/Astatic void patch_callers_callsite(MacroAssembler *masm) {
0N/A Label L;
0N/A __ verify_oop(rbx);
304N/A __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
0N/A __ jcc(Assembler::equal, L);
0N/A // Schedule the branch target address early.
0N/A // Call into the VM to patch the caller, then jump to compiled callee
0N/A // rax, isn't live so capture return address while we easily can
304N/A __ movptr(rax, Address(rsp, 0));
304N/A __ pusha();
304N/A __ pushf();
0N/A
0N/A if (UseSSE == 1) {
304N/A __ subptr(rsp, 2*wordSize);
0N/A __ movflt(Address(rsp, 0), xmm0);
0N/A __ movflt(Address(rsp, wordSize), xmm1);
0N/A }
0N/A if (UseSSE >= 2) {
304N/A __ subptr(rsp, 4*wordSize);
0N/A __ movdbl(Address(rsp, 0), xmm0);
0N/A __ movdbl(Address(rsp, 2*wordSize), xmm1);
0N/A }
0N/A#ifdef COMPILER2
0N/A // C2 may leave the stack dirty if not in SSE2+ mode
0N/A if (UseSSE >= 2) {
0N/A __ verify_FPU(0, "c2i transition should have clean FPU stack");
0N/A } else {
0N/A __ empty_FPU_stack();
0N/A }
0N/A#endif /* COMPILER2 */
0N/A
0N/A // VM needs caller's callsite
304N/A __ push(rax);
0N/A // VM needs target method
304N/A __ push(rbx);
0N/A __ verify_oop(rbx);
0N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
304N/A __ addptr(rsp, 2*wordSize);
0N/A
0N/A if (UseSSE == 1) {
0N/A __ movflt(xmm0, Address(rsp, 0));
0N/A __ movflt(xmm1, Address(rsp, wordSize));
304N/A __ addptr(rsp, 2*wordSize);
0N/A }
0N/A if (UseSSE >= 2) {
0N/A __ movdbl(xmm0, Address(rsp, 0));
0N/A __ movdbl(xmm1, Address(rsp, 2*wordSize));
304N/A __ addptr(rsp, 4*wordSize);
0N/A }
0N/A
304N/A __ popf();
304N/A __ popa();
0N/A __ bind(L);
0N/A}
0N/A
0N/A
0N/Astatic void move_c2i_double(MacroAssembler *masm, XMMRegister r, int st_off) {
1426N/A int next_off = st_off - Interpreter::stackElementSize;
1426N/A __ movdbl(Address(rsp, next_off), r);
0N/A}
0N/A
0N/Astatic void gen_c2i_adapter(MacroAssembler *masm,
0N/A int total_args_passed,
0N/A int comp_args_on_stack,
0N/A const BasicType *sig_bt,
0N/A const VMRegPair *regs,
0N/A Label& skip_fixup) {
0N/A // Before we get into the guts of the C2I adapter, see if we should be here
0N/A // at all. We've come from compiled code and are attempting to jump to the
0N/A // interpreter, which means the caller made a static call to get here
0N/A // (vcalls always get a compiled target if there is one). Check for a
0N/A // compiled target. If there is one, we need to patch the caller's call.
0N/A patch_callers_callsite(masm);
0N/A
0N/A __ bind(skip_fixup);
0N/A
0N/A#ifdef COMPILER2
0N/A // C2 may leave the stack dirty if not in SSE2+ mode
0N/A if (UseSSE >= 2) {
0N/A __ verify_FPU(0, "c2i transition should have clean FPU stack");
0N/A } else {
0N/A __ empty_FPU_stack();
0N/A }
0N/A#endif /* COMPILER2 */
0N/A
0N/A // Since all args are passed on the stack, total_args_passed * interpreter_
0N/A // stack_element_size is the
0N/A // space we need.
1426N/A int extraspace = total_args_passed * Interpreter::stackElementSize;
0N/A
0N/A // Get return address
304N/A __ pop(rax);
0N/A
0N/A // set senderSP value
304N/A __ movptr(rsi, rsp);
304N/A
304N/A __ subptr(rsp, extraspace);
0N/A
0N/A // Now write the args into the outgoing interpreter space
0N/A for (int i = 0; i < total_args_passed; i++) {
0N/A if (sig_bt[i] == T_VOID) {
0N/A assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
0N/A continue;
0N/A }
0N/A
0N/A // st_off points to lowest address on stack.
1426N/A int st_off = ((total_args_passed - 1) - i) * Interpreter::stackElementSize;
1426N/A int next_off = st_off - Interpreter::stackElementSize;
304N/A
0N/A // Say 4 args:
0N/A // i st_off
0N/A // 0 12 T_LONG
0N/A // 1 8 T_VOID
0N/A // 2 4 T_OBJECT
0N/A // 3 0 T_BOOL
0N/A VMReg r_1 = regs[i].first();
0N/A VMReg r_2 = regs[i].second();
0N/A if (!r_1->is_valid()) {
0N/A assert(!r_2->is_valid(), "");
0N/A continue;
0N/A }
0N/A
0N/A if (r_1->is_stack()) {
0N/A // memory to memory use fpu stack top
0N/A int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
0N/A
0N/A if (!r_2->is_valid()) {
0N/A __ movl(rdi, Address(rsp, ld_off));
304N/A __ movptr(Address(rsp, st_off), rdi);
0N/A } else {
0N/A
0N/A // ld_off == LSW, ld_off+VMRegImpl::stack_slot_size == MSW
0N/A // st_off == MSW, st_off-wordSize == LSW
0N/A
304N/A __ movptr(rdi, Address(rsp, ld_off));
304N/A __ movptr(Address(rsp, next_off), rdi);
304N/A#ifndef _LP64
304N/A __ movptr(rdi, Address(rsp, ld_off + wordSize));
304N/A __ movptr(Address(rsp, st_off), rdi);
304N/A#else
304N/A#ifdef ASSERT
304N/A // Overwrite the unused slot with known junk
304N/A __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
304N/A __ movptr(Address(rsp, st_off), rax);
304N/A#endif /* ASSERT */
304N/A#endif // _LP64
0N/A }
0N/A } else if (r_1->is_Register()) {
0N/A Register r = r_1->as_Register();
0N/A if (!r_2->is_valid()) {
0N/A __ movl(Address(rsp, st_off), r);
0N/A } else {
0N/A // long/double in gpr
304N/A NOT_LP64(ShouldNotReachHere());
304N/A // Two VMRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
304N/A // T_DOUBLE and T_LONG use two slots in the interpreter
304N/A if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
304N/A // long/double in gpr
304N/A#ifdef ASSERT
304N/A // Overwrite the unused slot with known junk
304N/A LP64_ONLY(__ mov64(rax, CONST64(0xdeadffffdeadaaab)));
304N/A __ movptr(Address(rsp, st_off), rax);
304N/A#endif /* ASSERT */
304N/A __ movptr(Address(rsp, next_off), r);
304N/A } else {
304N/A __ movptr(Address(rsp, st_off), r);
304N/A }
0N/A }
0N/A } else {
0N/A assert(r_1->is_XMMRegister(), "");
0N/A if (!r_2->is_valid()) {
0N/A __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
0N/A } else {
0N/A assert(sig_bt[i] == T_DOUBLE || sig_bt[i] == T_LONG, "wrong type");
0N/A move_c2i_double(masm, r_1->as_XMMRegister(), st_off);
0N/A }
0N/A }
0N/A }
0N/A
0N/A // Schedule the branch target address early.
304N/A __ movptr(rcx, Address(rbx, in_bytes(methodOopDesc::interpreter_entry_offset())));
0N/A // And repush original return address
304N/A __ push(rax);
0N/A __ jmp(rcx);
0N/A}
0N/A
0N/A
0N/Astatic void move_i2c_double(MacroAssembler *masm, XMMRegister r, Register saved_sp, int ld_off) {
1426N/A int next_val_off = ld_off - Interpreter::stackElementSize;
1426N/A __ movdbl(r, Address(saved_sp, next_val_off));
0N/A}
0N/A
3932N/Astatic void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg,
3932N/A address code_start, address code_end,
3932N/A Label& L_ok) {
3932N/A Label L_fail;
3932N/A __ lea(temp_reg, ExternalAddress(code_start));
3932N/A __ cmpptr(pc_reg, temp_reg);
3932N/A __ jcc(Assembler::belowEqual, L_fail);
3932N/A __ lea(temp_reg, ExternalAddress(code_end));
3932N/A __ cmpptr(pc_reg, temp_reg);
3932N/A __ jcc(Assembler::below, L_ok);
3932N/A __ bind(L_fail);
3932N/A}
3932N/A
0N/Astatic void gen_i2c_adapter(MacroAssembler *masm,
0N/A int total_args_passed,
0N/A int comp_args_on_stack,
0N/A const BasicType *sig_bt,
0N/A const VMRegPair *regs) {
0N/A
0N/A // Note: rsi contains the senderSP on entry. We must preserve it since
0N/A // we may do a i2c -> c2i transition if we lose a race where compiled
0N/A // code goes non-entrant while we get args ready.
0N/A
3932N/A // Adapters can be frameless because they do not require the caller
3932N/A // to perform additional cleanup work, such as correcting the stack pointer.
3932N/A // An i2c adapter is frameless because the *caller* frame, which is interpreted,
3932N/A // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
3932N/A // even if a callee has modified the stack pointer.
3932N/A // A c2i adapter is frameless because the *callee* frame, which is interpreted,
3932N/A // routinely repairs its caller's stack pointer (from sender_sp, which is set
3932N/A // up via the senderSP register).
3932N/A // In other words, if *either* the caller or callee is interpreted, we can
3932N/A // get the stack pointer repaired after a call.
3932N/A // This is why c2i and i2c adapters cannot be indefinitely composed.
3932N/A // In particular, if a c2i adapter were to somehow call an i2c adapter,
3932N/A // both caller and callee would be compiled methods, and neither would
3932N/A // clean up the stack pointer changes performed by the two adapters.
3932N/A // If this happens, control eventually transfers back to the compiled
3932N/A // caller, but with an uncorrected stack, causing delayed havoc.
3932N/A
0N/A // Pick up the return address
304N/A __ movptr(rax, Address(rsp, 0));
0N/A
3932N/A if (VerifyAdapterCalls &&
3932N/A (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) {
3932N/A // So, let's test for cascading c2i/i2c adapters right now.
3932N/A // assert(Interpreter::contains($return_addr) ||
3932N/A // StubRoutines::contains($return_addr),
3932N/A // "i2c adapter must return to an interpreter frame");
3932N/A __ block_comment("verify_i2c { ");
3932N/A Label L_ok;
3932N/A if (Interpreter::code() != NULL)
3932N/A range_check(masm, rax, rdi,
3932N/A Interpreter::code()->code_start(), Interpreter::code()->code_end(),
3932N/A L_ok);
3932N/A if (StubRoutines::code1() != NULL)
3932N/A range_check(masm, rax, rdi,
3932N/A StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(),
3932N/A L_ok);
3932N/A if (StubRoutines::code2() != NULL)
3932N/A range_check(masm, rax, rdi,
3932N/A StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(),
3932N/A L_ok);
3932N/A const char* msg = "i2c adapter must return to an interpreter frame";
3932N/A __ block_comment(msg);
3932N/A __ stop(msg);
3932N/A __ bind(L_ok);
3932N/A __ block_comment("} verify_i2ce ");
3932N/A }
3932N/A
0N/A // Must preserve original SP for loading incoming arguments because
0N/A // we need to align the outgoing SP for compiled code.
304N/A __ movptr(rdi, rsp);
0N/A
0N/A // Cut-out for having no stack args. Since up to 2 int/oop args are passed
0N/A // in registers, we will occasionally have no stack args.
0N/A int comp_words_on_stack = 0;
0N/A if (comp_args_on_stack) {
0N/A // Sig words on the stack are greater-than VMRegImpl::stack0. Those in
0N/A // registers are below. By subtracting stack0, we either get a negative
0N/A // number (all values in registers) or the maximum stack slot accessed.
0N/A // int comp_args_on_stack = VMRegImpl::reg2stack(max_arg);
0N/A // Convert 4-byte stack slots to words.
0N/A comp_words_on_stack = round_to(comp_args_on_stack*4, wordSize)>>LogBytesPerWord;
0N/A // Round up to miminum stack alignment, in wordSize
0N/A comp_words_on_stack = round_to(comp_words_on_stack, 2);
304N/A __ subptr(rsp, comp_words_on_stack * wordSize);
0N/A }
0N/A
0N/A // Align the outgoing SP
304N/A __ andptr(rsp, -(StackAlignmentInBytes));
0N/A
0N/A // push the return address on the stack (note that pushing, rather
0N/A // than storing it, yields the correct frame alignment for the callee)
304N/A __ push(rax);
0N/A
0N/A // Put saved SP in another register
0N/A const Register saved_sp = rax;
304N/A __ movptr(saved_sp, rdi);
0N/A
0N/A
0N/A // Will jump to the compiled code just as if compiled code was doing it.
0N/A // Pre-load the register-jump target early, to schedule it better.
304N/A __ movptr(rdi, Address(rbx, in_bytes(methodOopDesc::from_compiled_offset())));
0N/A
0N/A // Now generate the shuffle code. Pick up all register args and move the
0N/A // rest through the floating point stack top.
0N/A for (int i = 0; i < total_args_passed; i++) {
0N/A if (sig_bt[i] == T_VOID) {
0N/A // Longs and doubles are passed in native word order, but misaligned
0N/A // in the 32-bit build.
0N/A assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
0N/A continue;
0N/A }
0N/A
0N/A // Pick up 0, 1 or 2 words from SP+offset.
0N/A
0N/A assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
0N/A "scrambled load targets?");
0N/A // Load in argument order going down.
1426N/A int ld_off = (total_args_passed - i) * Interpreter::stackElementSize;
0N/A // Point to interpreter value (vs. tag)
1426N/A int next_off = ld_off - Interpreter::stackElementSize;
0N/A //
0N/A //
0N/A //
0N/A VMReg r_1 = regs[i].first();
0N/A VMReg r_2 = regs[i].second();
0N/A if (!r_1->is_valid()) {
0N/A assert(!r_2->is_valid(), "");
0N/A continue;
0N/A }
0N/A if (r_1->is_stack()) {
0N/A // Convert stack slot to an SP offset (+ wordSize to account for return address )
0N/A int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
0N/A
0N/A // We can use rsi as a temp here because compiled code doesn't need rsi as an input
0N/A // and if we end up going thru a c2i because of a miss a reasonable value of rsi
0N/A // we be generated.
0N/A if (!r_2->is_valid()) {
0N/A // __ fld_s(Address(saved_sp, ld_off));
0N/A // __ fstp_s(Address(rsp, st_off));
0N/A __ movl(rsi, Address(saved_sp, ld_off));
304N/A __ movptr(Address(rsp, st_off), rsi);
0N/A } else {
0N/A // Interpreter local[n] == MSW, local[n+1] == LSW however locals
0N/A // are accessed as negative so LSW is at LOW address
0N/A
0N/A // ld_off is MSW so get LSW
0N/A // st_off is LSW (i.e. reg.first())
0N/A // __ fld_d(Address(saved_sp, next_off));
0N/A // __ fstp_d(Address(rsp, st_off));
304N/A //
304N/A // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
304N/A // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
304N/A // So we must adjust where to pick up the data to match the interpreter.
304N/A //
304N/A // Interpreter local[n] == MSW, local[n+1] == LSW however locals
304N/A // are accessed as negative so LSW is at LOW address
304N/A
304N/A // ld_off is MSW so get LSW
304N/A const int offset = (NOT_LP64(true ||) sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
304N/A next_off : ld_off;
304N/A __ movptr(rsi, Address(saved_sp, offset));
304N/A __ movptr(Address(rsp, st_off), rsi);
304N/A#ifndef _LP64
304N/A __ movptr(rsi, Address(saved_sp, ld_off));
304N/A __ movptr(Address(rsp, st_off + wordSize), rsi);
304N/A#endif // _LP64
0N/A }
0N/A } else if (r_1->is_Register()) { // Register argument
0N/A Register r = r_1->as_Register();
0N/A assert(r != rax, "must be different");
0N/A if (r_2->is_valid()) {
304N/A //
304N/A // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
304N/A // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
304N/A // So we must adjust where to pick up the data to match the interpreter.
304N/A
304N/A const int offset = (NOT_LP64(true ||) sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
304N/A next_off : ld_off;
304N/A
304N/A // this can be a misaligned move
304N/A __ movptr(r, Address(saved_sp, offset));
304N/A#ifndef _LP64
0N/A assert(r_2->as_Register() != rax, "need another temporary register");
0N/A // Remember r_1 is low address (and LSB on x86)
0N/A // So r_2 gets loaded from high address regardless of the platform
304N/A __ movptr(r_2->as_Register(), Address(saved_sp, ld_off));
304N/A#endif // _LP64
0N/A } else {
0N/A __ movl(r, Address(saved_sp, ld_off));
0N/A }
0N/A } else {
0N/A assert(r_1->is_XMMRegister(), "");
0N/A if (!r_2->is_valid()) {
0N/A __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
0N/A } else {
0N/A move_i2c_double(masm, r_1->as_XMMRegister(), saved_sp, ld_off);
0N/A }
0N/A }
0N/A }
0N/A
0N/A // 6243940 We might end up in handle_wrong_method if
0N/A // the callee is deoptimized as we race thru here. If that
0N/A // happens we don't want to take a safepoint because the
0N/A // caller frame will look interpreted and arguments are now
0N/A // "compiled" so it is much better to make this transition
0N/A // invisible to the stack walking code. Unfortunately if
0N/A // we try and find the callee by normal means a safepoint
0N/A // is possible. So we stash the desired callee in the thread
0N/A // and the vm will find there should this case occur.
0N/A
0N/A __ get_thread(rax);
304N/A __ movptr(Address(rax, JavaThread::callee_target_offset()), rbx);
0N/A
0N/A // move methodOop to rax, in case we end up in an c2i adapter.
0N/A // the c2i adapters expect methodOop in rax, (c2) because c2's
0N/A // resolve stubs return the result (the method) in rax,.
0N/A // I'd love to fix this.
304N/A __ mov(rax, rbx);
0N/A
0N/A __ jmp(rdi);
0N/A}
0N/A
0N/A// ---------------------------------------------------------------
0N/AAdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
0N/A int total_args_passed,
0N/A int comp_args_on_stack,
0N/A const BasicType *sig_bt,
1187N/A const VMRegPair *regs,
1187N/A AdapterFingerPrint* fingerprint) {
0N/A address i2c_entry = __ pc();
0N/A
0N/A gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
0N/A
0N/A // -------------------------------------------------------------------------
0N/A // Generate a C2I adapter. On entry we know rbx, holds the methodOop during calls
0N/A // to the interpreter. The args start out packed in the compiled layout. They
0N/A // need to be unpacked into the interpreter layout. This will almost always
0N/A // require some stack space. We grow the current (compiled) stack, then repack
0N/A // the args. We finally end in a jump to the generic interpreter entry point.
0N/A // On exit from the interpreter, the interpreter will restore our SP (lest the
0N/A // compiled code, which relys solely on SP and not EBP, get sick).
0N/A
0N/A address c2i_unverified_entry = __ pc();
0N/A Label skip_fixup;
0N/A
0N/A Register holder = rax;
0N/A Register receiver = rcx;
0N/A Register temp = rbx;
0N/A
0N/A {
0N/A
0N/A Label missed;
0N/A
0N/A __ verify_oop(holder);
304N/A __ movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
0N/A __ verify_oop(temp);
0N/A
304N/A __ cmpptr(temp, Address(holder, compiledICHolderOopDesc::holder_klass_offset()));
304N/A __ movptr(rbx, Address(holder, compiledICHolderOopDesc::holder_method_offset()));
0N/A __ jcc(Assembler::notEqual, missed);
0N/A // Method might have been compiled since the call site was patched to
0N/A // interpreted if that is the case treat it as a miss so we can get
0N/A // the call site corrected.
304N/A __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
0N/A __ jcc(Assembler::equal, skip_fixup);
0N/A
0N/A __ bind(missed);
0N/A __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
0N/A }
0N/A
0N/A address c2i_entry = __ pc();
0N/A
0N/A gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
0N/A
0N/A __ flush();
1187N/A return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
0N/A}
0N/A
0N/Aint SharedRuntime::c_calling_convention(const BasicType *sig_bt,
0N/A VMRegPair *regs,
0N/A int total_args_passed) {
0N/A// We return the amount of VMRegImpl stack slots we need to reserve for all
0N/A// the arguments NOT counting out_preserve_stack_slots.
0N/A
0N/A uint stack = 0; // All arguments on stack
0N/A
0N/A for( int i = 0; i < total_args_passed; i++) {
0N/A // From the type and the argument number (count) compute the location
0N/A switch( sig_bt[i] ) {
0N/A case T_BOOLEAN:
0N/A case T_CHAR:
0N/A case T_FLOAT:
0N/A case T_BYTE:
0N/A case T_SHORT:
0N/A case T_INT:
0N/A case T_OBJECT:
0N/A case T_ARRAY:
0N/A case T_ADDRESS:
0N/A regs[i].set1(VMRegImpl::stack2reg(stack++));
0N/A break;
0N/A case T_LONG:
0N/A case T_DOUBLE: // The stack numbering is reversed from Java
0N/A // Since C arguments do not get reversed, the ordering for
0N/A // doubles on the stack must be opposite the Java convention
0N/A assert(sig_bt[i+1] == T_VOID, "missing Half" );
0N/A regs[i].set2(VMRegImpl::stack2reg(stack));
0N/A stack += 2;
0N/A break;
0N/A case T_VOID: regs[i].set_bad(); break;
0N/A default:
0N/A ShouldNotReachHere();
0N/A break;
0N/A }
0N/A }
0N/A return stack;
0N/A}
0N/A
0N/A// A simple move of integer like type
0N/Astatic void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
0N/A if (src.first()->is_stack()) {
0N/A if (dst.first()->is_stack()) {
0N/A // stack to stack
0N/A // __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
0N/A // __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
304N/A __ movl2ptr(rax, Address(rbp, reg2offset_in(src.first())));
304N/A __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
0N/A } else {
0N/A // stack to reg
304N/A __ movl2ptr(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
0N/A }
0N/A } else if (dst.first()->is_stack()) {
0N/A // reg to stack
304N/A // no need to sign extend on 64bit
304N/A __ movptr(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
0N/A } else {
304N/A if (dst.first() != src.first()) {
304N/A __ mov(dst.first()->as_Register(), src.first()->as_Register());
304N/A }
0N/A }
0N/A}
0N/A
0N/A// An oop arg. Must pass a handle not the oop itself
0N/Astatic void object_move(MacroAssembler* masm,
0N/A OopMap* map,
0N/A int oop_handle_offset,
0N/A int framesize_in_slots,
0N/A VMRegPair src,
0N/A VMRegPair dst,
0N/A bool is_receiver,
0N/A int* receiver_offset) {
0N/A
0N/A // Because of the calling conventions we know that src can be a
0N/A // register or a stack location. dst can only be a stack location.
0N/A
0N/A assert(dst.first()->is_stack(), "must be stack");
0N/A // must pass a handle. First figure out the location we use as a handle
0N/A
0N/A if (src.first()->is_stack()) {
0N/A // Oop is already on the stack as an argument
0N/A Register rHandle = rax;
0N/A Label nil;
304N/A __ xorptr(rHandle, rHandle);
304N/A __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
0N/A __ jcc(Assembler::equal, nil);
304N/A __ lea(rHandle, Address(rbp, reg2offset_in(src.first())));
0N/A __ bind(nil);
304N/A __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
0N/A
0N/A int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
0N/A map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
0N/A if (is_receiver) {
0N/A *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
0N/A }
0N/A } else {
0N/A // Oop is in an a register we must store it to the space we reserve
0N/A // on the stack for oop_handles
0N/A const Register rOop = src.first()->as_Register();
0N/A const Register rHandle = rax;
0N/A int oop_slot = (rOop == rcx ? 0 : 1) * VMRegImpl::slots_per_word + oop_handle_offset;
0N/A int offset = oop_slot*VMRegImpl::stack_slot_size;
0N/A Label skip;
304N/A __ movptr(Address(rsp, offset), rOop);
0N/A map->set_oop(VMRegImpl::stack2reg(oop_slot));
304N/A __ xorptr(rHandle, rHandle);
304N/A __ cmpptr(rOop, (int32_t)NULL_WORD);
0N/A __ jcc(Assembler::equal, skip);
304N/A __ lea(rHandle, Address(rsp, offset));
0N/A __ bind(skip);
0N/A // Store the handle parameter
304N/A __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
0N/A if (is_receiver) {
0N/A *receiver_offset = offset;
0N/A }
0N/A }
0N/A}
0N/A
0N/A// A float arg may have to do float reg int reg conversion
0N/Astatic void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
0N/A assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
0N/A
0N/A // Because of the calling convention we know that src is either a stack location
0N/A // or an xmm register. dst can only be a stack location.
0N/A
0N/A assert(dst.first()->is_stack() && ( src.first()->is_stack() || src.first()->is_XMMRegister()), "bad parameters");
0N/A
0N/A if (src.first()->is_stack()) {
0N/A __ movl(rax, Address(rbp, reg2offset_in(src.first())));
304N/A __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
0N/A } else {
0N/A // reg to stack
0N/A __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
0N/A }
0N/A}
0N/A
0N/A// A long move
0N/Astatic void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
0N/A
0N/A // The only legal possibility for a long_move VMRegPair is:
0N/A // 1: two stack slots (possibly unaligned)
0N/A // as neither the java or C calling convention will use registers
0N/A // for longs.
0N/A
0N/A if (src.first()->is_stack() && dst.first()->is_stack()) {
0N/A assert(src.second()->is_stack() && dst.second()->is_stack(), "must be all stack");
304N/A __ movptr(rax, Address(rbp, reg2offset_in(src.first())));
304N/A NOT_LP64(__ movptr(rbx, Address(rbp, reg2offset_in(src.second()))));
304N/A __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
304N/A NOT_LP64(__ movptr(Address(rsp, reg2offset_out(dst.second())), rbx));
0N/A } else {
0N/A ShouldNotReachHere();
0N/A }
0N/A}
0N/A
0N/A// A double move
0N/Astatic void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
0N/A
0N/A // The only legal possibilities for a double_move VMRegPair are:
0N/A // The painful thing here is that like long_move a VMRegPair might be
0N/A
0N/A // Because of the calling convention we know that src is either
0N/A // 1: a single physical register (xmm registers only)
0N/A // 2: two stack slots (possibly unaligned)
0N/A // dst can only be a pair of stack slots.
0N/A
0N/A assert(dst.first()->is_stack() && (src.first()->is_XMMRegister() || src.first()->is_stack()), "bad args");
0N/A
0N/A if (src.first()->is_stack()) {
0N/A // source is all stack
304N/A __ movptr(rax, Address(rbp, reg2offset_in(src.first())));
304N/A NOT_LP64(__ movptr(rbx, Address(rbp, reg2offset_in(src.second()))));
304N/A __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
304N/A NOT_LP64(__ movptr(Address(rsp, reg2offset_out(dst.second())), rbx));
0N/A } else {
0N/A // reg to stack
0N/A // No worries about stack alignment
0N/A __ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
0N/A // We always ignore the frame_slots arg and just use the space just below frame pointer
0N/A // which by this time is free to use
0N/A switch (ret_type) {
0N/A case T_FLOAT:
0N/A __ fstp_s(Address(rbp, -wordSize));
0N/A break;
0N/A case T_DOUBLE:
0N/A __ fstp_d(Address(rbp, -2*wordSize));
0N/A break;
0N/A case T_VOID: break;
0N/A case T_LONG:
304N/A __ movptr(Address(rbp, -wordSize), rax);
304N/A NOT_LP64(__ movptr(Address(rbp, -2*wordSize), rdx));
0N/A break;
0N/A default: {
304N/A __ movptr(Address(rbp, -wordSize), rax);
0N/A }
0N/A }
0N/A}
0N/A
0N/Avoid SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
0N/A // We always ignore the frame_slots arg and just use the space just below frame pointer
0N/A // which by this time is free to use
0N/A switch (ret_type) {
0N/A case T_FLOAT:
0N/A __ fld_s(Address(rbp, -wordSize));
0N/A break;
0N/A case T_DOUBLE:
0N/A __ fld_d(Address(rbp, -2*wordSize));
0N/A break;
0N/A case T_LONG:
304N/A __ movptr(rax, Address(rbp, -wordSize));
304N/A NOT_LP64(__ movptr(rdx, Address(rbp, -2*wordSize)));
0N/A break;
0N/A case T_VOID: break;
0N/A default: {
304N/A __ movptr(rax, Address(rbp, -wordSize));
0N/A }
0N/A }
0N/A}
0N/A
3158N/A
3158N/Astatic void save_or_restore_arguments(MacroAssembler* masm,
3158N/A const int stack_slots,
3158N/A const int total_in_args,
3158N/A const int arg_save_area,
3158N/A OopMap* map,
3158N/A VMRegPair* in_regs,
3158N/A BasicType* in_sig_bt) {
3158N/A // if map is non-NULL then the code should store the values,
3158N/A // otherwise it should load them.
3158N/A int handle_index = 0;
3158N/A // Save down double word first
3158N/A for ( int i = 0; i < total_in_args; i++) {
3158N/A if (in_regs[i].first()->is_XMMRegister() && in_sig_bt[i] == T_DOUBLE) {
3158N/A int slot = handle_index * VMRegImpl::slots_per_word + arg_save_area;
3158N/A int offset = slot * VMRegImpl::stack_slot_size;
3158N/A handle_index += 2;
3158N/A assert(handle_index <= stack_slots, "overflow");
3158N/A if (map != NULL) {
3158N/A __ movdbl(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
3158N/A } else {
3158N/A __ movdbl(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
3158N/A }
3158N/A }
3158N/A if (in_regs[i].first()->is_Register() && in_sig_bt[i] == T_LONG) {
3158N/A int slot = handle_index * VMRegImpl::slots_per_word + arg_save_area;
3158N/A int offset = slot * VMRegImpl::stack_slot_size;
3158N/A handle_index += 2;
3158N/A assert(handle_index <= stack_slots, "overflow");
3158N/A if (map != NULL) {
3158N/A __ movl(Address(rsp, offset), in_regs[i].first()->as_Register());
3158N/A if (in_regs[i].second()->is_Register()) {
3158N/A __ movl(Address(rsp, offset + 4), in_regs[i].second()->as_Register());
3158N/A }
3158N/A } else {
3158N/A __ movl(in_regs[i].first()->as_Register(), Address(rsp, offset));
3158N/A if (in_regs[i].second()->is_Register()) {
3158N/A __ movl(in_regs[i].second()->as_Register(), Address(rsp, offset + 4));
3158N/A }
3158N/A }
3158N/A }
3158N/A }
3158N/A // Save or restore single word registers
3158N/A for ( int i = 0; i < total_in_args; i++) {
3158N/A if (in_regs[i].first()->is_Register()) {
3158N/A int slot = handle_index++ * VMRegImpl::slots_per_word + arg_save_area;
3158N/A int offset = slot * VMRegImpl::stack_slot_size;
3158N/A assert(handle_index <= stack_slots, "overflow");
3158N/A if (in_sig_bt[i] == T_ARRAY && map != NULL) {
3158N/A map->set_oop(VMRegImpl::stack2reg(slot));;
3158N/A }
3158N/A
3158N/A // Value is in an input register pass we must flush it to the stack
3158N/A const Register reg = in_regs[i].first()->as_Register();
3158N/A switch (in_sig_bt[i]) {
3158N/A case T_ARRAY:
3158N/A if (map != NULL) {
3158N/A __ movptr(Address(rsp, offset), reg);
3158N/A } else {
3158N/A __ movptr(reg, Address(rsp, offset));
3158N/A }
3158N/A break;
3158N/A case T_BOOLEAN:
3158N/A case T_CHAR:
3158N/A case T_BYTE:
3158N/A case T_SHORT:
3158N/A case T_INT:
3158N/A if (map != NULL) {
3158N/A __ movl(Address(rsp, offset), reg);
3158N/A } else {
3158N/A __ movl(reg, Address(rsp, offset));
3158N/A }
3158N/A break;
3158N/A case T_OBJECT:
3158N/A default: ShouldNotReachHere();
3158N/A }
3158N/A } else if (in_regs[i].first()->is_XMMRegister()) {
3158N/A if (in_sig_bt[i] == T_FLOAT) {
3158N/A int slot = handle_index++ * VMRegImpl::slots_per_word + arg_save_area;
3158N/A int offset = slot * VMRegImpl::stack_slot_size;
3158N/A assert(handle_index <= stack_slots, "overflow");
3158N/A if (map != NULL) {
3158N/A __ movflt(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
3158N/A } else {
3158N/A __ movflt(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
3158N/A }
3158N/A }
3158N/A } else if (in_regs[i].first()->is_stack()) {
3158N/A if (in_sig_bt[i] == T_ARRAY && map != NULL) {
3158N/A int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
3158N/A map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots));
3158N/A }
3158N/A }
3158N/A }
3158N/A}
3158N/A
3158N/A// Check GC_locker::needs_gc and enter the runtime if it's true. This
3158N/A// keeps a new JNI critical region from starting until a GC has been
3158N/A// forced. Save down any oops in registers and describe them in an
3158N/A// OopMap.
3158N/Astatic void check_needs_gc_for_critical_native(MacroAssembler* masm,
3158N/A Register thread,
3158N/A int stack_slots,
3158N/A int total_c_args,
3158N/A int total_in_args,
3158N/A int arg_save_area,
3158N/A OopMapSet* oop_maps,
3158N/A VMRegPair* in_regs,
3158N/A BasicType* in_sig_bt) {
3158N/A __ block_comment("check GC_locker::needs_gc");
3158N/A Label cont;
3158N/A __ cmp8(ExternalAddress((address)GC_locker::needs_gc_address()), false);
3158N/A __ jcc(Assembler::equal, cont);
3158N/A
3158N/A // Save down any incoming oops and call into the runtime to halt for a GC
3158N/A
3158N/A OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
3158N/A
3158N/A save_or_restore_arguments(masm, stack_slots, total_in_args,
3158N/A arg_save_area, map, in_regs, in_sig_bt);
3158N/A
3158N/A address the_pc = __ pc();
3158N/A oop_maps->add_gc_map( __ offset(), map);
3158N/A __ set_last_Java_frame(thread, rsp, noreg, the_pc);
3158N/A
3158N/A __ block_comment("block_for_jni_critical");
3158N/A __ push(thread);
3158N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical)));
3158N/A __ increment(rsp, wordSize);
3158N/A
3158N/A __ get_thread(thread);
3158N/A __ reset_last_Java_frame(thread, false, true);
3158N/A
3158N/A save_or_restore_arguments(masm, stack_slots, total_in_args,
3158N/A arg_save_area, NULL, in_regs, in_sig_bt);
3158N/A
3158N/A __ bind(cont);
3158N/A#ifdef ASSERT
3158N/A if (StressCriticalJNINatives) {
3158N/A // Stress register saving
3158N/A OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
3158N/A save_or_restore_arguments(masm, stack_slots, total_in_args,
3158N/A arg_save_area, map, in_regs, in_sig_bt);
3158N/A // Destroy argument registers
3158N/A for (int i = 0; i < total_in_args - 1; i++) {
3158N/A if (in_regs[i].first()->is_Register()) {
3158N/A const Register reg = in_regs[i].first()->as_Register();
3158N/A __ xorptr(reg, reg);
3158N/A } else if (in_regs[i].first()->is_XMMRegister()) {
3158N/A __ xorpd(in_regs[i].first()->as_XMMRegister(), in_regs[i].first()->as_XMMRegister());
3158N/A } else if (in_regs[i].first()->is_FloatRegister()) {
3158N/A ShouldNotReachHere();
3158N/A } else if (in_regs[i].first()->is_stack()) {
3158N/A // Nothing to do
3158N/A } else {
3158N/A ShouldNotReachHere();
3158N/A }
3158N/A if (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_DOUBLE) {
3158N/A i++;
3158N/A }
3158N/A }
3158N/A
3158N/A save_or_restore_arguments(masm, stack_slots, total_in_args,
3158N/A arg_save_area, NULL, in_regs, in_sig_bt);
3158N/A }
3158N/A#endif
3158N/A}
3158N/A
3158N/A// Unpack an array argument into a pointer to the body and the length
3158N/A// if the array is non-null, otherwise pass 0 for both.
3158N/Astatic void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) {
3158N/A Register tmp_reg = rax;
3158N/A assert(!body_arg.first()->is_Register() || body_arg.first()->as_Register() != tmp_reg,
3158N/A "possible collision");
3158N/A assert(!length_arg.first()->is_Register() || length_arg.first()->as_Register() != tmp_reg,
3158N/A "possible collision");
3158N/A
3158N/A // Pass the length, ptr pair
3158N/A Label is_null, done;
3158N/A VMRegPair tmp(tmp_reg->as_VMReg());
3158N/A if (reg.first()->is_stack()) {
3158N/A // Load the arg up from the stack
3158N/A simple_move32(masm, reg, tmp);
3158N/A reg = tmp;
3158N/A }
3158N/A __ testptr(reg.first()->as_Register(), reg.first()->as_Register());
3158N/A __ jccb(Assembler::equal, is_null);
3158N/A __ lea(tmp_reg, Address(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type)));
3158N/A simple_move32(masm, tmp, body_arg);
3158N/A // load the length relative to the body.
3158N/A __ movl(tmp_reg, Address(tmp_reg, arrayOopDesc::length_offset_in_bytes() -
3158N/A arrayOopDesc::base_offset_in_bytes(in_elem_type)));
3158N/A simple_move32(masm, tmp, length_arg);
3158N/A __ jmpb(done);
3158N/A __ bind(is_null);
3158N/A // Pass zeros
3158N/A __ xorptr(tmp_reg, tmp_reg);
3158N/A simple_move32(masm, tmp, body_arg);
3158N/A simple_move32(masm, tmp, length_arg);
3158N/A __ bind(done);
3158N/A}
3158N/A
3932N/Astatic void verify_oop_args(MacroAssembler* masm,
4010N/A methodHandle method,
3932N/A const BasicType* sig_bt,
3932N/A const VMRegPair* regs) {
3932N/A Register temp_reg = rbx; // not part of any compiled calling seq
3932N/A if (VerifyOops) {
4010N/A for (int i = 0; i < method->size_of_parameters(); i++) {
3932N/A if (sig_bt[i] == T_OBJECT ||
3932N/A sig_bt[i] == T_ARRAY) {
3932N/A VMReg r = regs[i].first();
3932N/A assert(r->is_valid(), "bad oop arg");
3932N/A if (r->is_stack()) {
3932N/A __ movptr(temp_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
3932N/A __ verify_oop(temp_reg);
3932N/A } else {
3932N/A __ verify_oop(r->as_Register());
3932N/A }
3932N/A }
3932N/A }
3932N/A }
3932N/A}
3932N/A
3932N/Astatic void gen_special_dispatch(MacroAssembler* masm,
4010N/A methodHandle method,
3932N/A const BasicType* sig_bt,
3932N/A const VMRegPair* regs) {
4010N/A verify_oop_args(masm, method, sig_bt, regs);
4010N/A vmIntrinsics::ID iid = method->intrinsic_id();
3932N/A
3932N/A // Now write the args into the outgoing interpreter space
3932N/A bool has_receiver = false;
3932N/A Register receiver_reg = noreg;
3932N/A int member_arg_pos = -1;
3932N/A Register member_reg = noreg;
4010N/A int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid);
3932N/A if (ref_kind != 0) {
4010N/A member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument
3932N/A member_reg = rbx; // known to be free at this point
3932N/A has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind);
4010N/A } else if (iid == vmIntrinsics::_invokeBasic) {
3932N/A has_receiver = true;
3932N/A } else {
4010N/A fatal(err_msg_res("unexpected intrinsic id %d", iid));
3932N/A }
3932N/A
3932N/A if (member_reg != noreg) {
3932N/A // Load the member_arg into register, if necessary.
4010N/A SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs);
3932N/A VMReg r = regs[member_arg_pos].first();
3932N/A if (r->is_stack()) {
3932N/A __ movptr(member_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
3932N/A } else {
3932N/A // no data motion is needed
3932N/A member_reg = r->as_Register();
3932N/A }
3932N/A }
3932N/A
3932N/A if (has_receiver) {
3932N/A // Make sure the receiver is loaded into a register.
4010N/A assert(method->size_of_parameters() > 0, "oob");
3932N/A assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object");
3932N/A VMReg r = regs[0].first();
3932N/A assert(r->is_valid(), "bad receiver arg");
3932N/A if (r->is_stack()) {
3932N/A // Porting note: This assumes that compiled calling conventions always
3932N/A // pass the receiver oop in a register. If this is not true on some
3932N/A // platform, pick a temp and load the receiver from stack.
4010N/A fatal("receiver always in a register");
3932N/A receiver_reg = rcx; // known to be free at this point
3932N/A __ movptr(receiver_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
3932N/A } else {
3932N/A // no data motion is needed
3932N/A receiver_reg = r->as_Register();
3932N/A }
3932N/A }
3932N/A
3932N/A // Figure out which address we are really jumping to:
4010N/A MethodHandles::generate_method_handle_dispatch(masm, iid,
3932N/A receiver_reg, member_reg, /*for_compiler_entry:*/ true);
3932N/A}
3158N/A
0N/A// ---------------------------------------------------------------------------
0N/A// Generate a native wrapper for a given method. The method takes arguments
0N/A// in the Java compiled code convention, marshals them to the native
0N/A// convention (handlizes oops, etc), transitions to native, makes the call,
0N/A// returns to java state (possibly blocking), unhandlizes any result and
0N/A// returns.
3158N/A//
3158N/A// Critical native functions are a shorthand for the use of
3158N/A// GetPrimtiveArrayCritical and disallow the use of any other JNI
3158N/A// functions. The wrapper is expected to unpack the arguments before
3158N/A// passing them to the callee and perform checks before and after the
3158N/A// native call to ensure that they GC_locker
3158N/A// lock_critical/unlock_critical semantics are followed. Some other
3158N/A// parts of JNI setup are skipped like the tear down of the JNI handle
3158N/A// block and the check for pending exceptions it's impossible for them
3158N/A// to be thrown.
3158N/A//
3158N/A// They are roughly structured like this:
3158N/A// if (GC_locker::needs_gc())
3158N/A// SharedRuntime::block_for_jni_critical();
3158N/A// tranistion to thread_in_native
3158N/A// unpack arrray arguments and call native entry point
3158N/A// check for safepoint in progress
3158N/A// check if any thread suspend flags are set
3158N/A// call into JVM and possible unlock the JNI critical
3158N/A// if a GC was suppressed while in the critical native.
3158N/A// transition back to thread_in_Java
3158N/A// return to caller
3158N/A//
3932N/Anmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
0N/A methodHandle method,
2252N/A int compile_id,
3932N/A BasicType* in_sig_bt,
3932N/A VMRegPair* in_regs,
0N/A BasicType ret_type) {
3932N/A if (method->is_method_handle_intrinsic()) {
3932N/A vmIntrinsics::ID iid = method->intrinsic_id();
3932N/A intptr_t start = (intptr_t)__ pc();
3932N/A int vep_offset = ((intptr_t)__ pc()) - start;
3932N/A gen_special_dispatch(masm,
4010N/A method,
3932N/A in_sig_bt,
3932N/A in_regs);
3932N/A int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period
3932N/A __ flush();
3932N/A int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually
3932N/A return nmethod::new_native_nmethod(method,
3932N/A compile_id,
3932N/A masm->code(),
3932N/A vep_offset,
3932N/A frame_complete,
3932N/A stack_slots / VMRegImpl::slots_per_word,
3932N/A in_ByteSize(-1),
3932N/A in_ByteSize(-1),
3932N/A (OopMapSet*)NULL);
3932N/A }
3158N/A bool is_critical_native = true;
3158N/A address native_func = method->critical_native_function();
3158N/A if (native_func == NULL) {
3158N/A native_func = method->native_function();
3158N/A is_critical_native = false;
3158N/A }
3158N/A assert(native_func != NULL, "must have function");
0N/A
0N/A // An OopMap for lock (and class if static)
0N/A OopMapSet *oop_maps = new OopMapSet();
0N/A
0N/A // We have received a description of where all the java arg are located
0N/A // on entry to the wrapper. We need to convert these args to where
0N/A // the jni function will expect them. To figure out where they go
0N/A // we convert the java signature to a C signature by inserting
0N/A // the hidden arguments as arg[0] and possibly arg[1] (static method)
0N/A
4010N/A const int total_in_args = method->size_of_parameters();
3158N/A int total_c_args = total_in_args;
3158N/A if (!is_critical_native) {
3158N/A total_c_args += 1;
3158N/A if (method->is_static()) {
3158N/A total_c_args++;
3158N/A }
3158N/A } else {
3158N/A for (int i = 0; i < total_in_args; i++) {
3158N/A if (in_sig_bt[i] == T_ARRAY) {
3158N/A total_c_args++;
3158N/A }
3158N/A }
0N/A }
0N/A
0N/A BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
3158N/A VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
3158N/A BasicType* in_elem_bt = NULL;
0N/A
0N/A int argc = 0;
3158N/A if (!is_critical_native) {
3158N/A out_sig_bt[argc++] = T_ADDRESS;
3158N/A if (method->is_static()) {
3158N/A out_sig_bt[argc++] = T_OBJECT;
3158N/A }
3158N/A
3158N/A for (int i = 0; i < total_in_args ; i++ ) {
3158N/A out_sig_bt[argc++] = in_sig_bt[i];
3158N/A }
3158N/A } else {
3158N/A Thread* THREAD = Thread::current();
3158N/A in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args);
3158N/A SignatureStream ss(method->signature());
3158N/A for (int i = 0; i < total_in_args ; i++ ) {
3158N/A if (in_sig_bt[i] == T_ARRAY) {
3158N/A // Arrays are passed as int, elem* pair
3158N/A out_sig_bt[argc++] = T_INT;
3158N/A out_sig_bt[argc++] = T_ADDRESS;
3158N/A Symbol* atype = ss.as_symbol(CHECK_NULL);
3158N/A const char* at = atype->as_C_string();
3158N/A if (strlen(at) == 2) {
3158N/A assert(at[0] == '[', "must be");
3158N/A switch (at[1]) {
3158N/A case 'B': in_elem_bt[i] = T_BYTE; break;
3158N/A case 'C': in_elem_bt[i] = T_CHAR; break;
3158N/A case 'D': in_elem_bt[i] = T_DOUBLE; break;
3158N/A case 'F': in_elem_bt[i] = T_FLOAT; break;
3158N/A case 'I': in_elem_bt[i] = T_INT; break;
3158N/A case 'J': in_elem_bt[i] = T_LONG; break;
3158N/A case 'S': in_elem_bt[i] = T_SHORT; break;
3158N/A case 'Z': in_elem_bt[i] = T_BOOLEAN; break;
3158N/A default: ShouldNotReachHere();
3158N/A }
3158N/A }
3158N/A } else {
3158N/A out_sig_bt[argc++] = in_sig_bt[i];
3158N/A in_elem_bt[i] = T_VOID;
3158N/A }
3158N/A if (in_sig_bt[i] != T_VOID) {
3158N/A assert(in_sig_bt[i] == ss.type(), "must match");
3158N/A ss.next();
3158N/A }
3158N/A }
0N/A }
0N/A
0N/A // Now figure out where the args must be stored and how much stack space
3158N/A // they require.
0N/A int out_arg_slots;
0N/A out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
0N/A
0N/A // Compute framesize for the wrapper. We need to handlize all oops in
0N/A // registers a max of 2 on x86.
0N/A
0N/A // Calculate the total number of stack slots we will need.
0N/A
0N/A // First count the abi requirement plus all of the outgoing args
0N/A int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
0N/A
0N/A // Now the space for the inbound oop handle area
3158N/A int total_save_slots = 2 * VMRegImpl::slots_per_word; // 2 arguments passed in registers
3158N/A if (is_critical_native) {
3158N/A // Critical natives may have to call out so they need a save area
3158N/A // for register arguments.
3158N/A int double_slots = 0;
3158N/A int single_slots = 0;
3158N/A for ( int i = 0; i < total_in_args; i++) {
3158N/A if (in_regs[i].first()->is_Register()) {
3158N/A const Register reg = in_regs[i].first()->as_Register();
3158N/A switch (in_sig_bt[i]) {
3932N/A case T_ARRAY: // critical array (uses 2 slots on LP64)
3158N/A case T_BOOLEAN:
3158N/A case T_BYTE:
3158N/A case T_SHORT:
3158N/A case T_CHAR:
3158N/A case T_INT: single_slots++; break;
3158N/A case T_LONG: double_slots++; break;
3158N/A default: ShouldNotReachHere();
3158N/A }
3158N/A } else if (in_regs[i].first()->is_XMMRegister()) {
3158N/A switch (in_sig_bt[i]) {
3158N/A case T_FLOAT: single_slots++; break;
3158N/A case T_DOUBLE: double_slots++; break;
3158N/A default: ShouldNotReachHere();
3158N/A }
3158N/A } else if (in_regs[i].first()->is_FloatRegister()) {
3158N/A ShouldNotReachHere();
3158N/A }
3158N/A }
3158N/A total_save_slots = double_slots * 2 + single_slots;
3158N/A // align the save area
3158N/A if (double_slots != 0) {
3158N/A stack_slots = round_to(stack_slots, 2);
3158N/A }
3158N/A }
0N/A
0N/A int oop_handle_offset = stack_slots;
3158N/A stack_slots += total_save_slots;
0N/A
0N/A // Now any space we need for handlizing a klass if static method
0N/A
0N/A int klass_slot_offset = 0;
0N/A int klass_offset = -1;
0N/A int lock_slot_offset = 0;
0N/A bool is_static = false;
0N/A
0N/A if (method->is_static()) {
0N/A klass_slot_offset = stack_slots;
0N/A stack_slots += VMRegImpl::slots_per_word;
0N/A klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
0N/A is_static = true;
0N/A }
0N/A
0N/A // Plus a lock if needed
0N/A
0N/A if (method->is_synchronized()) {
0N/A lock_slot_offset = stack_slots;
0N/A stack_slots += VMRegImpl::slots_per_word;
0N/A }
0N/A
0N/A // Now a place (+2) to save return values or temp during shuffling
0N/A // + 2 for return address (which we own) and saved rbp,
0N/A stack_slots += 4;
0N/A
0N/A // Ok The space we have allocated will look like:
0N/A //
0N/A //
0N/A // FP-> | |
0N/A // |---------------------|
0N/A // | 2 slots for moves |
0N/A // |---------------------|
0N/A // | lock box (if sync) |
0N/A // |---------------------| <- lock_slot_offset (-lock_slot_rbp_offset)
0N/A // | klass (if static) |
0N/A // |---------------------| <- klass_slot_offset
0N/A // | oopHandle area |
0N/A // |---------------------| <- oop_handle_offset (a max of 2 registers)
0N/A // | outbound memory |
0N/A // | based arguments |
0N/A // | |
0N/A // |---------------------|
0N/A // | |
0N/A // SP-> | out_preserved_slots |
0N/A //
0N/A //
0N/A // ****************************************************************************
0N/A // WARNING - on Windows Java Natives use pascal calling convention and pop the
0N/A // arguments off of the stack after the jni call. Before the call we can use
0N/A // instructions that are SP relative. After the jni call we switch to FP
0N/A // relative instructions instead of re-adjusting the stack on windows.
0N/A // ****************************************************************************
0N/A
0N/A
0N/A // Now compute actual number of stack words we need rounding to make
0N/A // stack properly aligned.
524N/A stack_slots = round_to(stack_slots, StackAlignmentInSlots);
0N/A
0N/A int stack_size = stack_slots * VMRegImpl::stack_slot_size;
0N/A
0N/A intptr_t start = (intptr_t)__ pc();
0N/A
0N/A // First thing make an ic check to see if we should even be here
0N/A
0N/A // We are free to use all registers as temps without saving them and
3158N/A // restoring them except rbp. rbp is the only callee save register
0N/A // as far as the interpreter and the compiler(s) are concerned.
0N/A
0N/A
0N/A const Register ic_reg = rax;
0N/A const Register receiver = rcx;
0N/A Label hit;
0N/A Label exception_pending;
0N/A
0N/A __ verify_oop(receiver);
304N/A __ cmpptr(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes()));
0N/A __ jcc(Assembler::equal, hit);
0N/A
0N/A __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
0N/A
0N/A // verified entry must be aligned for code patching.
0N/A // and the first 5 bytes must be in the same cache line
0N/A // if we align at 8 then we will be sure 5 bytes are in the same line
0N/A __ align(8);
0N/A
0N/A __ bind(hit);
0N/A
0N/A int vep_offset = ((intptr_t)__ pc()) - start;
0N/A
0N/A#ifdef COMPILER1
0N/A if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) {
0N/A // Object.hashCode can pull the hashCode from the header word
0N/A // instead of doing a full VM transition once it's been computed.
0N/A // Since hashCode is usually polymorphic at call sites we can't do
0N/A // this optimization at the call site without a lot of work.
0N/A Label slowCase;
0N/A Register receiver = rcx;
0N/A Register result = rax;
304N/A __ movptr(result, Address(receiver, oopDesc::mark_offset_in_bytes()));
0N/A
0N/A // check if locked
304N/A __ testptr(result, markOopDesc::unlocked_value);
0N/A __ jcc (Assembler::zero, slowCase);
0N/A
0N/A if (UseBiasedLocking) {
0N/A // Check if biased and fall through to runtime if so
304N/A __ testptr(result, markOopDesc::biased_lock_bit_in_place);
0N/A __ jcc (Assembler::notZero, slowCase);
0N/A }
0N/A
0N/A // get hash
304N/A __ andptr(result, markOopDesc::hash_mask_in_place);
0N/A // test if hashCode exists
0N/A __ jcc (Assembler::zero, slowCase);
304N/A __ shrptr(result, markOopDesc::hash_shift);
0N/A __ ret(0);
0N/A __ bind (slowCase);
0N/A }
0N/A#endif // COMPILER1
0N/A
0N/A // The instruction at the verified entry point must be 5 bytes or longer
0N/A // because it can be patched on the fly by make_non_entrant. The stack bang
0N/A // instruction fits that requirement.
0N/A
0N/A // Generate stack overflow check
0N/A
0N/A if (UseStackBanging) {
0N/A __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
0N/A } else {
0N/A // need a 5 byte instruction to allow MT safe patching to non-entrant
0N/A __ fat_nop();
0N/A }
0N/A
0N/A // Generate a new frame for the wrapper.
0N/A __ enter();
3158N/A // -2 because return address is already present and so is saved rbp
304N/A __ subptr(rsp, stack_size - 2*wordSize);
0N/A
3158N/A // Frame is now completed as far as size and linkage.
0N/A int frame_complete = ((intptr_t)__ pc()) - start;
0N/A
0N/A // Calculate the difference between rsp and rbp,. We need to know it
0N/A // after the native call because on windows Java Natives will pop
0N/A // the arguments and it is painful to do rsp relative addressing
0N/A // in a platform independent way. So after the call we switch to
0N/A // rbp, relative addressing.
0N/A
0N/A int fp_adjustment = stack_size - 2*wordSize;
0N/A
0N/A#ifdef COMPILER2
0N/A // C2 may leave the stack dirty if not in SSE2+ mode
0N/A if (UseSSE >= 2) {
0N/A __ verify_FPU(0, "c2i transition should have clean FPU stack");
0N/A } else {
0N/A __ empty_FPU_stack();
0N/A }
0N/A#endif /* COMPILER2 */
0N/A
0N/A // Compute the rbp, offset for any slots used after the jni call
0N/A
0N/A int lock_slot_rbp_offset = (lock_slot_offset*VMRegImpl::stack_slot_size) - fp_adjustment;
0N/A
0N/A // We use rdi as a thread pointer because it is callee save and
0N/A // if we load it once it is usable thru the entire wrapper
0N/A const Register thread = rdi;
0N/A
0N/A // We use rsi as the oop handle for the receiver/klass
0N/A // It is callee save so it survives the call to native
0N/A
0N/A const Register oop_handle_reg = rsi;
0N/A
0N/A __ get_thread(thread);
0N/A
3158N/A if (is_critical_native) {
3158N/A check_needs_gc_for_critical_native(masm, thread, stack_slots, total_c_args, total_in_args,
3158N/A oop_handle_offset, oop_maps, in_regs, in_sig_bt);
3158N/A }
0N/A
0N/A //
0N/A // We immediately shuffle the arguments so that any vm call we have to
0N/A // make from here on out (sync slow path, jvmti, etc.) we will have
0N/A // captured the oops from our caller and have a valid oopMap for
0N/A // them.
0N/A
0N/A // -----------------
0N/A // The Grand Shuffle
0N/A //
0N/A // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv*
0N/A // and, if static, the class mirror instead of a receiver. This pretty much
0N/A // guarantees that register layout will not match (and x86 doesn't use reg
0N/A // parms though amd does). Since the native abi doesn't use register args
0N/A // and the java conventions does we don't have to worry about collisions.
0N/A // All of our moved are reg->stack or stack->stack.
0N/A // We ignore the extra arguments during the shuffle and handle them at the
0N/A // last moment. The shuffle is described by the two calling convention
0N/A // vectors we have in our possession. We simply walk the java vector to
0N/A // get the source locations and the c vector to get the destinations.
0N/A
3158N/A int c_arg = is_critical_native ? 0 : (method->is_static() ? 2 : 1 );
0N/A
0N/A // Record rsp-based slot for receiver on stack for non-static methods
0N/A int receiver_offset = -1;
0N/A
0N/A // This is a trick. We double the stack slots so we can claim
0N/A // the oops in the caller's frame. Since we are sure to have
0N/A // more args than the caller doubling is enough to make
0N/A // sure we can capture all the incoming oop args from the
0N/A // caller.
0N/A //
0N/A OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
0N/A
0N/A // Mark location of rbp,
0N/A // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, rbp->as_VMReg());
0N/A
0N/A // We know that we only have args in at most two integer registers (rcx, rdx). So rax, rbx
0N/A // Are free to temporaries if we have to do stack to steck moves.
0N/A // All inbound args are referenced based on rbp, and all outbound args via rsp.
0N/A
3158N/A for (int i = 0; i < total_in_args ; i++, c_arg++ ) {
0N/A switch (in_sig_bt[i]) {
0N/A case T_ARRAY:
3158N/A if (is_critical_native) {
3158N/A unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]);
3158N/A c_arg++;
3158N/A break;
3158N/A }
0N/A case T_OBJECT:
3158N/A assert(!is_critical_native, "no oop arguments");
0N/A object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
0N/A ((i == 0) && (!is_static)),
0N/A &receiver_offset);
0N/A break;
0N/A case T_VOID:
0N/A break;
0N/A
0N/A case T_FLOAT:
0N/A float_move(masm, in_regs[i], out_regs[c_arg]);
0N/A break;
0N/A
0N/A case T_DOUBLE:
0N/A assert( i + 1 < total_in_args &&
0N/A in_sig_bt[i + 1] == T_VOID &&
0N/A out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
0N/A double_move(masm, in_regs[i], out_regs[c_arg]);
0N/A break;
0N/A
0N/A case T_LONG :
0N/A long_move(masm, in_regs[i], out_regs[c_arg]);
0N/A break;
0N/A
0N/A case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
0N/A
0N/A default:
0N/A simple_move32(masm, in_regs[i], out_regs[c_arg]);
0N/A }
0N/A }
0N/A
0N/A // Pre-load a static method's oop into rsi. Used both by locking code and
0N/A // the normal JNI call code.
3158N/A if (method->is_static() && !is_critical_native) {
0N/A
0N/A // load opp into a register
0N/A __ movoop(oop_handle_reg, JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()));
0N/A
0N/A // Now handlize the static class mirror it's known not-null.
304N/A __ movptr(Address(rsp, klass_offset), oop_handle_reg);
0N/A map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
0N/A
0N/A // Now get the handle
304N/A __ lea(oop_handle_reg, Address(rsp, klass_offset));
0N/A // store the klass handle as second argument
304N/A __ movptr(Address(rsp, wordSize), oop_handle_reg);
0N/A }
0N/A
0N/A // Change state to native (we save the return address in the thread, since it might not
0N/A // be pushed on the stack when we do a a stack traversal). It is enough that the pc()
0N/A // points into the right code segment. It does not have to be the correct return pc.
0N/A // We use the same pc/oopMap repeatedly when we call out
0N/A
0N/A intptr_t the_pc = (intptr_t) __ pc();
0N/A oop_maps->add_gc_map(the_pc - start, map);
0N/A
0N/A __ set_last_Java_frame(thread, rsp, noreg, (address)the_pc);
0N/A
0N/A
0N/A // We have all of the arguments setup at this point. We must not touch any register
0N/A // argument registers at this point (what if we save/restore them there are no oop?
0N/A
0N/A {
0N/A SkipIfEqual skip_if(masm, &DTraceMethodProbes, 0);
0N/A __ movoop(rax, JNIHandles::make_local(method()));
0N/A __ call_VM_leaf(
0N/A CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
0N/A thread, rax);
0N/A }
0N/A
610N/A // RedefineClasses() tracing support for obsolete method entry
610N/A if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
610N/A __ movoop(rax, JNIHandles::make_local(method()));
610N/A __ call_VM_leaf(
610N/A CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
610N/A thread, rax);
610N/A }
610N/A
0N/A // These are register definitions we need for locking/unlocking
0N/A const Register swap_reg = rax; // Must use rax, for cmpxchg instruction
0N/A const Register obj_reg = rcx; // Will contain the oop
0N/A const Register lock_reg = rdx; // Address of compiler lock object (BasicLock)
0N/A
0N/A Label slow_path_lock;
0N/A Label lock_done;
0N/A
0N/A // Lock a synchronized method
0N/A if (method->is_synchronized()) {
3158N/A assert(!is_critical_native, "unhandled");
0N/A
0N/A
0N/A const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes();
0N/A
0N/A // Get the handle (the 2nd argument)
304N/A __ movptr(oop_handle_reg, Address(rsp, wordSize));
0N/A
0N/A // Get address of the box
0N/A
304N/A __ lea(lock_reg, Address(rbp, lock_slot_rbp_offset));
0N/A
0N/A // Load the oop from the handle
304N/A __ movptr(obj_reg, Address(oop_handle_reg, 0));
0N/A
0N/A if (UseBiasedLocking) {
0N/A // Note that oop_handle_reg is trashed during this call
0N/A __ biased_locking_enter(lock_reg, obj_reg, swap_reg, oop_handle_reg, false, lock_done, &slow_path_lock);
0N/A }
0N/A
0N/A // Load immediate 1 into swap_reg %rax,
304N/A __ movptr(swap_reg, 1);
0N/A
0N/A // Load (object->mark() | 1) into swap_reg %rax,
304N/A __ orptr(swap_reg, Address(obj_reg, 0));
0N/A
0N/A // Save (object->mark() | 1) into BasicLock's displaced header
304N/A __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
0N/A
0N/A if (os::is_MP()) {
0N/A __ lock();
0N/A }
0N/A
0N/A // src -> dest iff dest == rax, else rax, <- dest
0N/A // *obj_reg = lock_reg iff *obj_reg == rax, else rax, = *(obj_reg)
304N/A __ cmpxchgptr(lock_reg, Address(obj_reg, 0));
0N/A __ jcc(Assembler::equal, lock_done);
0N/A
0N/A // Test if the oopMark is an obvious stack pointer, i.e.,
0N/A // 1) (mark & 3) == 0, and
0N/A // 2) rsp <= mark < mark + os::pagesize()
0N/A // These 3 tests can be done by evaluating the following
0N/A // expression: ((mark - rsp) & (3 - os::vm_page_size())),
0N/A // assuming both stack pointer and pagesize have their
0N/A // least significant 2 bits clear.
0N/A // NOTE: the oopMark is in swap_reg %rax, as the result of cmpxchg
0N/A
304N/A __ subptr(swap_reg, rsp);
304N/A __ andptr(swap_reg, 3 - os::vm_page_size());
0N/A
0N/A // Save the test result, for recursive case, the result is zero
304N/A __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
0N/A __ jcc(Assembler::notEqual, slow_path_lock);
0N/A // Slow path will re-enter here
0N/A __ bind(lock_done);
0N/A
0N/A if (UseBiasedLocking) {
0N/A // Re-fetch oop_handle_reg as we trashed it above
304N/A __ movptr(oop_handle_reg, Address(rsp, wordSize));
0N/A }
0N/A }
0N/A
0N/A
0N/A // Finally just about ready to make the JNI call
0N/A
0N/A
0N/A // get JNIEnv* which is first argument to native
3158N/A if (!is_critical_native) {
3158N/A __ lea(rdx, Address(thread, in_bytes(JavaThread::jni_environment_offset())));
3158N/A __ movptr(Address(rsp, 0), rdx);
3158N/A }
0N/A
0N/A // Now set thread in native
0N/A __ movl(Address(thread, JavaThread::thread_state_offset()), _thread_in_native);
0N/A
3158N/A __ call(RuntimeAddress(native_func));
0N/A
4442N/A // Verify or restore cpu control state after JNI call
4442N/A __ restore_cpu_control_state_after_jni();
4442N/A
0N/A // WARNING - on Windows Java Natives use pascal calling convention and pop the
0N/A // arguments off of the stack. We could just re-adjust the stack pointer here
0N/A // and continue to do SP relative addressing but we instead switch to FP
0N/A // relative addressing.
0N/A
0N/A // Unpack native results.
0N/A switch (ret_type) {
0N/A case T_BOOLEAN: __ c2bool(rax); break;
304N/A case T_CHAR : __ andptr(rax, 0xFFFF); break;
0N/A case T_BYTE : __ sign_extend_byte (rax); break;
0N/A case T_SHORT : __ sign_extend_short(rax); break;
0N/A case T_INT : /* nothing to do */ break;
0N/A case T_DOUBLE :
0N/A case T_FLOAT :
0N/A // Result is in st0 we'll save as needed
0N/A break;
0N/A case T_ARRAY: // Really a handle
0N/A case T_OBJECT: // Really a handle
0N/A break; // can't de-handlize until after safepoint check
0N/A case T_VOID: break;
0N/A case T_LONG: break;
0N/A default : ShouldNotReachHere();
0N/A }
0N/A
0N/A // Switch thread to "native transition" state before reading the synchronization state.
0N/A // This additional state is necessary because reading and testing the synchronization
0N/A // state is not atomic w.r.t. GC, as this scenario demonstrates:
0N/A // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
0N/A // VM thread changes sync state to synchronizing and suspends threads for GC.
0N/A // Thread A is resumed to finish this native method, but doesn't block here since it
0N/A // didn't see any synchronization is progress, and escapes.
0N/A __ movl(Address(thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
0N/A
0N/A if(os::is_MP()) {
0N/A if (UseMembar) {
304N/A // Force this write out before the read below
304N/A __ membar(Assembler::Membar_mask_bits(
304N/A Assembler::LoadLoad | Assembler::LoadStore |
304N/A Assembler::StoreLoad | Assembler::StoreStore));
0N/A } else {
0N/A // Write serialization page so VM thread can do a pseudo remote membar.
0N/A // We use the current thread pointer to calculate a thread specific
0N/A // offset to write to within the page. This minimizes bus traffic
0N/A // due to cache line collision.
0N/A __ serialize_memory(thread, rcx);
0N/A }
0N/A }
0N/A
0N/A if (AlwaysRestoreFPU) {
0N/A // Make sure the control word is correct.
0N/A __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
0N/A }
0N/A
3158N/A Label after_transition;
3158N/A
0N/A // check for safepoint operation in progress and/or pending suspend requests
0N/A { Label Continue;
0N/A
0N/A __ cmp32(ExternalAddress((address)SafepointSynchronize::address_of_state()),
0N/A SafepointSynchronize::_not_synchronized);
0N/A
0N/A Label L;
0N/A __ jcc(Assembler::notEqual, L);
0N/A __ cmpl(Address(thread, JavaThread::suspend_flags_offset()), 0);
0N/A __ jcc(Assembler::equal, Continue);
0N/A __ bind(L);
0N/A
0N/A // Don't use call_VM as it will see a possible pending exception and forward it
0N/A // and never return here preventing us from clearing _last_native_pc down below.
0N/A // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are
0N/A // preserved and correspond to the bcp/locals pointers. So we do a runtime call
0N/A // by hand.
0N/A //
0N/A save_native_result(masm, ret_type, stack_slots);
304N/A __ push(thread);
3158N/A if (!is_critical_native) {
3158N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address,
3158N/A JavaThread::check_special_condition_for_native_trans)));
3158N/A } else {
3158N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address,
3158N/A JavaThread::check_special_condition_for_native_trans_and_transition)));
3158N/A }
0N/A __ increment(rsp, wordSize);
0N/A // Restore any method result value
0N/A restore_native_result(masm, ret_type, stack_slots);
0N/A
3158N/A if (is_critical_native) {
3158N/A // The call above performed the transition to thread_in_Java so
3158N/A // skip the transition logic below.
3158N/A __ jmpb(after_transition);
3158N/A }
3158N/A
0N/A __ bind(Continue);
0N/A }
0N/A
0N/A // change thread state
0N/A __ movl(Address(thread, JavaThread::thread_state_offset()), _thread_in_Java);
3158N/A __ bind(after_transition);
0N/A
0N/A Label reguard;
0N/A Label reguard_done;
0N/A __ cmpl(Address(thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_disabled);
0N/A __ jcc(Assembler::equal, reguard);
0N/A
0N/A // slow path reguard re-enters here
0N/A __ bind(reguard_done);
0N/A
0N/A // Handle possible exception (will unlock if necessary)
0N/A
0N/A // native result if any is live
0N/A
0N/A // Unlock
0N/A Label slow_path_unlock;
0N/A Label unlock_done;
0N/A if (method->is_synchronized()) {
0N/A
0N/A Label done;
0N/A
0N/A // Get locked oop from the handle we passed to jni
304N/A __ movptr(obj_reg, Address(oop_handle_reg, 0));
0N/A
0N/A if (UseBiasedLocking) {
0N/A __ biased_locking_exit(obj_reg, rbx, done);
0N/A }
0N/A
0N/A // Simple recursive lock?
0N/A
304N/A __ cmpptr(Address(rbp, lock_slot_rbp_offset), (int32_t)NULL_WORD);
0N/A __ jcc(Assembler::equal, done);
0N/A
0N/A // Must save rax, if if it is live now because cmpxchg must use it
0N/A if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
0N/A save_native_result(masm, ret_type, stack_slots);
0N/A }
0N/A
0N/A // get old displaced header
304N/A __ movptr(rbx, Address(rbp, lock_slot_rbp_offset));
0N/A
0N/A // get address of the stack lock
304N/A __ lea(rax, Address(rbp, lock_slot_rbp_offset));
0N/A
0N/A // Atomic swap old header if oop still contains the stack lock
0N/A if (os::is_MP()) {
0N/A __ lock();
0N/A }
0N/A
0N/A // src -> dest iff dest == rax, else rax, <- dest
0N/A // *obj_reg = rbx, iff *obj_reg == rax, else rax, = *(obj_reg)
304N/A __ cmpxchgptr(rbx, Address(obj_reg, 0));
0N/A __ jcc(Assembler::notEqual, slow_path_unlock);
0N/A
0N/A // slow path re-enters here
0N/A __ bind(unlock_done);
0N/A if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
0N/A restore_native_result(masm, ret_type, stack_slots);
0N/A }
0N/A
0N/A __ bind(done);
0N/A
0N/A }
0N/A
0N/A {
0N/A SkipIfEqual skip_if(masm, &DTraceMethodProbes, 0);
0N/A // Tell dtrace about this method exit
0N/A save_native_result(masm, ret_type, stack_slots);
0N/A __ movoop(rax, JNIHandles::make_local(method()));
0N/A __ call_VM_leaf(
0N/A CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
0N/A thread, rax);
0N/A restore_native_result(masm, ret_type, stack_slots);
0N/A }
0N/A
0N/A // We can finally stop using that last_Java_frame we setup ages ago
0N/A
0N/A __ reset_last_Java_frame(thread, false, true);
0N/A
0N/A // Unpack oop result
0N/A if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
0N/A Label L;
304N/A __ cmpptr(rax, (int32_t)NULL_WORD);
0N/A __ jcc(Assembler::equal, L);
304N/A __ movptr(rax, Address(rax, 0));
0N/A __ bind(L);
0N/A __ verify_oop(rax);
0N/A }
0N/A
3158N/A if (!is_critical_native) {
3158N/A // reset handle block
3158N/A __ movptr(rcx, Address(thread, JavaThread::active_handles_offset()));
3158N/A __ movptr(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), NULL_WORD);
3158N/A
3158N/A // Any exception pending?
3158N/A __ cmpptr(Address(thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
3158N/A __ jcc(Assembler::notEqual, exception_pending);
3158N/A }
0N/A
0N/A // no exception, we're almost done
0N/A
0N/A // check that only result value is on FPU stack
0N/A __ verify_FPU(ret_type == T_FLOAT || ret_type == T_DOUBLE ? 1 : 0, "native_wrapper normal exit");
0N/A
0N/A // Fixup floating pointer results so that result looks like a return from a compiled method
0N/A if (ret_type == T_FLOAT) {
0N/A if (UseSSE >= 1) {
0N/A // Pop st0 and store as float and reload into xmm register
0N/A __ fstp_s(Address(rbp, -4));
0N/A __ movflt(xmm0, Address(rbp, -4));
0N/A }
0N/A } else if (ret_type == T_DOUBLE) {
0N/A if (UseSSE >= 2) {
0N/A // Pop st0 and store as double and reload into xmm register
0N/A __ fstp_d(Address(rbp, -8));
0N/A __ movdbl(xmm0, Address(rbp, -8));
0N/A }
0N/A }
0N/A
0N/A // Return
0N/A
0N/A __ leave();
0N/A __ ret(0);
0N/A
0N/A // Unexpected paths are out of line and go here
0N/A
0N/A // Slow path locking & unlocking
0N/A if (method->is_synchronized()) {
0N/A
0N/A // BEGIN Slow path lock
0N/A
0N/A __ bind(slow_path_lock);
0N/A
0N/A // has last_Java_frame setup. No exceptions so do vanilla call not call_VM
0N/A // args are (oop obj, BasicLock* lock, JavaThread* thread)
304N/A __ push(thread);
304N/A __ push(lock_reg);
304N/A __ push(obj_reg);
0N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C)));
304N/A __ addptr(rsp, 3*wordSize);
0N/A
0N/A#ifdef ASSERT
0N/A { Label L;
304N/A __ cmpptr(Address(thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
0N/A __ jcc(Assembler::equal, L);
0N/A __ stop("no pending exception allowed on exit from monitorenter");
0N/A __ bind(L);
0N/A }
0N/A#endif
0N/A __ jmp(lock_done);
0N/A
0N/A // END Slow path lock
0N/A
0N/A // BEGIN Slow path unlock
0N/A __ bind(slow_path_unlock);
0N/A
0N/A // Slow path unlock
0N/A
0N/A if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
0N/A save_native_result(masm, ret_type, stack_slots);
0N/A }
0N/A // Save pending exception around call to VM (which contains an EXCEPTION_MARK)
0N/A
304N/A __ pushptr(Address(thread, in_bytes(Thread::pending_exception_offset())));
512N/A __ movptr(Address(thread, in_bytes(Thread::pending_exception_offset())), NULL_WORD);
0N/A
0N/A
0N/A // should be a peal
0N/A // +wordSize because of the push above
304N/A __ lea(rax, Address(rbp, lock_slot_rbp_offset));
304N/A __ push(rax);
304N/A
304N/A __ push(obj_reg);
0N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C)));
304N/A __ addptr(rsp, 2*wordSize);
0N/A#ifdef ASSERT
0N/A {
0N/A Label L;
304N/A __ cmpptr(Address(thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
0N/A __ jcc(Assembler::equal, L);
0N/A __ stop("no pending exception allowed on exit complete_monitor_unlocking_C");
0N/A __ bind(L);
0N/A }
0N/A#endif /* ASSERT */
0N/A
304N/A __ popptr(Address(thread, in_bytes(Thread::pending_exception_offset())));
0N/A
0N/A if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
0N/A restore_native_result(masm, ret_type, stack_slots);
0N/A }
0N/A __ jmp(unlock_done);
0N/A // END Slow path unlock
0N/A
0N/A }
0N/A
0N/A // SLOW PATH Reguard the stack if needed
0N/A
0N/A __ bind(reguard);
0N/A save_native_result(masm, ret_type, stack_slots);
0N/A {
0N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)));
0N/A }
0N/A restore_native_result(masm, ret_type, stack_slots);
0N/A __ jmp(reguard_done);
0N/A
0N/A
0N/A // BEGIN EXCEPTION PROCESSING
0N/A
3158N/A if (!is_critical_native) {
3158N/A // Forward the exception
3158N/A __ bind(exception_pending);
3158N/A
3158N/A // remove possible return value from FPU register stack
3158N/A __ empty_FPU_stack();
3158N/A
3158N/A // pop our frame
3158N/A __ leave();
3158N/A // and forward the exception
3158N/A __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3158N/A }
0N/A
0N/A __ flush();
0N/A
0N/A nmethod *nm = nmethod::new_native_nmethod(method,
2252N/A compile_id,
0N/A masm->code(),
0N/A vep_offset,
0N/A frame_complete,
0N/A stack_slots / VMRegImpl::slots_per_word,
0N/A (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
0N/A in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size),
0N/A oop_maps);
3158N/A
3158N/A if (is_critical_native) {
3158N/A nm->set_lazy_critical_native(true);
3158N/A }
3158N/A
0N/A return nm;
0N/A
0N/A}
0N/A
116N/A#ifdef HAVE_DTRACE_H
116N/A// ---------------------------------------------------------------------------
116N/A// Generate a dtrace nmethod for a given signature. The method takes arguments
116N/A// in the Java compiled code convention, marshals them to the native
116N/A// abi and then leaves nops at the position you would expect to call a native
116N/A// function. When the probe is enabled the nops are replaced with a trap
116N/A// instruction that dtrace inserts and the trace will cause a notification
116N/A// to dtrace.
116N/A//
116N/A// The probes are only able to take primitive types and java/lang/String as
116N/A// arguments. No other java types are allowed. Strings are converted to utf8
116N/A// strings so that from dtrace point of view java strings are converted to C
116N/A// strings. There is an arbitrary fixed limit on the total space that a method
116N/A// can use for converting the strings. (256 chars per string in the signature).
116N/A// So any java string larger then this is truncated.
116N/A
116N/Anmethod *SharedRuntime::generate_dtrace_nmethod(
116N/A MacroAssembler *masm, methodHandle method) {
116N/A
116N/A // generate_dtrace_nmethod is guarded by a mutex so we are sure to
116N/A // be single threaded in this method.
116N/A assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
116N/A
116N/A // Fill in the signature array, for the calling-convention call.
116N/A int total_args_passed = method->size_of_parameters();
116N/A
116N/A BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
116N/A VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
116N/A
116N/A // The signature we are going to use for the trap that dtrace will see
116N/A // java/lang/String is converted. We drop "this" and any other object
116N/A // is converted to NULL. (A one-slot java/lang/Long object reference
116N/A // is converted to a two-slot long, which is why we double the allocation).
116N/A BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
116N/A VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
116N/A
116N/A int i=0;
116N/A int total_strings = 0;
116N/A int first_arg_to_pass = 0;
116N/A int total_c_args = 0;
116N/A
116N/A if( !method->is_static() ) { // Pass in receiver first
116N/A in_sig_bt[i++] = T_OBJECT;
116N/A first_arg_to_pass = 1;
116N/A }
116N/A
116N/A // We need to convert the java args to where a native (non-jni) function
116N/A // would expect them. To figure out where they go we convert the java
116N/A // signature to a C signature.
116N/A
116N/A SignatureStream ss(method->signature());
116N/A for ( ; !ss.at_return_type(); ss.next()) {
116N/A BasicType bt = ss.type();
116N/A in_sig_bt[i++] = bt; // Collect remaining bits of signature
116N/A out_sig_bt[total_c_args++] = bt;
116N/A if( bt == T_OBJECT) {
2062N/A Symbol* s = ss.as_symbol_or_null(); // symbol is created
116N/A if (s == vmSymbols::java_lang_String()) {
116N/A total_strings++;
116N/A out_sig_bt[total_c_args-1] = T_ADDRESS;
116N/A } else if (s == vmSymbols::java_lang_Boolean() ||
116N/A s == vmSymbols::java_lang_Character() ||
116N/A s == vmSymbols::java_lang_Byte() ||
116N/A s == vmSymbols::java_lang_Short() ||
116N/A s == vmSymbols::java_lang_Integer() ||
116N/A s == vmSymbols::java_lang_Float()) {
116N/A out_sig_bt[total_c_args-1] = T_INT;
116N/A } else if (s == vmSymbols::java_lang_Long() ||
116N/A s == vmSymbols::java_lang_Double()) {
116N/A out_sig_bt[total_c_args-1] = T_LONG;
116N/A out_sig_bt[total_c_args++] = T_VOID;
116N/A }
116N/A } else if ( bt == T_LONG || bt == T_DOUBLE ) {
116N/A in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
116N/A out_sig_bt[total_c_args++] = T_VOID;
116N/A }
116N/A }
116N/A
116N/A assert(i==total_args_passed, "validly parsed signature");
116N/A
116N/A // Now get the compiled-Java layout as input arguments
116N/A int comp_args_on_stack;
116N/A comp_args_on_stack = SharedRuntime::java_calling_convention(
116N/A in_sig_bt, in_regs, total_args_passed, false);
116N/A
116N/A // Now figure out where the args must be stored and how much stack space
116N/A // they require (neglecting out_preserve_stack_slots).
116N/A
116N/A int out_arg_slots;
116N/A out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
116N/A
116N/A // Calculate the total number of stack slots we will need.
116N/A
116N/A // First count the abi requirement plus all of the outgoing args
116N/A int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
116N/A
116N/A // Now space for the string(s) we must convert
116N/A
116N/A int* string_locs = NEW_RESOURCE_ARRAY(int, total_strings + 1);
116N/A for (i = 0; i < total_strings ; i++) {
116N/A string_locs[i] = stack_slots;
116N/A stack_slots += max_dtrace_string_size / VMRegImpl::stack_slot_size;
116N/A }
116N/A
116N/A // + 2 for return address (which we own) and saved rbp,
116N/A
116N/A stack_slots += 2;
116N/A
116N/A // Ok The space we have allocated will look like:
116N/A //
116N/A //
116N/A // FP-> | |
116N/A // |---------------------|
116N/A // | string[n] |
116N/A // |---------------------| <- string_locs[n]
116N/A // | string[n-1] |
116N/A // |---------------------| <- string_locs[n-1]
116N/A // | ... |
116N/A // | ... |
116N/A // |---------------------| <- string_locs[1]
116N/A // | string[0] |
116N/A // |---------------------| <- string_locs[0]
116N/A // | outbound memory |
116N/A // | based arguments |
116N/A // | |
116N/A // |---------------------|
116N/A // | |
116N/A // SP-> | out_preserved_slots |
116N/A //
116N/A //
116N/A
116N/A // Now compute actual number of stack words we need rounding to make
116N/A // stack properly aligned.
116N/A stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word);
116N/A
116N/A int stack_size = stack_slots * VMRegImpl::stack_slot_size;
116N/A
116N/A intptr_t start = (intptr_t)__ pc();
116N/A
116N/A // First thing make an ic check to see if we should even be here
116N/A
116N/A // We are free to use all registers as temps without saving them and
116N/A // restoring them except rbp. rbp, is the only callee save register
116N/A // as far as the interpreter and the compiler(s) are concerned.
116N/A
116N/A const Register ic_reg = rax;
116N/A const Register receiver = rcx;
116N/A Label hit;
116N/A Label exception_pending;
116N/A
116N/A
116N/A __ verify_oop(receiver);
116N/A __ cmpl(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes()));
116N/A __ jcc(Assembler::equal, hit);
116N/A
116N/A __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
116N/A
116N/A // verified entry must be aligned for code patching.
116N/A // and the first 5 bytes must be in the same cache line
116N/A // if we align at 8 then we will be sure 5 bytes are in the same line
116N/A __ align(8);
116N/A
116N/A __ bind(hit);
116N/A
116N/A int vep_offset = ((intptr_t)__ pc()) - start;
116N/A
116N/A
116N/A // The instruction at the verified entry point must be 5 bytes or longer
116N/A // because it can be patched on the fly by make_non_entrant. The stack bang
116N/A // instruction fits that requirement.
116N/A
116N/A // Generate stack overflow check
116N/A
116N/A
116N/A if (UseStackBanging) {
116N/A if (stack_size <= StackShadowPages*os::vm_page_size()) {
116N/A __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
116N/A } else {
116N/A __ movl(rax, stack_size);
116N/A __ bang_stack_size(rax, rbx);
116N/A }
116N/A } else {
116N/A // need a 5 byte instruction to allow MT safe patching to non-entrant
116N/A __ fat_nop();
116N/A }
116N/A
116N/A assert(((int)__ pc() - start - vep_offset) >= 5,
116N/A "valid size for make_non_entrant");
116N/A
116N/A // Generate a new frame for the wrapper.
116N/A __ enter();
116N/A
116N/A // -2 because return address is already present and so is saved rbp,
116N/A if (stack_size - 2*wordSize != 0) {
116N/A __ subl(rsp, stack_size - 2*wordSize);
116N/A }
116N/A
116N/A // Frame is now completed as far a size and linkage.
116N/A
116N/A int frame_complete = ((intptr_t)__ pc()) - start;
116N/A
116N/A // First thing we do store all the args as if we are doing the call.
116N/A // Since the C calling convention is stack based that ensures that
116N/A // all the Java register args are stored before we need to convert any
116N/A // string we might have.
116N/A
116N/A int sid = 0;
116N/A int c_arg, j_arg;
116N/A int string_reg = 0;
116N/A
116N/A for (j_arg = first_arg_to_pass, c_arg = 0 ;
116N/A j_arg < total_args_passed ; j_arg++, c_arg++ ) {
116N/A
116N/A VMRegPair src = in_regs[j_arg];
116N/A VMRegPair dst = out_regs[c_arg];
116N/A assert(dst.first()->is_stack() || in_sig_bt[j_arg] == T_VOID,
116N/A "stack based abi assumed");
116N/A
116N/A switch (in_sig_bt[j_arg]) {
116N/A
116N/A case T_ARRAY:
116N/A case T_OBJECT:
116N/A if (out_sig_bt[c_arg] == T_ADDRESS) {
116N/A // Any register based arg for a java string after the first
116N/A // will be destroyed by the call to get_utf so we store
116N/A // the original value in the location the utf string address
116N/A // will eventually be stored.
116N/A if (src.first()->is_reg()) {
116N/A if (string_reg++ != 0) {
116N/A simple_move32(masm, src, dst);
116N/A }
116N/A }
116N/A } else if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
116N/A // need to unbox a one-word value
116N/A Register in_reg = rax;
116N/A if ( src.first()->is_reg() ) {
116N/A in_reg = src.first()->as_Register();
116N/A } else {
116N/A simple_move32(masm, src, in_reg->as_VMReg());
116N/A }
116N/A Label skipUnbox;
116N/A __ movl(Address(rsp, reg2offset_out(dst.first())), NULL_WORD);
116N/A if ( out_sig_bt[c_arg] == T_LONG ) {
116N/A __ movl(Address(rsp, reg2offset_out(dst.second())), NULL_WORD);
116N/A }
116N/A __ testl(in_reg, in_reg);
116N/A __ jcc(Assembler::zero, skipUnbox);
116N/A assert(dst.first()->is_stack() &&
116N/A (!dst.second()->is_valid() || dst.second()->is_stack()),
116N/A "value(s) must go into stack slots");
165N/A
165N/A BasicType bt = out_sig_bt[c_arg];
165N/A int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
165N/A if ( bt == T_LONG ) {
116N/A __ movl(rbx, Address(in_reg,
116N/A box_offset + VMRegImpl::stack_slot_size));
116N/A __ movl(Address(rsp, reg2offset_out(dst.second())), rbx);
116N/A }
116N/A __ movl(in_reg, Address(in_reg, box_offset));
116N/A __ movl(Address(rsp, reg2offset_out(dst.first())), in_reg);
116N/A __ bind(skipUnbox);
116N/A } else {
116N/A // Convert the arg to NULL
116N/A __ movl(Address(rsp, reg2offset_out(dst.first())), NULL_WORD);
116N/A }
116N/A if (out_sig_bt[c_arg] == T_LONG) {
116N/A assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
116N/A ++c_arg; // Move over the T_VOID To keep the loop indices in sync
116N/A }
116N/A break;
116N/A
116N/A case T_VOID:
116N/A break;
116N/A
116N/A case T_FLOAT:
116N/A float_move(masm, src, dst);
116N/A break;
116N/A
116N/A case T_DOUBLE:
116N/A assert( j_arg + 1 < total_args_passed &&
116N/A in_sig_bt[j_arg + 1] == T_VOID, "bad arg list");
116N/A double_move(masm, src, dst);
116N/A break;
116N/A
116N/A case T_LONG :
116N/A long_move(masm, src, dst);
116N/A break;
116N/A
116N/A case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
116N/A
116N/A default:
116N/A simple_move32(masm, src, dst);
116N/A }
116N/A }
116N/A
116N/A // Now we must convert any string we have to utf8
116N/A //
116N/A
116N/A for (sid = 0, j_arg = first_arg_to_pass, c_arg = 0 ;
116N/A sid < total_strings ; j_arg++, c_arg++ ) {
116N/A
116N/A if (out_sig_bt[c_arg] == T_ADDRESS) {
116N/A
116N/A Address utf8_addr = Address(
116N/A rsp, string_locs[sid++] * VMRegImpl::stack_slot_size);
116N/A __ leal(rax, utf8_addr);
116N/A
116N/A // The first string we find might still be in the original java arg
116N/A // register
116N/A VMReg orig_loc = in_regs[j_arg].first();
116N/A Register string_oop;
116N/A
116N/A // This is where the argument will eventually reside
116N/A Address dest = Address(rsp, reg2offset_out(out_regs[c_arg].first()));
116N/A
116N/A if (sid == 1 && orig_loc->is_reg()) {
116N/A string_oop = orig_loc->as_Register();
116N/A assert(string_oop != rax, "smashed arg");
116N/A } else {
116N/A
116N/A if (orig_loc->is_reg()) {
116N/A // Get the copy of the jls object
116N/A __ movl(rcx, dest);
116N/A } else {
116N/A // arg is still in the original location
116N/A __ movl(rcx, Address(rbp, reg2offset_in(orig_loc)));
116N/A }
116N/A string_oop = rcx;
116N/A
116N/A }
116N/A Label nullString;
116N/A __ movl(dest, NULL_WORD);
116N/A __ testl(string_oop, string_oop);
116N/A __ jcc(Assembler::zero, nullString);
116N/A
116N/A // Now we can store the address of the utf string as the argument
116N/A __ movl(dest, rax);
116N/A
116N/A // And do the conversion
116N/A __ call_VM_leaf(CAST_FROM_FN_PTR(
116N/A address, SharedRuntime::get_utf), string_oop, rax);
116N/A __ bind(nullString);
116N/A }
116N/A
116N/A if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
116N/A assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
116N/A ++c_arg; // Move over the T_VOID To keep the loop indices in sync
116N/A }
116N/A }
116N/A
116N/A
116N/A // Ok now we are done. Need to place the nop that dtrace wants in order to
116N/A // patch in the trap
116N/A
116N/A int patch_offset = ((intptr_t)__ pc()) - start;
116N/A
116N/A __ nop();
116N/A
116N/A
116N/A // Return
116N/A
116N/A __ leave();
116N/A __ ret(0);
116N/A
116N/A __ flush();
116N/A
116N/A nmethod *nm = nmethod::new_dtrace_nmethod(
116N/A method, masm->code(), vep_offset, patch_offset, frame_complete,
116N/A stack_slots / VMRegImpl::slots_per_word);
116N/A return nm;
116N/A
116N/A}
116N/A
116N/A#endif // HAVE_DTRACE_H
116N/A
0N/A// this function returns the adjust size (in number of words) to a c2i adapter
0N/A// activation for use during deoptimization
0N/Aint Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals ) {
1426N/A return (callee_locals - callee_parameters) * Interpreter::stackElementWords;
0N/A}
0N/A
0N/A
0N/Auint SharedRuntime::out_preserve_stack_slots() {
0N/A return 0;
0N/A}
0N/A
0N/A//------------------------------generate_deopt_blob----------------------------
0N/Avoid SharedRuntime::generate_deopt_blob() {
0N/A // allocate space for the code
0N/A ResourceMark rm;
0N/A // setup code generation tools
0N/A CodeBuffer buffer("deopt_blob", 1024, 1024);
0N/A MacroAssembler* masm = new MacroAssembler(&buffer);
0N/A int frame_size_in_words;
0N/A OopMap* map = NULL;
0N/A // Account for the extra args we place on the stack
0N/A // by the time we call fetch_unroll_info
0N/A const int additional_words = 2; // deopt kind, thread
0N/A
0N/A OopMapSet *oop_maps = new OopMapSet();
0N/A
0N/A // -------------
0N/A // This code enters when returning to a de-optimized nmethod. A return
0N/A // address has been pushed on the the stack, and return values are in
0N/A // registers.
0N/A // If we are doing a normal deopt then we were called from the patched
0N/A // nmethod from the point we returned to the nmethod. So the return
0N/A // address on the stack is wrong by NativeCall::instruction_size
0N/A // We will adjust the value to it looks like we have the original return
0N/A // address on the stack (like when we eagerly deoptimized).
0N/A // In the case of an exception pending with deoptimized then we enter
0N/A // with a return address on the stack that points after the call we patched
0N/A // into the exception handler. We have the following register state:
0N/A // rax,: exception
0N/A // rbx,: exception handler
0N/A // rdx: throwing pc
0N/A // So in this case we simply jam rdx into the useless return address and
0N/A // the stack looks just like we want.
0N/A //
0N/A // At this point we need to de-opt. We save the argument return
0N/A // registers. We call the first C routine, fetch_unroll_info(). This
0N/A // routine captures the return values and returns a structure which
0N/A // describes the current frame size and the sizes of all replacement frames.
0N/A // The current frame is compiled code and may contain many inlined
0N/A // functions, each with their own JVM state. We pop the current frame, then
0N/A // push all the new frames. Then we call the C routine unpack_frames() to
0N/A // populate these frames. Finally unpack_frames() returns us the new target
0N/A // address. Notice that callee-save registers are BLOWN here; they have
0N/A // already been captured in the vframeArray at the time the return PC was
0N/A // patched.
0N/A address start = __ pc();
0N/A Label cont;
0N/A
0N/A // Prolog for non exception case!
0N/A
0N/A // Save everything in sight.
0N/A
926N/A map = RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words, false);
0N/A // Normal deoptimization
304N/A __ push(Deoptimization::Unpack_deopt);
0N/A __ jmp(cont);
0N/A
0N/A int reexecute_offset = __ pc() - start;
0N/A
0N/A // Reexecute case
0N/A // return address is the pc describes what bci to do re-execute at
0N/A
0N/A // No need to update map as each call to save_live_registers will produce identical oopmap
926N/A (void) RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words, false);
0N/A
304N/A __ push(Deoptimization::Unpack_reexecute);
0N/A __ jmp(cont);
0N/A
0N/A int exception_offset = __ pc() - start;
0N/A
0N/A // Prolog for exception case
0N/A
0N/A // all registers are dead at this entry point, except for rax, and
0N/A // rdx which contain the exception oop and exception pc
0N/A // respectively. Set them in TLS and fall thru to the
0N/A // unpack_with_exception_in_tls entry point.
0N/A
0N/A __ get_thread(rdi);
304N/A __ movptr(Address(rdi, JavaThread::exception_pc_offset()), rdx);
304N/A __ movptr(Address(rdi, JavaThread::exception_oop_offset()), rax);
0N/A
0N/A int exception_in_tls_offset = __ pc() - start;
0N/A
0N/A // new implementation because exception oop is now passed in JavaThread
0N/A
0N/A // Prolog for exception case
0N/A // All registers must be preserved because they might be used by LinearScan
0N/A // Exceptiop oop and throwing PC are passed in JavaThread
0N/A // tos: stack at point of call to method that threw the exception (i.e. only
0N/A // args are on the stack, no return address)
0N/A
0N/A // make room on stack for the return address
0N/A // It will be patched later with the throwing pc. The correct value is not
0N/A // available now because loading it from memory would destroy registers.
304N/A __ push(0);
0N/A
0N/A // Save everything in sight.
0N/A
0N/A // No need to update map as each call to save_live_registers will produce identical oopmap
926N/A (void) RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words, false);
0N/A
0N/A // Now it is safe to overwrite any register
0N/A
0N/A // store the correct deoptimization type
304N/A __ push(Deoptimization::Unpack_exception);
0N/A
0N/A // load throwing pc from JavaThread and patch it as the return address
0N/A // of the current frame. Then clear the field in JavaThread
0N/A __ get_thread(rdi);
304N/A __ movptr(rdx, Address(rdi, JavaThread::exception_pc_offset()));
304N/A __ movptr(Address(rbp, wordSize), rdx);
512N/A __ movptr(Address(rdi, JavaThread::exception_pc_offset()), NULL_WORD);
0N/A
0N/A#ifdef ASSERT
0N/A // verify that there is really an exception oop in JavaThread
304N/A __ movptr(rax, Address(rdi, JavaThread::exception_oop_offset()));
0N/A __ verify_oop(rax);
0N/A
0N/A // verify that there is no pending exception
0N/A Label no_pending_exception;
304N/A __ movptr(rax, Address(rdi, Thread::pending_exception_offset()));
304N/A __ testptr(rax, rax);
0N/A __ jcc(Assembler::zero, no_pending_exception);
0N/A __ stop("must not have pending exception here");
0N/A __ bind(no_pending_exception);
0N/A#endif
0N/A
0N/A __ bind(cont);
0N/A
0N/A // Compiled code leaves the floating point stack dirty, empty it.
0N/A __ empty_FPU_stack();
0N/A
0N/A
0N/A // Call C code. Need thread and this frame, but NOT official VM entry
0N/A // crud. We cannot block on this call, no GC can happen.
0N/A __ get_thread(rcx);
304N/A __ push(rcx);
0N/A // fetch_unroll_info needs to call last_java_frame()
0N/A __ set_last_Java_frame(rcx, noreg, noreg, NULL);
0N/A
0N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info)));
0N/A
0N/A // Need to have an oopmap that tells fetch_unroll_info where to
0N/A // find any register it might need.
0N/A
0N/A oop_maps->add_gc_map( __ pc()-start, map);
0N/A
0N/A // Discard arg to fetch_unroll_info
304N/A __ pop(rcx);
0N/A
0N/A __ get_thread(rcx);
0N/A __ reset_last_Java_frame(rcx, false, false);
0N/A
0N/A // Load UnrollBlock into EDI
304N/A __ mov(rdi, rax);
0N/A
0N/A // Move the unpack kind to a safe place in the UnrollBlock because
0N/A // we are very short of registers
0N/A
0N/A Address unpack_kind(rdi, Deoptimization::UnrollBlock::unpack_kind_offset_in_bytes());
0N/A // retrieve the deopt kind from where we left it.
304N/A __ pop(rax);
0N/A __ movl(unpack_kind, rax); // save the unpack_kind value
0N/A
0N/A Label noException;
0N/A __ cmpl(rax, Deoptimization::Unpack_exception); // Was exception pending?
0N/A __ jcc(Assembler::notEqual, noException);
304N/A __ movptr(rax, Address(rcx, JavaThread::exception_oop_offset()));
304N/A __ movptr(rdx, Address(rcx, JavaThread::exception_pc_offset()));
512N/A __ movptr(Address(rcx, JavaThread::exception_oop_offset()), NULL_WORD);
512N/A __ movptr(Address(rcx, JavaThread::exception_pc_offset()), NULL_WORD);
0N/A
0N/A __ verify_oop(rax);
0N/A
0N/A // Overwrite the result registers with the exception results.
304N/A __ movptr(Address(rsp, RegisterSaver::raxOffset()*wordSize), rax);
304N/A __ movptr(Address(rsp, RegisterSaver::rdxOffset()*wordSize), rdx);
0N/A
0N/A __ bind(noException);
0N/A
0N/A // Stack is back to only having register save data on the stack.
0N/A // Now restore the result registers. Everything else is either dead or captured
0N/A // in the vframeArray.
0N/A
0N/A RegisterSaver::restore_result_registers(masm);
0N/A
926N/A // Non standard control word may be leaked out through a safepoint blob, and we can
926N/A // deopt at a poll point with the non standard control word. However, we should make
926N/A // sure the control word is correct after restore_result_registers.
926N/A __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
926N/A
0N/A // All of the register save area has been popped of the stack. Only the
0N/A // return address remains.
0N/A
0N/A // Pop all the frames we must move/replace.
0N/A //
0N/A // Frame picture (youngest to oldest)
0N/A // 1: self-frame (no frame link)
0N/A // 2: deopting frame (no frame link)
0N/A // 3: caller of deopting frame (could be compiled/interpreted).
0N/A //
0N/A // Note: by leaving the return address of self-frame on the stack
0N/A // and using the size of frame 2 to adjust the stack
0N/A // when we are done the return to frame 3 will still be on the stack.
0N/A
0N/A // Pop deoptimized frame
304N/A __ addptr(rsp, Address(rdi,Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
0N/A
0N/A // sp should be pointing at the return address to the caller (3)
0N/A
0N/A // Stack bang to make sure there's enough room for these interpreter frames.
0N/A if (UseStackBanging) {
0N/A __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
0N/A __ bang_stack_size(rbx, rcx);
0N/A }
0N/A
0N/A // Load array of frame pcs into ECX
304N/A __ movptr(rcx,Address(rdi,Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
304N/A
304N/A __ pop(rsi); // trash the old pc
0N/A
0N/A // Load array of frame sizes into ESI
304N/A __ movptr(rsi,Address(rdi,Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
0N/A
0N/A Address counter(rdi, Deoptimization::UnrollBlock::counter_temp_offset_in_bytes());
0N/A
0N/A __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
0N/A __ movl(counter, rbx);
0N/A
0N/A // Pick up the initial fp we should save
2764N/A __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
0N/A
0N/A // Now adjust the caller's stack to make up for the extra locals
0N/A // but record the original sp so that we can save it in the skeletal interpreter
0N/A // frame and the stack walking of interpreter_sender will get the unextended sp
0N/A // value and not the "real" sp value.
0N/A
0N/A Address sp_temp(rdi, Deoptimization::UnrollBlock::sender_sp_temp_offset_in_bytes());
304N/A __ movptr(sp_temp, rsp);
304N/A __ movl2ptr(rbx, Address(rdi, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes()));
304N/A __ subptr(rsp, rbx);
0N/A
0N/A // Push interpreter frames in a loop
0N/A Label loop;
0N/A __ bind(loop);
304N/A __ movptr(rbx, Address(rsi, 0)); // Load frame size
0N/A#ifdef CC_INTERP
304N/A __ subptr(rbx, 4*wordSize); // we'll push pc and ebp by hand and
0N/A#ifdef ASSERT
304N/A __ push(0xDEADDEAD); // Make a recognizable pattern
304N/A __ push(0xDEADDEAD);
0N/A#else /* ASSERT */
304N/A __ subptr(rsp, 2*wordSize); // skip the "static long no_param"
0N/A#endif /* ASSERT */
0N/A#else /* CC_INTERP */
304N/A __ subptr(rbx, 2*wordSize); // we'll push pc and rbp, by hand
0N/A#endif /* CC_INTERP */
304N/A __ pushptr(Address(rcx, 0)); // save return address
0N/A __ enter(); // save old & set new rbp,
304N/A __ subptr(rsp, rbx); // Prolog!
304N/A __ movptr(rbx, sp_temp); // sender's sp
0N/A#ifdef CC_INTERP
304N/A __ movptr(Address(rbp,
0N/A -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
0N/A rbx); // Make it walkable
0N/A#else /* CC_INTERP */
0N/A // This value is corrected by layout_activation_impl
512N/A __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD);
304N/A __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), rbx); // Make it walkable
0N/A#endif /* CC_INTERP */
304N/A __ movptr(sp_temp, rsp); // pass to next frame
304N/A __ addptr(rsi, wordSize); // Bump array pointer (sizes)
304N/A __ addptr(rcx, wordSize); // Bump array pointer (pcs)
304N/A __ decrementl(counter); // decrement counter
0N/A __ jcc(Assembler::notZero, loop);
304N/A __ pushptr(Address(rcx, 0)); // save final return address
0N/A
0N/A // Re-push self-frame
0N/A __ enter(); // save old & set new rbp,
0N/A
0N/A // Return address and rbp, are in place
0N/A // We'll push additional args later. Just allocate a full sized
0N/A // register save area
304N/A __ subptr(rsp, (frame_size_in_words-additional_words - 2) * wordSize);
0N/A
0N/A // Restore frame locals after moving the frame
304N/A __ movptr(Address(rsp, RegisterSaver::raxOffset()*wordSize), rax);
304N/A __ movptr(Address(rsp, RegisterSaver::rdxOffset()*wordSize), rdx);
0N/A __ fstp_d(Address(rsp, RegisterSaver::fpResultOffset()*wordSize)); // Pop float stack and store in local
0N/A if( UseSSE>=2 ) __ movdbl(Address(rsp, RegisterSaver::xmm0Offset()*wordSize), xmm0);
0N/A if( UseSSE==1 ) __ movflt(Address(rsp, RegisterSaver::xmm0Offset()*wordSize), xmm0);
0N/A
0N/A // Set up the args to unpack_frame
0N/A
0N/A __ pushl(unpack_kind); // get the unpack_kind value
0N/A __ get_thread(rcx);
304N/A __ push(rcx);
0N/A
0N/A // set last_Java_sp, last_Java_fp
0N/A __ set_last_Java_frame(rcx, noreg, rbp, NULL);
0N/A
0N/A // Call C code. Need thread but NOT official VM entry
0N/A // crud. We cannot block on this call, no GC can happen. Call should
0N/A // restore return values to their stack-slots with the new SP.
0N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
0N/A // Set an oopmap for the call site
0N/A oop_maps->add_gc_map( __ pc()-start, new OopMap( frame_size_in_words, 0 ));
0N/A
0N/A // rax, contains the return result type
304N/A __ push(rax);
0N/A
0N/A __ get_thread(rcx);
0N/A __ reset_last_Java_frame(rcx, false, false);
0N/A
0N/A // Collect return values
304N/A __ movptr(rax,Address(rsp, (RegisterSaver::raxOffset() + additional_words + 1)*wordSize));
304N/A __ movptr(rdx,Address(rsp, (RegisterSaver::rdxOffset() + additional_words + 1)*wordSize));
0N/A
0N/A // Clear floating point stack before returning to interpreter
0N/A __ empty_FPU_stack();
0N/A
0N/A // Check if we should push the float or double return value.
0N/A Label results_done, yes_double_value;
0N/A __ cmpl(Address(rsp, 0), T_DOUBLE);
0N/A __ jcc (Assembler::zero, yes_double_value);
0N/A __ cmpl(Address(rsp, 0), T_FLOAT);
0N/A __ jcc (Assembler::notZero, results_done);
0N/A
0N/A // return float value as expected by interpreter
0N/A if( UseSSE>=1 ) __ movflt(xmm0, Address(rsp, (RegisterSaver::xmm0Offset() + additional_words + 1)*wordSize));
0N/A else __ fld_d(Address(rsp, (RegisterSaver::fpResultOffset() + additional_words + 1)*wordSize));
0N/A __ jmp(results_done);
0N/A
0N/A // return double value as expected by interpreter
0N/A __ bind(yes_double_value);
0N/A if( UseSSE>=2 ) __ movdbl(xmm0, Address(rsp, (RegisterSaver::xmm0Offset() + additional_words + 1)*wordSize));
0N/A else __ fld_d(Address(rsp, (RegisterSaver::fpResultOffset() + additional_words + 1)*wordSize));
0N/A
0N/A __ bind(results_done);
0N/A
0N/A // Pop self-frame.
0N/A __ leave(); // Epilog!
0N/A
0N/A // Jump to interpreter
0N/A __ ret(0);
0N/A
0N/A // -------------
0N/A // make sure all code is generated
0N/A masm->flush();
0N/A
0N/A _deopt_blob = DeoptimizationBlob::create( &buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words);
0N/A _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
0N/A}
0N/A
0N/A
0N/A#ifdef COMPILER2
0N/A//------------------------------generate_uncommon_trap_blob--------------------
0N/Avoid SharedRuntime::generate_uncommon_trap_blob() {
0N/A // allocate space for the code
0N/A ResourceMark rm;
0N/A // setup code generation tools
0N/A CodeBuffer buffer("uncommon_trap_blob", 512, 512);
0N/A MacroAssembler* masm = new MacroAssembler(&buffer);
0N/A
0N/A enum frame_layout {
0N/A arg0_off, // thread sp + 0 // Arg location for
0N/A arg1_off, // unloaded_class_index sp + 1 // calling C
0N/A // The frame sender code expects that rbp will be in the "natural" place and
0N/A // will override any oopMap setting for it. We must therefore force the layout
0N/A // so that it agrees with the frame sender code.
0N/A rbp_off, // callee saved register sp + 2
0N/A return_off, // slot for return address sp + 3
0N/A framesize
0N/A };
0N/A
0N/A address start = __ pc();
0N/A // Push self-frame.
304N/A __ subptr(rsp, return_off*wordSize); // Epilog!
0N/A
0N/A // rbp, is an implicitly saved callee saved register (i.e. the calling
0N/A // convention will save restore it in prolog/epilog) Other than that
0N/A // there are no callee save registers no that adapter frames are gone.
304N/A __ movptr(Address(rsp, rbp_off*wordSize), rbp);
0N/A
0N/A // Clear the floating point exception stack
0N/A __ empty_FPU_stack();
0N/A
0N/A // set last_Java_sp
0N/A __ get_thread(rdx);
0N/A __ set_last_Java_frame(rdx, noreg, noreg, NULL);
0N/A
0N/A // Call C code. Need thread but NOT official VM entry
0N/A // crud. We cannot block on this call, no GC can happen. Call should
0N/A // capture callee-saved registers as well as return values.
304N/A __ movptr(Address(rsp, arg0_off*wordSize), rdx);
0N/A // argument already in ECX
0N/A __ movl(Address(rsp, arg1_off*wordSize),rcx);
0N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)));
0N/A
0N/A // Set an oopmap for the call site
0N/A OopMapSet *oop_maps = new OopMapSet();
0N/A OopMap* map = new OopMap( framesize, 0 );
0N/A // No oopMap for rbp, it is known implicitly
0N/A
0N/A oop_maps->add_gc_map( __ pc()-start, map);
0N/A
0N/A __ get_thread(rcx);
0N/A
0N/A __ reset_last_Java_frame(rcx, false, false);
0N/A
0N/A // Load UnrollBlock into EDI
304N/A __ movptr(rdi, rax);
0N/A
0N/A // Pop all the frames we must move/replace.
0N/A //
0N/A // Frame picture (youngest to oldest)
0N/A // 1: self-frame (no frame link)
0N/A // 2: deopting frame (no frame link)
0N/A // 3: caller of deopting frame (could be compiled/interpreted).
0N/A
0N/A // Pop self-frame. We have no frame, and must rely only on EAX and ESP.
304N/A __ addptr(rsp,(framesize-1)*wordSize); // Epilog!
0N/A
0N/A // Pop deoptimized frame
304N/A __ movl2ptr(rcx, Address(rdi,Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
304N/A __ addptr(rsp, rcx);
0N/A
0N/A // sp should be pointing at the return address to the caller (3)
0N/A
0N/A // Stack bang to make sure there's enough room for these interpreter frames.
0N/A if (UseStackBanging) {
0N/A __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
0N/A __ bang_stack_size(rbx, rcx);
0N/A }
0N/A
0N/A
0N/A // Load array of frame pcs into ECX
0N/A __ movl(rcx,Address(rdi,Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
0N/A
304N/A __ pop(rsi); // trash the pc
0N/A
0N/A // Load array of frame sizes into ESI
304N/A __ movptr(rsi,Address(rdi,Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
0N/A
0N/A Address counter(rdi, Deoptimization::UnrollBlock::counter_temp_offset_in_bytes());
0N/A
0N/A __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
0N/A __ movl(counter, rbx);
0N/A
0N/A // Pick up the initial fp we should save
2764N/A __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
0N/A
0N/A // Now adjust the caller's stack to make up for the extra locals
0N/A // but record the original sp so that we can save it in the skeletal interpreter
0N/A // frame and the stack walking of interpreter_sender will get the unextended sp
0N/A // value and not the "real" sp value.
0N/A
0N/A Address sp_temp(rdi, Deoptimization::UnrollBlock::sender_sp_temp_offset_in_bytes());
304N/A __ movptr(sp_temp, rsp);
304N/A __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes()));
304N/A __ subptr(rsp, rbx);
0N/A
0N/A // Push interpreter frames in a loop
0N/A Label loop;
0N/A __ bind(loop);
304N/A __ movptr(rbx, Address(rsi, 0)); // Load frame size
0N/A#ifdef CC_INTERP
304N/A __ subptr(rbx, 4*wordSize); // we'll push pc and ebp by hand and
0N/A#ifdef ASSERT
304N/A __ push(0xDEADDEAD); // Make a recognizable pattern
304N/A __ push(0xDEADDEAD); // (parm to RecursiveInterpreter...)
0N/A#else /* ASSERT */
304N/A __ subptr(rsp, 2*wordSize); // skip the "static long no_param"
0N/A#endif /* ASSERT */
0N/A#else /* CC_INTERP */
304N/A __ subptr(rbx, 2*wordSize); // we'll push pc and rbp, by hand
0N/A#endif /* CC_INTERP */
304N/A __ pushptr(Address(rcx, 0)); // save return address
0N/A __ enter(); // save old & set new rbp,
304N/A __ subptr(rsp, rbx); // Prolog!
304N/A __ movptr(rbx, sp_temp); // sender's sp
0N/A#ifdef CC_INTERP
304N/A __ movptr(Address(rbp,
0N/A -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
0N/A rbx); // Make it walkable
0N/A#else /* CC_INTERP */
0N/A // This value is corrected by layout_activation_impl
512N/A __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD );
304N/A __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), rbx); // Make it walkable
0N/A#endif /* CC_INTERP */
304N/A __ movptr(sp_temp, rsp); // pass to next frame
304N/A __ addptr(rsi, wordSize); // Bump array pointer (sizes)
304N/A __ addptr(rcx, wordSize); // Bump array pointer (pcs)
304N/A __ decrementl(counter); // decrement counter
0N/A __ jcc(Assembler::notZero, loop);
304N/A __ pushptr(Address(rcx, 0)); // save final return address
0N/A
0N/A // Re-push self-frame
0N/A __ enter(); // save old & set new rbp,
304N/A __ subptr(rsp, (framesize-2) * wordSize); // Prolog!
0N/A
0N/A
0N/A // set last_Java_sp, last_Java_fp
0N/A __ get_thread(rdi);
0N/A __ set_last_Java_frame(rdi, noreg, rbp, NULL);
0N/A
0N/A // Call C code. Need thread but NOT official VM entry
0N/A // crud. We cannot block on this call, no GC can happen. Call should
0N/A // restore return values to their stack-slots with the new SP.
304N/A __ movptr(Address(rsp,arg0_off*wordSize),rdi);
0N/A __ movl(Address(rsp,arg1_off*wordSize), Deoptimization::Unpack_uncommon_trap);
0N/A __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
0N/A // Set an oopmap for the call site
0N/A oop_maps->add_gc_map( __ pc()-start, new OopMap( framesize, 0 ) );
0N/A
0N/A __ get_thread(rdi);
0N/A __ reset_last_Java_frame(rdi, true, false);
0N/A
0N/A // Pop self-frame.
0N/A __ leave(); // Epilog!
0N/A
0N/A // Jump to interpreter
0N/A __ ret(0);
0N/A
0N/A // -------------
0N/A // make sure all code is generated
0N/A masm->flush();
0N/A
0N/A _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps, framesize);
0N/A}
0N/A#endif // COMPILER2
0N/A
0N/A//------------------------------generate_handler_blob------
0N/A//
0N/A// Generate a special Compile2Runtime blob that saves all registers,
0N/A// setup oopmap, and calls safepoint code to stop the compiled code for
0N/A// a safepoint.
0N/A//
4012N/ASafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) {
0N/A
0N/A // Account for thread arg in our frame
0N/A const int additional_words = 1;
0N/A int frame_size_in_words;
0N/A
0N/A assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
0N/A
0N/A ResourceMark rm;
0N/A OopMapSet *oop_maps = new OopMapSet();
0N/A OopMap* map;
0N/A
0N/A // allocate space for the code
0N/A // setup code generation tools
0N/A CodeBuffer buffer("handler_blob", 1024, 512);
0N/A MacroAssembler* masm = new MacroAssembler(&buffer);
0N/A
0N/A const Register java_thread = rdi; // callee-saved for VC++
0N/A address start = __ pc();
0N/A address call_pc = NULL;
4012N/A bool cause_return = (poll_type == POLL_AT_RETURN);
4012N/A bool save_vectors = (poll_type == POLL_AT_VECTOR_LOOP);
0N/A // If cause_return is true we are at a poll_return and there is
0N/A // the return address on the stack to the caller on the nmethod
0N/A // that is safepoint. We can leave this return on the stack and
0N/A // effectively complete the return and safepoint in the caller.
0N/A // Otherwise we push space for a return address that the safepoint
0N/A // handler will install later to make the stack walking sensible.
4012N/A if (!cause_return)
4012N/A __ push(rbx); // Make room for return address (or push it again)
4012N/A
4012N/A map = RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words, false, save_vectors);
0N/A
0N/A // The following is basically a call_VM. However, we need the precise
0N/A // address of the call in order to generate an oopmap. Hence, we do all the
0N/A // work ourselves.
0N/A
0N/A // Push thread argument and setup last_Java_sp
0N/A __ get_thread(java_thread);
304N/A __ push(java_thread);
0N/A __ set_last_Java_frame(java_thread, noreg, noreg, NULL);
0N/A
0N/A // if this was not a poll_return then we need to correct the return address now.
4012N/A if (!cause_return) {
304N/A __ movptr(rax, Address(java_thread, JavaThread::saved_exception_pc_offset()));
304N/A __ movptr(Address(rbp, wordSize), rax);
0N/A }
0N/A
0N/A // do the call
0N/A __ call(RuntimeAddress(call_ptr));
0N/A
0N/A // Set an oopmap for the call site. This oopmap will map all
0N/A // oop-registers and debug-info registers as callee-saved. This
0N/A // will allow deoptimization at this safepoint to find all possible
0N/A // debug-info recordings, as well as let GC find all oops.
0N/A
0N/A oop_maps->add_gc_map( __ pc() - start, map);
0N/A
0N/A // Discard arg
304N/A __ pop(rcx);
0N/A
0N/A Label noException;
0N/A
0N/A // Clear last_Java_sp again
0N/A __ get_thread(java_thread);
0N/A __ reset_last_Java_frame(java_thread, false, false);
0N/A
304N/A __ cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
0N/A __ jcc(Assembler::equal, noException);
0N/A
0N/A // Exception pending
4012N/A RegisterSaver::restore_live_registers(masm, save_vectors);
0N/A
0N/A __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
0N/A
0N/A __ bind(noException);
0N/A
0N/A // Normal exit, register restoring and exit
4012N/A RegisterSaver::restore_live_registers(masm, save_vectors);
0N/A
0N/A __ ret(0);
0N/A
0N/A // make sure all code is generated
0N/A masm->flush();
0N/A
0N/A // Fill-out other meta info
0N/A return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words);
0N/A}
0N/A
0N/A//
0N/A// generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
0N/A//
0N/A// Generate a stub that calls into vm to find out the proper destination
Error!

 

There was an error!

null

java.lang.NullPointerException