Searched defs:channel (Results 1 - 25 of 111) sorted by relevance

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/illumos-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_rx_rd32.h48 * channel The channel, which is used as a multiplicand.
58 * The rest of it is pretty straighforward. In a VR, a channel is
65 * offset += ((channel << 1) + 1) << DMA_CSR_SLL;
69 * RXDMA_REG_READ32(handle, RX_DMA_CTL_STAT_REG, channel);
70 * Let's say channel is 3
84 * E00 - FFF CSRs for bound logical receive DMA channel 3.
87 * channel number by 512 bytes, and get the correct offset to
89 * is, as are all of these registers, in a table where each channel
90 * is offset 512 bytes from the previous channel (coun
114 RXDMA_REG_READ32( npi_handle_t handle, uint32_t offset, int channel) argument
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H A Dnpi_rx_rd64.h44 * #define RXDMA_REG_READ64(handle, reg, channel, data_p) { \
46 * handle.is_vraddr, channel)), (data_p))
106 * #define NXGE_RXDMA_OFFSET(x, v, channel) (x + \
107 * (!v ? DMC_OFFSET(channel) : \
108 * RDMC_PIOVADDR_OFFSET(channel)))
111 * #define DMC_OFFSET(channel) (DMA_CSR_SIZE * channel)
113 * #define TDMC_PIOVADDR_OFFSET(channel) (2 * DMA_CSR_SIZE * channel)
115 * #define RDMC_PIOVADDR_OFFSET(channel) \
222 RXDMA_REG_READ64( npi_handle_t handle, uint64_t offset, int channel, uint64_t *value) argument
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H A Dnpi_rx_wr64.h44 * #define RXDMA_REG_WRITE64(handle, reg, channel, data) { \
46 * channel)), (data)) \
85 * #define NXGE_RXDMA_OFFSET(x, v, channel) (x + \
86 * (!v ? DMC_OFFSET(channel) : \
87 * RDMC_PIOVADDR_OFFSET(channel)))
90 * #define DMC_OFFSET(channel) (DMA_CSR_SIZE * channel)
92 * #define TDMC_PIOVADDR_OFFSET(channel) (2 * DMA_CSR_SIZE * channel)
94 * #define RDMC_PIOVADDR_OFFSET(channel) \
200 RXDMA_REG_WRITE64( npi_handle_t handle, uint64_t offset, int channel, uint64_t value) argument
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H A Dnpi_tx_rd64.h48 * channel The channel, which is used as a multiplicand.
54 * #define TXDMA_REG_READ64(handle, reg, channel, val_p) \
56 * (NXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel)), val_p)
65 * The rest of it is pretty straighforward. In a VR, a channel is
72 * offset += ((channel << 1) << DMA_CSR_SLL);
76 * TXDMA_REG_READ64(handle, TX_CS_REG, channel, &value);
77 * Let's say channel is 3
90 * C00 - dFF CSRs for bound logical transmit DMA channel 3.
93 * channel numbe
122 TXDMA_REG_READ64( npi_handle_t handle, uint64_t offset, int channel, uint64_t *value) argument
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H A Dnpi_tx_wr64.h48 * channel The channel, which is used as a multiplicand.
54 * #define TXDMA_REG_WRITE64(handle, reg, channel, data) \
56 * NXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel), data)
65 * The rest of it is pretty straighforward. In a VR, a channel is
72 * offset += ((channel << 1) << DMA_CSR_SLL);
76 * TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, value);
77 * Let's say channel is 3
90 * C00 - dFF CSRs for bound logical transmit DMA channel 3.
93 * channel numbe
122 TXDMA_REG_WRITE64( npi_handle_t handle, uint64_t offset, int channel, uint64_t value) argument
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/illumos-gate/usr/src/lib/libresolv2/common/isc/
H A Dlogging_p.h45 log_channel channel; member in struct:log_channel_list
/illumos-gate/usr/src/lib/libipmi/common/
H A Dipmi_misc.c128 ipmi_get_channel_auth_caps(ipmi_handle_t *ihp, uint8_t channel, uint8_t priv) argument
134 if (channel > 0xF) {
139 msg_data[0] = channel;
170 uint8_t channel; local
177 channel = (uint8_t)number;
182 cmd.ic_data = &channel;
183 cmd.ic_dlen = sizeof (channel);
H A Dipmi_lancfg.c98 ipmi_lan_get_param(ipmi_handle_t *ihp, int channel, int param, int set, argument
104 lcmd.ilgc_number = channel;
133 ipmi_lan_get_config(ipmi_handle_t *ihp, int channel, ipmi_lan_config_t *cfgp) argument
139 if (ipmi_lan_get_param(ihp, channel, IPMI_LAN_PARAM_SET_IN_PROGRESS, 0,
150 if (ipmi_lan_get_param(ihp, channel, lep->ile_param,
160 ipmi_lan_set_param(ipmi_handle_t *ihp, int channel, int param, void *data, argument
166 lcmd.ilsc_number = channel;
201 ipmi_lan_set_config(ipmi_handle_t *ihp, int channel, ipmi_lan_config_t *cfgp, argument
212 if (ipmi_lan_set_param(ihp, channel, IPMI_LAN_PARAM_SET_IN_PROGRESS,
216 if (ipmi_lan_set_param(ihp, channel, IPMI_LAN_PARAM_SET_IN_PROGRES
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H A Dipmi_user.c106 ipmi_get_user_access(ipmi_handle_t *ihp, uint8_t channel, uint8_t uid) argument
111 req.igua_channel = channel;
122 * If sessions aren't supported on the current channel, some
187 uint8_t channel; local
192 channel = IPMI_USER_CHANNEL_CURRENT;
198 if ((resp = ipmi_get_user_access(ihp, channel, 1)) == NULL) {
202 * channel. If this fails and we are on ILOM, then attempt to
203 * use the standard channel (1) instead.
211 channel = 1;
212 if ((resp = ipmi_get_user_access(ihp, channel,
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/illumos-gate/usr/src/uts/i86pc/io/ioat/
H A Dioat_ioctl.c208 dcopy_handle_t channel; local
231 /* allocate a DMA channel */
232 e = dcopy_alloc(DCOPY_SLEEP, &channel);
257 e = dcopy_cmd_alloc(channel, flags, &cmd);
281 e = dcopy_cmd_alloc(channel, flags, &cmd);
317 dcopy_free(&channel);
337 dcopy_free(&channel);
/illumos-gate/usr/src/uts/common/io/hxge/
H A Dhxge_fzc.c176 hxge_init_fzc_rxdma_channel(p_hxge_t hxgep, uint16_t channel, argument
184 status = hxge_init_fzc_rxdma_channel_pages(hxgep, channel, rbr_p);
195 uint16_t channel, p_rx_rbr_ring_t rbrp)
206 rs = hpi_rxdma_cfg_logical_page_handle(handle, channel,
218 hxge_init_fzc_txdma_channel(p_hxge_t hxgep, uint16_t channel, argument
226 (void) hxge_init_fzc_txdma_channel_pages(hxgep, channel, tx_ring_p);
262 hxge_init_fzc_txdma_channel_pages(p_hxge_t hxgep, uint16_t channel, argument
274 rs = hpi_txdma_log_page_handle_set(handle, channel,
194 hxge_init_fzc_rxdma_channel_pages(p_hxge_t hxgep, uint16_t channel, p_rx_rbr_ring_t rbrp) argument
H A Dhpi_rxdma.c230 * Configure The RDC channel Rcv Buffer Ring
523 hpi_rxdma_channel_rbr_empty_clear(hpi_handle_t handle, uint8_t channel) argument
527 if (!RXDMA_CHANNEL_VALID(channel)) {
529 " hpi_rxdma_channel_rbr_empty_clear", " channel", channel));
530 return (HPI_FAILURE | HPI_RXDMA_CHANNEL_INVALID(channel));
533 RXDMA_REG_READ64(handle, RDC_STAT, channel, &cs.value);
535 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value);
544 hpi_rxdma_control_status(hpi_handle_t handle, io_op_t op_mode, uint8_t channel, argument
550 if (!RXDMA_CHANNEL_VALID(channel)) {
585 hpi_rxdma_event_mask(hpi_handle_t handle, io_op_t op_mode, uint8_t channel, rdc_int_mask_t *mask_p) argument
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H A Dhpi_txdma.c35 uint8_t channel);
38 hpi_txdma_log_page_handle_set(hpi_handle_t handle, uint8_t channel, argument
43 if (!TXDMA_CHANNEL_VALID(channel)) {
46 " Invalid Input: channel <0x%x>", channel));
47 return (HPI_FAILURE | HPI_TXDMA_CHANNEL_INVALID(channel));
50 TXDMA_REG_WRITE64(handle, TDC_PAGE_HANDLE, channel, hdl_p->value);
56 hpi_txdma_channel_reset(hpi_handle_t handle, uint8_t channel) argument
59 " hpi_txdma_channel_reset" " RESETTING", channel));
60 return (hpi_txdma_channel_control(handle, TXDMA_RESET, channel));
64 hpi_txdma_channel_init_enable(hpi_handle_t handle, uint8_t channel) argument
70 hpi_txdma_channel_enable(hpi_handle_t handle, uint8_t channel) argument
76 hpi_txdma_channel_disable(hpi_handle_t handle, uint8_t channel) argument
82 hpi_txdma_channel_mbox_enable(hpi_handle_t handle, uint8_t channel) argument
88 hpi_txdma_channel_control(hpi_handle_t handle, txdma_cs_cntl_t control, uint8_t channel) argument
167 hpi_txdma_control_status(hpi_handle_t handle, io_op_t op_mode, uint8_t channel, tdc_stat_t *cs_p) argument
205 hpi_txdma_event_mask(hpi_handle_t handle, io_op_t op_mode, uint8_t channel, tdc_int_mask_t *mask_p) argument
243 hpi_txdma_ring_config(hpi_handle_t handle, io_op_t op_mode, uint8_t channel, uint64_t *reg_data) argument
274 hpi_txdma_mbox_config(hpi_handle_t handle, io_op_t op_mode, uint8_t channel, uint64_t *mbox_addr) argument
383 hpi_txdma_ring_head_get(hpi_handle_t handle, uint8_t channel, tdc_tdr_head_t *hdl_p) argument
437 hpi_txdma_control_reset_wait(hpi_handle_t handle, uint8_t channel) argument
466 hpi_txdma_control_stop_wait(hpi_handle_t handle, uint8_t channel) argument
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/illumos-gate/usr/src/uts/common/io/xge/hal/xgehal/
H A Dxgehal-channel-fp.c25 #include "xgehal-channel.h"
32 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
36 if (channel->terminating) {
40 if (channel->reserve_length - channel->reserve_top >
41 channel->reserve_threshold) {
44 *dtrh = channel->reserve_arr[--channel->reserve_length];
47 "channel %d:%d:%d, reserve_idx %d",
49 channel
114 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
140 xge_hal_channel_t *channel = (xge_hal_channel_t*)channelh; local
154 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
165 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
179 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
200 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
220 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
236 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
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H A Dxgehal-channel.c24 #include "xgehal-channel.h"
39 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
41 if (channel->reserve_top >= channel->reserve_length) {
45 *dtrh = channel->reserve_arr[channel->reserve_top++];
58 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
60 if (channel->reserve_initial == channel->free_length) {
64 *dtrh = channel
100 xge_hal_channel_t *channel; local
139 __hal_channel_free(xge_hal_channel_t *channel) argument
171 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
226 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
303 xge_hal_channel_t *channel = NULL; local
429 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
522 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
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H A Dxgehal-stats.c847 * xge_hal_stats_channel - Get channel statistics.
849 * @channel_info: HAL channel statistic counters.
852 * Retrieve statistics of a particular HAL channel. This includes, for instance,
866 xge_hal_channel_t *channel; local
869 channel = (xge_hal_channel_t *)channelh;
870 if ((channel == NULL) || (channel->magic != XGE_HAL_MAGIC)) {
873 hldev = (xge_hal_device_t *)channel->devh;
880 !channel->is_open) {
892 if (channel
976 xge_hal_channel_t *channel; local
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H A Dxgehal-fifo.c88 if (fifo->channel.dtr_init) {
89 fifo->channel.dtr_init(fifo, (xge_hal_dtr_h)txdp, index,
90 fifo->channel.userdata, XGE_HAL_CHANNEL_OC_NORMAL);
125 xge_os_dma_unmap(fifo->channel.pdev,
135 xge_os_dma_free(fifo->channel.pdev,
159 hldev = (xge_hal_device_t *)fifo->channel.devh;
164 xge_os_spin_lock_init(&fifo->channel.reserve_lock, hldev->pdev);
166 xge_os_spin_lock_init_irq(&fifo->channel.reserve_lock, hldev->irqh);
172 xge_os_spin_lock_init(&fifo->channel.post_lock, hldev->pdev);
173 fifo->post_lock_ptr = &fifo->channel
461 xge_hal_channel_t *channel = NULL; local
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H A Dxgehal-mgmtaux.c882 xge_hal_channel_t *channel; local
950 /* for each opened rx channel */
952 channel = xge_container_of(item, xge_hal_channel_t, item);
953 status = xge_hal_mgmt_channel_stats(channel, &chstat,
959 (void) xge_os_snprintf(key, sizeof(key), "ring%d_", channel->post_qid);
971 __HAL_AUX_ENTRY(key, channel->usage_cnt, "%u");
988 /* for each opened tx channel */
990 channel = xge_container_of(item, xge_hal_channel_t, item);
992 status = xge_hal_mgmt_channel_stats(channel, &chstat,
998 (void) xge_os_snprintf(key, sizeof(key), "fifo%d_", channel
1263 xge_hal_channel_t *channel; local
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/illumos-gate/usr/src/cmd/hal/hald/solaris/
H A Dosspec.c42 static gboolean mnttab_event (GIOChannel *channel, GIOCondition cond, gpointer user_data);
204 mnttab_event (GIOChannel *channel, GIOCondition cond, gpointer user_data) argument
/illumos-gate/usr/src/uts/common/io/nxge/
H A Dnxge_txc.c129 * channel The channel to bind.
149 int channel)
160 "==> nxge_txc_tdc_bind(port %d, channel %d)", port, channel));
172 /* Bind <channel> to <port>. */
177 if (bitmap & (1 << channel)) {
179 "nxge_txc_tdc_bind: channel %d already bound on port %d",
180 channel, port));
182 /* Bind the new channel
147 nxge_txc_tdc_bind( p_nxge_t nxgep, int channel) argument
249 nxge_txc_tdc_unbind( p_nxge_t nxgep, int channel) argument
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H A Dnxge_hio_guest.c286 * they are NOT real channel numbers.
297 * For each channel, mark these two fields
309 dc->channel = (nxge_channel_t)i;
319 * they are NOT real channel numbers.
330 * For each channel, mark these two fields
342 dc->channel = (nxge_channel_t)i;
388 * virtual channel numbers. So the <nhd>'s rdc & tdc
414 nxge_hio_get_dc_htable_idx(nxge_t *nxge, vpc_type_t type, uint32_t channel) argument
420 dc = nxge_grp_dc_find(nxge, type, channel);
592 * channel Th
600 nxge_tdc_lp_conf( p_nxge_t nxge, int channel) argument
719 nxge_rdc_lp_conf( p_nxge_t nxge, int channel) argument
925 uint32_t channel; local
980 uint32_t channel; local
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H A Dnxge_intr.c55 * Add <channel>'s interrupt.
60 * channel The channel whose interrupt we want to add.
73 int channel)
87 if ((vector = nxge_intr_vec_find(nxge, type, channel)) == -1) {
89 "nxge_intr_add(%cDC %d): vector not found", c, channel));
111 c, channel, vector, nxge_ddi_perror(status2)));
122 c, channel, vector, nxge_ddi_perror(status2)));
145 * Remove <channel>'s interrupt.
150 * channel Th
70 nxge_intr_add( nxge_t *nxge, vpc_type_t type, int channel) argument
160 nxge_intr_remove( nxge_t *nxge, vpc_type_t type, int channel) argument
245 nxge_intr_vec_find( nxge_t *nxge, vpc_type_t type, int channel) argument
316 nxge_hio_intr_add( nxge_t *nxge, vpc_type_t type, int channel) argument
417 nxge_hio_intr_remove( nxge_t *nxge, vpc_type_t type, int channel) argument
701 int channel; local
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/illumos-gate/usr/src/uts/intel/io/intel_nhm/
H A Ddimm_topo.c74 (void) snprintf(buf, sizeof (buf), "dimm-channel-interleave-%d",
78 "dimm-channel-interleave-way-%d", num);
93 uint8_t channel, uint32_t dimm, uint64_t rank_size)
111 pa = dimm_to_addr(node, channel, dimm * 4 + i,
133 inhm_dimm(nhm_dimm_t *nhm_dimm, uint32_t node, uint8_t channel, uint32_t dimm) argument
157 inhm_rank(newdimm, nhm_dimm, node, channel, dimm,
212 (void) nvlist_add_string(newchannel[i], "channel-mode",
92 inhm_rank(nvlist_t *newdimm, nhm_dimm_t *nhm_dimm, uint32_t node, uint8_t channel, uint32_t dimm, uint64_t rank_size) argument
/illumos-gate/usr/src/lib/fm/topo/modules/i86pc/chip/
H A Dchip_intel.c289 int channel, nvlist_t *auth, nvlist_t *nvl, int maxdimms, int maxranks)
299 if (mkrsrc(mod, pnode, DRAMCHANNEL, channel, auth, &fmri) != 0) {
303 if ((mc_channel = topo_node_bind(mod, pnode, DRAMCHANNEL, channel,
340 int channel; local
354 "mc_nb_create: failed to find channel information\n");
382 channel = 0;
403 if (topo_node_range_create(mod, mcnode, DRAMCHANNEL, channel,
404 channel + nchannels - 1) < 0) {
406 "mc_nb_create: channel node range create failed\n");
410 if (mc_add_channel(mod, chip_smbid, mcnode, channel,
288 mc_add_channel(topo_mod_t *mod, uint16_t chip_smbid, tnode_t *pnode, int channel, nvlist_t *auth, nvlist_t *nvl, int maxdimms, int maxranks) argument
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/illumos-gate/usr/src/lib/gss_mechs/mech_dh/backend/mech/
H A Dcontext_establish.c115 * Compare if two channel bindings are the same. If the local binding is
150 * Generate an accept token for a context and channel binding puting the
157 gss_channel_bindings_t channel, /* channel bindings */
179 /* Our channel bindings */
180 accept->channel = GSS2DH_channel_binding(&dh_binding, channel);
365 /* Local channel bindings */
366 gss_channel_bindings_t channel,
465 /* Check that the channel binding
156 gen_accept_token(dh_gss_context_t ctx, gss_channel_bindings_t channel, gss_buffer_t output ) argument
360 __dh_gss_accept_sec_context(void *ctx, OM_uint32 *minor, gss_ctx_id_t *gss_ctx, gss_cred_id_t cred, gss_buffer_t input, gss_channel_bindings_t channel, gss_name_t *principal, gss_OID* mech, gss_buffer_t output, OM_uint32 *flags, OM_uint32 *expire, gss_cred_id_t *del_cred ) argument
588 gen_init_token(dh_gss_context_t cntx, dh_context_t dhctx, gss_channel_bindings_t channel, gss_buffer_t result ) argument
663 create_context(OM_uint32 *minor, dh_context_t cntx, dh_gss_context_t *gss_ctx, dh_principal netname, dh_principal target, gss_channel_bindings_t channel, OM_uint32 flags_req, OM_uint32 time_req, OM_uint32 *flags_rec, OM_uint32 *time_rec, gss_buffer_t results ) argument
801 continue_context(OM_uint32 *minor, gss_buffer_t token, dh_gss_context_t dh_gss_ctx, gss_channel_bindings_t channel) argument
889 __dh_gss_init_sec_context(void *ctx, OM_uint32 *minor, gss_cred_id_t cred, gss_ctx_id_t *context, gss_name_t target, gss_OID mech, OM_uint32 req_flags, OM_uint32 time_req, gss_channel_bindings_t channel, gss_buffer_t input_token, gss_OID *mech_rec, gss_buffer_t output_token, OM_uint32 *flags_rec, OM_uint32 *time_rec ) argument
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