/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*
* Copyright (c) 2002-2006 Neterion, Inc.
*/
#include "xgehal-fifo.h"
#include "xgehal-device.h"
static xge_hal_status_e
void *memblock,
int memblock_index,
void *item,
int index,
int is_last,
void *userdata)
{
int memblock_item_idx;
txdl_priv = (xge_hal_fifo_txdl_priv_t *) \
item,
/* pre-format HAL's TxDL's private */
txdl_priv->dang_frags = 0;
txdl_priv->alloc_frags = 0;
#ifdef XGE_DEBUG_ASSERT
#endif
#ifdef XGE_HAL_ALIGN_XMIT
#ifndef XGE_HAL_ALIGN_XMIT_ALLOC_RT
{
if (status != XGE_HAL_OK) {
"align buffer[%d] %d bytes, status %d",
status);
return status;
}
}
}
#endif
#endif
}
return XGE_HAL_OK;
}
static xge_hal_status_e
void *memblock,
int memblock_index,
void *item,
int index,
int is_last,
void *userdata)
{
int memblock_item_idx;
#ifdef XGE_HAL_ALIGN_XMIT
#endif
txdl_priv = (xge_hal_fifo_txdl_priv_t *) \
item,
#ifdef XGE_HAL_ALIGN_XMIT
if (txdl_priv->align_dma_addr != 0) {
txdl_priv->align_dma_addr = 0;
}
}
}
#endif
return XGE_HAL_OK;
}
{
#if defined(XGE_HAL_TX_MULTI_RESERVE)
#elif defined(XGE_HAL_TX_MULTI_RESERVE_IRQ)
#endif
#if defined(XGE_HAL_TX_MULTI_POST)
} else {
}
#elif defined(XGE_HAL_TX_MULTI_POST_IRQ)
} else {
}
#endif
fifo->align_size =
/* Initializing the BAR1 address as the start of
* the FIFO queue pointer and as a location of FIFO control
* word. */
/* apply "interrupts per txdl" attribute */
}
/*
* FIFO memory management strategy:
*
* TxDL splitted into three independent parts:
* - set of TxD's
* - TxD HAL private part
* - upper layer private part
*
* Adaptative memory allocation used. i.e. Memory allocated on
* demand with the size which will fit into one memory block.
* One memory block may contain more than one TxDL. In simple case
* memory block size can be equal to CPU page size. On more
* sophisticated OS's memory block can be contigious across
* several pages.
*
* During "reserve" operations more memory can be allocated on demand
* for example due to FIFO full condition.
*
* Pool of memory memblocks never shrinks except __hal_fifo_close
* routine which will essentially stop channel and free the resources.
*/
/* TxDL common private size == TxDL private + ULD private */
/* recompute txdl size to be cacheline aligned */
/* since dtr_init() callback will be called from item_alloc(),
* the same way channels userdata might be used prior to
* channel_initialize() */
fifo);
return XGE_HAL_ERR_OUT_OF_MEMORY;
}
if (status != XGE_HAL_OK) {
return status;
}
"DTR reserve_length:%d reserve_top:%d\n"
"max_frags:%d reserve_threshold:%d\n"
"memblock_size:%d alignment_size:%d max_aligned_frags:%d",
#ifdef XGE_DEBUG_ASSERT
}
#endif
/* reverse the FIFO dtr array */
for (i = 0; i < mid_point; i++) {
}
#ifdef XGE_DEBUG_ASSERT
}
#endif
return XGE_HAL_OK;
}
void
{
}
#if defined(XGE_HAL_TX_MULTI_RESERVE)
#elif defined(XGE_HAL_TX_MULTI_RESERVE_IRQ)
#endif
#if defined(XGE_HAL_TX_MULTI_POST)
#elif defined(XGE_HAL_TX_MULTI_POST_IRQ)
#endif
}
}
void
{
int i;
/* Tx DMA Initialization */
/* Note: WRR calendar must be configured before the transmit
* FIFOs are enabled! page 6-77 user guide */
/* all zeroes for Round-Robin */
for (i = 0; i < XGE_HAL_FIFO_MAX_WRR; i++) {
tx_fifo_wrr[i]);
}
/* reset all of them but '0' */
for (i=1; i < XGE_HAL_FIFO_MAX_PARTITION; i++) {
tx_fifo_partitions[i]);
}
} else { /* Change the default settings */
for (i = 0; i < XGE_HAL_FIFO_MAX_WRR; i++) {
tx_fifo_wrr_value[i], tx_fifo_wrr[i]);
}
}
/* configure only configured FIFOs */
for (i = 0; i < XGE_HAL_MAX_FIFO_NUM; i++) {
val64 |=
}
/* NOTE: do write operation for each second u64 half
* or force for first one if configured number
* is even */
if (reg_half) {
if (reg_num == 0) {
/* skip partition '0', must write it once at
* the end */
} else {
"fifo partition_%d at: "
(unsigned long long)val64);
}
val64 = 0;
}
}
tx_fifo_partitions[0]);
xge_os_wmb();
tx_fifo_partitions[0]);
(unsigned long long)(ulong_t)
(unsigned long long) part0);
/*
* Initialization of Tx_PA_CONFIG register to ignore packet
* integrity checking.
*/
return;
/*
* Assign MSI-X vectors
*/
for (i = 0; i < XGE_HAL_MAX_FIFO_NUM; i++) {
continue;
/* find channel */
item);
break;
}
}
if (channel) {
(void) xge_hal_channel_msix_set(channel,
}
}
}
#ifdef XGE_HAL_ALIGN_XMIT
void
{
if (txdl_priv->align_dma_addr != 0) {
txdl_priv->align_dma_addr = 0;
}
}
}
{
/* allocate alignment DMA-buffer */
return XGE_HAL_ERR_OUT_OF_MEMORY;
}
/* map it */
return XGE_HAL_ERR_OUT_OF_MAPPING;
}
return XGE_HAL_OK;
}
#endif