3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * CDDL HEADER START
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * The contents of this file are subject to the terms of the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Common Development and Distribution License (the "License").
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * You may not use this file except in compliance with the License.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * See the License for the specific language governing permissions
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * and limitations under the License.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * When distributing Covered Code, include this CDDL HEADER in each
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * If applicable, add the following below this CDDL HEADER, with the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * fields enclosed by brackets "[]" replaced with your own identifying
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * information: Portions Copyright [yyyy] [name of copyright owner]
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * CDDL HEADER END
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Use is subject to license terms.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#pragma ident "%Z%%M% %I% %E% SMI"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * System interrupt registers that are under function zero management.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_fzc_intr_init"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Configure the initial timer resolution */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if ((status = hxge_fzc_intr_tmres_set(hxgep)) != HXGE_OK) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Set up the logical device group's logical devices that
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * the group owns.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if ((status = hxge_fzc_intr_ldg_num_set(hxgep)) != HXGE_OK) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Configure the system interrupt data */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if ((status = hxge_fzc_intr_sid_set(hxgep)) != HXGE_OK) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_fzc_intr_init"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_fzc_intr_ldg_num_set"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_fzc_intr_ldg_num_set "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_fzc_intr_ldg_num_set failed "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " rs 0x%x ldv %d ldg %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_fzc_intr_ldg_num_set OK ldv %d ldg %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_fzc_intr_ldg_num_set"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_fzc_intr_tmrese_set"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if ((rs = hpi_fzc_ldg_timer_res_set(handle, hxgep->ldgvp->tmres))) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_fzc_intr_tmrese_set"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_fzc_intr_sid_set"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_fzc_intr_sid_set: no ldg"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_fzc_intr_sid_set: #int %d", hxgep->ldgvp->ldg_intrs));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_fzc_intr_sid_set(%d): group %d vector %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_fzc_intr_sid_set"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Receive DMA registers that are under function zero management.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_init_fzc_rxdma_channel(p_hxge_t hxgep, uint16_t channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_init_fzc_rxdma_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Initialize the RXDMA logical pages */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs status = hxge_init_fzc_rxdma_channel_pages(hxgep, channel, rbr_p);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_init_fzc_rxdma_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_init_fzc_rxdma_channel_pages"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Initialize the page handle */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_init_fzc_rxdma_channel_pages"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_init_fzc_txdma_channel(p_hxge_t hxgep, uint16_t channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_init_fzc_txdma_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Initialize the TXDMA logical pages */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (void) hxge_init_fzc_txdma_channel_pages(hxgep, channel, tx_ring_p);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_init_fzc_txdma_channel"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_init_fzc_rx_common"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Configure the rxdma clock divider
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * This is the granularity counter based on
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * the hardware system clock (i.e. 300 Mhz) and
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * it is running around 3 nanoseconds.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * So, set the clock divider counter to 1000 to get
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * microsecond granularity.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * For example, for a 3 microsecond timeout, the timeout
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * will be set to 1.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs rs = hpi_rxdma_cfg_clock_div_set(handle, RXDMA_CK_DIV_DEFAULT);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_init_fzc_txdma_channel_pages(p_hxge_t hxgep, uint16_t channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_init_fzc_txdma_channel_pages"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Initialize the page handle */