3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * CDDL HEADER START
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * The contents of this file are subject to the terms of the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Common Development and Distribution License (the "License").
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * You may not use this file except in compliance with the License.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * See the License for the specific language governing permissions
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * and limitations under the License.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * When distributing Covered Code, include this CDDL HEADER in each
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * If applicable, add the following below this CDDL HEADER, with the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * fields enclosed by brackets "[]" replaced with your own identifying
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * information: Portions Copyright [yyyy] [name of copyright owner]
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * CDDL HEADER END
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Use is subject to license terms.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshpi_rxdma_cfg_logical_page_handle(hpi_handle_t handle, uint8_t rdc,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "rxdma_cfg_logical_page_handle"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs RXDMA_REG_WRITE64(handle, RDC_PAGE_HANDLE, rdc, page_hdl.value);
069fd767a977699f506b76b0432a2c61709b90ecMichael Speerhpi_rxdma_cfg_rdc_wait_for_qst(hpi_handle_t handle, uint8_t rdc)
069fd767a977699f506b76b0432a2c61709b90ecMichael Speer RXDMA_REG_READ64(handle, RDC_RX_CFG1, rdc, &cfg.value);
069fd767a977699f506b76b0432a2c61709b90ecMichael Speer RXDMA_REG_READ64(handle, RDC_RX_CFG1, rdc, &cfg.value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/* RX DMA functions */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshpi_rxdma_cfg_rdc_ctl(hpi_handle_t handle, uint8_t rdc, uint8_t op)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint32_t error = HPI_RXDMA_ERROR_ENCODE(HPI_RXDMA_RESET_ERR, rdc);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs switch (op) {
069fd767a977699f506b76b0432a2c61709b90ecMichael Speer RXDMA_REG_READ64(handle, RDC_RX_CFG1, rdc, &cfg.value);
069fd767a977699f506b76b0432a2c61709b90ecMichael Speer RXDMA_REG_READ64(handle, RDC_RX_CFG1, rdc, &cfg.value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hpi_rxdma_cfg_rdc_ctl"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " RXDMA_OP_DISABLE Failed for RDC %d \n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (count == 0) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hpi_rxdma_cfg_rdc_ctl"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshpi_rxdma_cfg_rdc_enable(hpi_handle_t handle, uint8_t rdc)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (hpi_rxdma_cfg_rdc_ctl(handle, rdc, RXDMA_OP_ENABLE));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshpi_rxdma_cfg_rdc_disable(hpi_handle_t handle, uint8_t rdc)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (hpi_rxdma_cfg_rdc_ctl(handle, rdc, RXDMA_OP_DISABLE));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (hpi_rxdma_cfg_rdc_ctl(handle, rdc, RXDMA_OP_RESET));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshpi_rxdma_cfg_rdc_rcr_ctl(hpi_handle_t handle, uint8_t rdc,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs RXDMA_REG_READ64(handle, RDC_RCR_CFG_B, rdc, &rcr_cfgb.value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs switch (op) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs RXDMA_REG_WRITE64(handle, RDC_RCR_CFG_B, rdc, rcr_cfgb.value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshpi_rxdma_cfg_rdc_rcr_threshold(hpi_handle_t handle, uint8_t rdc,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshpi_rxdma_cfg_rdc_rcr_timeout(hpi_handle_t handle, uint8_t rdc,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Configure The RDC channel Rcv Buffer Ring
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs cfg1.bits.mbaddr_h = (rdc_desc_cfg->mbox_addr >> 32) & 0xfff;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs RXDMA_CFIG2_MBADDR_L_MASK) >> RXDMA_CFIG2_MBADDR_L_SHIFT);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Only after all the configurations are set, then
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * enable the RDC or else configuration fatal error
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * will be returned (especially if the Hypervisor
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * set up the logical pages with non-zero values.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * This HPI function only sets up the configuration.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Call the enable function to enable the RDMC!
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* rbr config */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (RBR_CFIG_A_STDADDR_MASK | RBR_CFIG_A_STDADDR_BASE_MASK));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* The remaining 20 bits in the DMA address form the handle */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs page_handle.bits.handle = (rdc_desc_cfg->rbr_addr >> 44) && 0xfffff;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * The RBR ring size must be multiple of 64.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hpi_rxdma_cfg_rdc_ring Illegal RBR Queue Length %d \n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (HPI_RXDMA_ERROR_ENCODE(HPI_RXDMA_RBRSZIE_INVALID, rdc));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * The lower 6 bits are hardcoded to 0 and the higher 10 bits are
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * stored in len.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hpi_rxdma_cfg_rdc_ring CFGA 0x%llx len %d (RBR LEN %d)\n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * bksize is 1 bit
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Buffer Block Size. b0 - 4K; b1 - 8K.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "rxdma_cfg_rdc_ring blksize: Illegal buffer size %d \n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Size 0 of packet buffer. b00 - 256; b01 - 512; b10 - 1K; b11 - resvd.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " rxdma_cfg_rdc_ring"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " blksize0: Illegal buffer size %x \n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Size 1 of packet buffer. b0 - 1K; b1 - 2K.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " rxdma_cfg_rdc_ring"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " blksize1: Illegal buffer size %x \n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Size 2 of packet buffer. b0 - 2K; b1 - 4K.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " rxdma_cfg_rdc_ring"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " blksize2: Illegal buffer size %x \n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * The rcr len must be multiple of 32.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " rxdma_cfg_rdc_ring Illegal RCR Queue Length %d \n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (HPI_RXDMA_ERROR_ENCODE(HPI_RXDMA_RCRSZIE_INVALID, rdc));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Bits 15:5 of the maximum number of 8B entries in RCR. Bits 4:0 are
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * hard-coded to zero. The maximum size is 2^16 - 32.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* check if the rcr timeout value is valid */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " rxdma_cfg_rdc_ring"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " Illegal RCR Timeout value %d \n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* check if the rcr threshold value is valid */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (RXDMA_RCR_THRESH_VALID(rdc_desc_cfg->rcr_threshold)) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " rxdma_cfg_rdc_ring Illegal RCR Threshold value %d \n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* now do the actual HW configuration */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs RXDMA_REG_WRITE64(handle, RDC_RBR_CFG_A, rdc, cfga.value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs RXDMA_REG_WRITE64(handle, RDC_RBR_CFG_B, rdc, cfgb.value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs RXDMA_REG_WRITE64(handle, RDC_RCR_CFG_A, rdc, rcr_cfga.value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs RXDMA_REG_WRITE64(handle, RDC_RCR_CFG_B, rdc, rcr_cfgb.value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs RXDMA_REG_WRITE64(handle, RDC_PAGE_HANDLE, rdc, page_handle.value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs rdc_pref_par_log_t *pre_log, rdc_pref_par_log_t *sha_log)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Hydra doesn't have details about these errors.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * It only provides the addresses of the errors.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_REG_RD64(handle, RDC_PREF_PAR_LOG, &pre_log->value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_REG_RD64(handle, RDC_SHADOW_PAR_LOG, &sha_log->value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/* system wide conf functions */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshpi_rxdma_cfg_clock_div_set(hpi_handle_t handle, uint16_t count)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hpi_rxdma_cfg_clock_div_set: add 0x%llx "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "handle 0x%llx value 0x%llx",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshpi_rxdma_rdc_rbr_stat_get(hpi_handle_t handle, uint8_t rdc,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " rxdma_rdc_rbr_stat_get Illegal RDC Number %d \n", rdc));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs RXDMA_REG_READ64(handle, RDC_RBR_QLEN, rdc, &rbr_stat->value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshpi_rxdma_rdc_rcr_qlen_get(hpi_handle_t handle, uint8_t rdc,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " rxdma_rdc_rcr_qlen_get Illegal RDC Number %d \n", rdc));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs RXDMA_REG_READ64(handle, RDC_RCR_QLEN, rdc, &stats.value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " rxdma_rdc_rcr_qlen_get RDC %d qlen %x qlen %x\n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshpi_rxdma_channel_rbr_empty_clear(hpi_handle_t handle, uint8_t channel)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hpi_rxdma_channel_rbr_empty_clear", " channel", channel));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (HPI_FAILURE | HPI_RXDMA_CHANNEL_INVALID(channel));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * This function is called to operate on the control and status register.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshpi_rxdma_control_status(hpi_handle_t handle, io_op_t op_mode, uint8_t channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (HPI_FAILURE | HPI_RXDMA_CHANNEL_INVALID(channel));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs RXDMA_REG_READ64(handle, RDC_STAT, channel, &cs_p->value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs_p->value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (HPI_FAILURE | HPI_RXDMA_OPCODE_INVALID(channel));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * This function is called to operate on the event mask
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * register which is used for generating interrupts.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshpi_rxdma_event_mask(hpi_handle_t handle, io_op_t op_mode, uint8_t channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (HPI_FAILURE | HPI_RXDMA_CHANNEL_INVALID(channel));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs RXDMA_REG_READ64(handle, RDC_INT_MASK, channel, &mask_p->value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs RXDMA_REG_WRITE64(handle, RDC_INT_MASK, channel, mask_p->value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs RXDMA_REG_READ64(handle, RDC_INT_MASK, channel, &mask.value);