Searched refs:_MASKED_BIT_ENABLE (Results 1 - 6 of 6) sorted by relevance

/solaris-x11-s11/open-src/kernel/i915/src/
H A Dintel_pm.c3561 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3997 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4065 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4070 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4135 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
4223 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4252 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4262 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4265 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4278 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABL
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H A Dintel_ringbuffer.c554 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
563 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
568 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
573 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
599 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
977 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1644 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
H A Di915_gem_gtt.c256 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
277 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
H A Di915_gem.c3487 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3489 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3766 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
H A Di915_irq.c2238 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
H A Di915_reg.h43 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) macro

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