/*
*/
/*
* Copyright (c) 2012, 2013, Intel Corporation. All rights reserved.
*/
/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _I915_REG_H_
#define _I915_REG_H_
/* Note: PGETBL_CTL2 has a different offset on G33. */
/*
* The Bridge device's PCI config space has information about the
* fb aperture size and the amount of pre-reserved memory.
* This is all handled in the intel-gtt.ko module. i915.ko only
* cares about the vga bit for the vga rbiter.
*/
#define INTEL_GMCH_MEM_128M 0
/* PCI config space */
#define GC_CLOCK_133_200 (0 << 0)
#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
/* Graphics reset regs */
/* VGA stuff */
/* GR05 */
/* GR06 */
#define VGA_GR_MEM_A0000_AFFFF 0
/*
* Memory interface instructions used by the kernel
*/
/* IVB has funny definitions for which plane to flip. */
#define MI_ARB_DISABLE (0<<0)
/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
* - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
* simply ignores the register load under certain conditions.
* - One can actually load arbitrary many arbitrary registers: Simply issue x
*/
/*
* 3D instructions used by the kernel
*/
/*
* Reset registers
*/
/*
* IOSF sideband
*/
/*
* DPIO - a special bus for various display related registers to hide behind
*
* DPIO is VLV only.
*
* Note: digital port B is DDI0, digital pot C is DDI1
*/
#define DPIO_DEVFN 0
#define DPIO_OPCODE_REG_READ 0
/*
*/
#define DPIO_POST_DIV_DAC 0
/*
* Per DDI channel DPIO regs
*/
/*
* Fence registers
*/
/* control register for cpu gtt access */
/*
* Instruction and interrupt control regs
*/
#define GEN6_NOSYNC 0
#if 0
#define PRB0_TAIL 0x02030
#define PRB0_HEAD 0x02034
#define PRB0_START 0x02038
#define PRB0_CTL 0x0203c
#endif
/* GM45+ chicken bits -- debug workaround bits that may be required
* for various sorts of correct behavior. The top 16 bits of each are
* the enables for writing to the corresponding low bit.
*/
/* Disables pipelining of read flushes past the SF-WIZ interface.
* Required on all Ironlake steppings according to the B-Spec, but the
* particular danger of not doing so is not specified.
*/
will not assert AGPBUSY# and will only
be delivered when out of C3. */
* fetches. This is not turned on by default
*/
/* Isoch request wait on GTT enable (Display A/B/C streams).
* Make isoch requests stall on the TLB update. May cause
* display underruns (test mode only)
*/
/* Block grant count for isoch requests when block count is
* set to a finite value.
*/
* If this isn't enabled, render writes are prevented in low
* power states. That seems bad to me.
*/
/* This acknowledges an async flip immediately instead
* of waiting for 2TLB fetches.
*/
/* Enables non-sequential data reads through arbiter
*/
* command stream
*/
/* Arbiter time slice for non-isoch streams */
/* Low priority grace period page size */
/* Disable display A/B trickle feed */
/* Set display plane priority */
/* On modern GEN architectures interrupt control consists of two sets
* of registers. The first set pertains to the ring generating the
* interrupt. The second control is for the functional block generating the
* interrupt. These are PM, GT, DE, etc.
*
* Luckily *knocks on wood* all the ring interrupt bits match up with the
* GT interrupt bits, so we don't need to duplicate the defines.
*
* These defines should cover us well from SNB->HSW with minor exceptions
* it can also work on ILK.
*/
/* These are all the "old" interrupts */
/*
* Framebuffer compression (915+ only)
*/
#define FBC_CTL_PLANEA (0<<0)
/* Framebuffer compression for GM45+ */
#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
#define DPFC_COMP_SEG_SHIFT (0)
/* Framebuffer compression for Ironlake */
/* The bit 28-8 is reserved */
/*
* Framebuffer compression for Sandybridge
*
* The following two registers are of type GTTMMADR
*/
/* Framebuffer compression for Ivybridge */
/*
* GPIO regs
*/
#define GMBUS_PORT_DISABLED 0
#define GMBUS_SLAVE_WRITE (0<<0)
/*
* Clock control & power management
*/
#define VGA0_PD_P1_SHIFT 0
/*
* The i830 generation, in LVDS mode, defines P1 as the bit number set within
* this field (only one bit may be set).
*/
/* i830, required in DVO non-gang */
/* Ironlake */
# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
/*
* Parallel to Serial Load Pulse phase selection.
* Selects the phase for the 10X DPLL clock for the PCIe
* digital display port. The range is 4 to 13; 10 or more
* is just a flip delay. The default is 6
*/
/*
*/
#define SDVO_MULTIPLIER_SHIFT_VGA 0
/*
* UDI pixel divider, controlling how many pixels are stuffed into a packet.
*
* Value is pixels minus 1. Must be set to 1 pixel for SDVO.
*/
/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
/*
*
* SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
* clock rate is 10 times the DPLL clock. At low resolution/refresh rate
* modes, the bus rate would be below the limits, so SDVO allows for stuffing
* dummy bytes in the datastream at an increased clock rate, with both sides of
* the link knowing how many bytes are fill.
*
* So, for a mode with a dotclock of 65Mhz, we would want to double the clock
* rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
* set to 130Mhz, and the SDVO multiplier set to 2x in this register and
* through an SDVO command.
*
* This register field has values of multiplication factor minus 1, with
* a maximum multiplier of 5 for SDVO.
*/
/*
* This best be set to the default value (3) or the CRT won't work. No,
* I don't entirely understand what this does...
*/
#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
#define FP_M2_DIV_SHIFT 0
/**
* This bit must be set on the 830 to prevent hangs when turning off the
* overlay scaler.
*/
/** This bit must be unset on 855,865 */
/** This bit must be set on 855,865. */
/** This bit must always be set on 965G/965GM */
/** This bit must always be set on 965G */
/*
* Palette regs
*/
/* MCH MMIO space */
/*
* MCHBAR mirror.
*
* This mirrors the MCHBAR MMIO space whose location is determined by
* device 0 function 0's pci config register 0x44 or 0x48 and matches it in
* every way. It is not accessible from the CP register read instructions.
*
*/
/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
/** 915-945 and GM965 MCH register controlling DRAM channel access */
#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
/** Pineview MCH register contains DDR3 setting */
/** 965 MCH register controlling DRAM channel configuration */
/** snb MCH registers for reading the DRAM channel configuration */
/* DIMM sizes are in multiples of 256mb. */
#define MAD_DIMM_A_SIZE_SHIFT 0
/** snb MCH registers for priority tuning */
/* Clocking configuration register */
/* Note, below two are guess */
#define INTTOEXT_MAP0_SHIFT 0
#define MEMCTL_CMD_RCLK_OFF 0
when command complete */
#define MEM_INT_STEER_GFX 0
#define MEMMODE_IDLE_MODE_EVAL 0
#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
#define MEMSTAT_SRC_CTL_CORE 0
/*
* Logical Context regs
*/
GEN7_CXT_GT1_SIZE(ctx_reg) + \
/* Haswell does have the CXT_SIZE register however it does not appear to be
* valid. Now, docs explain in dwords what is in the context object. The full
* size is 70720 bytes, however, the power context and execlist context will
* never be saved (power context is stored elsewhere, and execlists don't work
* on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
*/
/*
* Overlay regs
*/
/*
* Display engine regs
*/
/* Pipe A timing regs */
/* Pipe B timing regs */
/* VGA port control */
#define ADPA_DAC_DISABLE 0
#define ADPA_PIPE_A_SELECT 0
/* CPT uses bits 29:30 for pch transcoder select */
#define ADPA_SETS_HVPOLARITY 0
#define ADPA_VSYNC_CNTL_ENABLE 0
#define ADPA_HSYNC_CNTL_ENABLE 0
#define ADPA_VSYNC_ACTIVE_LOW 0
#define ADPA_HSYNC_ACTIVE_LOW 0
/* Hotplug control (945+ only) */
/* must use period 64 on GM45 according to docs */
/*
*
* WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
* Please check the detailed lore in the commit message for for experimental
* evidence.
*/
/* SDVO is different across gen3/4 */
/*
* since reality corrobates that they're the same as on gen3. But keep these
* bits here (and the comment!) to help any other lost wanderers back onto the
* right tracks.
*/
/* SDVO and HDMI port control.
* The same register may be used for SDVO or HDMI */
/* Gen 3 SDVO bits: */
/**
* Programmed value is multiplier - 1, up to 5x.
* \sa DPLL_MD_UDI_MULTIPLIER_MASK
*/
/* Bits to be preserved when writing */
/* DVO port control */
#define DVO_SRCDIM_VERTICAL_SHIFT 0
/* LVDS port control */
/*
* Enables the LVDS port. This bit must be set before DPLLs are enabled, as
* the DPLL semantics change when the LVDS is assigned to that pipe.
*/
/* Selects pipe B for LVDS data. Must be set on pre-965. */
/* LVDS dithering flag on 965/g4x platform */
/* LVDS sync polarity flags. Set to invert (i.e. negative) */
/* Enable border for unscaled (or aspect-scaled) display */
/*
* Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
* pixel.
*/
/*
* Controls the A3 data pair, which contains the additional LSBs for 24 bit
* mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
* on.
*/
/*
* Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
* is set.
*/
/*
* Controls the B0-B3 data pairs. This must be set to match the DPLL p2
* setting for whether we are in dual-channel mode. The B3 pair will
* additionally only be powered up when LVDS_A3_POWER_UP is set.
*/
/* Video Data Island Packet control */
/* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
* (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
* of the infoframe structure specified by CEA-861. */
/* Pre HSW: */
/* HSW and later: */
/* Panel power sequencing */
/*
* Indicates that all dependencies of the panel are on:
*
* - PLL enabled
* - pipe enabled
*/
/* Panel fitting */
/* Pre-965 */
/* 965+ */
#define PFIT_HORIZ_SCALE_SHIFT_965 0
/* Backlight control */
#define BLM_PHASE_IN_INCR_SHIFT (0)
/*
* This is the most significant 15 bits of the number of backlight cycles in a
* complete cycle of the modulated backlight control.
*
* The actual value is this field multiplied by two.
*/
/*
* This is the number of cycles out of the backlight modulation cycle for which
* the backlight is on.
*
* This field must be no greater than the number of cycles in the complete
* backlight modulation cycle.
*/
#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
/* New registers for PCH-split platforms. Safe where new bits show up, the
* register layout machtes with gen4 BLC_PWM_CTL[12]. */
/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
* like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
/* TV port control */
/** Enables the TV encoder */
/** Sources the TV encoder input from pipe B instead of A. */
/** Outputs composite video (DAC A only) */
/** Outputs SVideo video (DAC B/C) */
/** Outputs Component video (DAC A/B/C) */
/** Outputs Composite and SVideo (DAC A/B/C) */
/** Enables slow sync generation (945GM only) */
/** Selects 4x oversampling for 480i and 576p */
/** Selects 2x oversampling for 720p and 1080i */
/** Selects no oversampling for 1080p */
/** Selects 8x oversampling */
/** Selects progressive mode rather than interlaced */
/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
/** Field for setting delay of Y compared to C */
/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
/**
* Enables a fix for the 915GM only.
*
* Not sure what it does.
*/
/** Bits that must be preserved by software */
/** Read-only state that reports all features enabled */
/** Read-only state that reports that Macrovision is disabled in hardware*/
/** Read-only state that reports that TV-out is disabled in hardware. */
/** Normal operation */
# define TV_TEST_MODE_NORMAL (0 << 0)
/** Encoder test pattern 1 - combo pattern */
/** Encoder test pattern 2 - full screen vertical 75% color bars */
/** Encoder test pattern 3 - full screen horizontal 75% color bars */
/** Encoder test pattern 4 - random noise */
/** Encoder test pattern 5 - linear color ramps */
/**
* This test mode forces the DACs to 50% of full output.
*
* This is used for load detection in combination with TVDAC_SENSE_MASK
*/
/**
* Reports that DAC state change logic has reported change (RO).
*
* This gets cleared when TV_DAC_STATE_EN is cleared
*/
/** Reports that DAC A voltage is above the detect threshold */
/** Reports that DAC B voltage is above the detect threshold */
/** Reports that DAC C voltage is above the detect threshold */
/**
* Enables DAC state detection logic, for load-based TV detection.
*
* The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
* to off, for load detection to work.
*/
/** Sets the DAC A sense value to high */
/** Sets the DAC B sense value to high */
/** Sets the DAC C sense value to high */
/** Overrides the ENC_ENABLE and DAC voltage levels */
/** Sets the slew rate. Must be preserved in software */
# define DAC_C_1_3_V (0 << 0)
/**
* CSC coefficients are stored in a floating point format with 9 bits of
* mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
* where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
* -1 (0x3) being the only legal negative value.
*/
# define TV_GY_SHIFT 0
/**
* Y attenuation for component video.
*
* Stored in 1.9 fixed point.
*/
# define TV_AY_SHIFT 0
# define TV_GU_SHIFT 0
/**
* U attenuation for component video.
*
* Stored in 1.9 fixed point.
*/
# define TV_AU_SHIFT 0
# define TV_GV_SHIFT 0
/**
* V attenuation for component video.
*
* Stored in 1.9 fixed point.
*/
# define TV_AV_SHIFT 0
/** 2s-complement brightness adjustment */
/** Contrast adjustment, as a 2.6 unsigned floating point number */
/** Saturation adjustment, as a 2.6 unsigned floating point number */
/** Hue adjustment, as an integer phase angle in degrees */
# define TV_HUE_SHIFT 0
/** Controls the DAC level for black */
/** Controls the DAC level for blanking */
# define TV_BLANK_LEVEL_SHIFT 0
/** Number of pixels in the hsync. */
/** Total number of pixels minus one in the line (display and blanking). */
# define TV_HTOTAL_SHIFT 0
/** Enables the colorburst (needed for non-component color) */
/** Offset of the colorburst from the start of hsync, in pixels minus one. */
/** Length of the colorburst */
# define TV_HBURST_LEN_SHIFT 0
/** End of hblank, measured in pixels minus one from start of hsync */
/** Start of hblank, measured in pixels minus one from start of hsync */
# define TV_HBLANK_START_SHIFT 0
/** XXX */
/** XXX */
/** XXX */
# define TV_VI_END_F2_SHIFT 0
/** Length of vsync, in half lines */
/** Offset of the start of vsync in field 1, measured in one less than the
* number of half lines.
*/
/**
* Offset of the start of vsync in field 2, measured in one less than the
* number of half lines.
*/
# define TV_VSYNC_START_F2_SHIFT 0
/** Enables generation of the equalization signal */
/** Length of vsync, in half lines */
/** Offset of the start of equalization in field 1, measured in one less than
* the number of half lines.
*/
/**
* Offset of the start of equalization in field 2, measured in one less than
* the number of half lines.
*/
# define TV_VEQ_START_F2_SHIFT 0
/**
* Offset to start of vertical colorburst, measured in one less than the
* number of lines from vertical start.
*/
/**
* Offset to the end of vertical colorburst, measured in one less than the
* number of lines from the start of NBR.
*/
# define TV_VBURST_END_F1_SHIFT 0
/**
* Offset to start of vertical colorburst, measured in one less than the
* number of lines from vertical start.
*/
/**
* Offset to the end of vertical colorburst, measured in one less than the
* number of lines from the start of NBR.
*/
# define TV_VBURST_END_F2_SHIFT 0
/**
* Offset to start of vertical colorburst, measured in one less than the
* number of lines from vertical start.
*/
/**
* Offset to the end of vertical colorburst, measured in one less than the
* number of lines from the start of NBR.
*/
# define TV_VBURST_END_F3_SHIFT 0
/**
* Offset to start of vertical colorburst, measured in one less than the
* number of lines from vertical start.
*/
/**
* Offset to the end of vertical colorburst, measured in one less than the
* number of lines from the start of NBR.
*/
# define TV_VBURST_END_F4_SHIFT 0
/** Turns on the first subcarrier phase generation DDA */
/** Turns on the first subcarrier phase generation DDA */
/** Turns on the first subcarrier phase generation DDA */
/** Sets the subcarrier DDA to reset frequency every other field */
/** Sets the subcarrier DDA to reset frequency every fourth field */
/** Sets the subcarrier DDA to reset frequency every eighth field */
/** Sets the subcarrier DDA to never reset the frequency */
/** Sets the peak amplitude of the colorburst.*/
/** Sets the increment of the first subcarrier phase generation DDA */
# define TV_SCDDA1_INC_SHIFT 0
/** Sets the rollover for the second subcarrier phase generation DDA */
/** Sets the increent of the second subcarrier phase generation DDA */
# define TV_SCDDA2_INC_SHIFT 0
/** Sets the rollover for the third subcarrier phase generation DDA */
/** Sets the increent of the third subcarrier phase generation DDA */
# define TV_SCDDA3_INC_SHIFT 0
/** X coordinate of the display from the start of horizontal active */
/** Y coordinate of the display from the start of vertical active (NBR) */
# define TV_YPOS_SHIFT 0
/** Horizontal size of the display window, measured in pixels*/
/**
* Vertical size of the display window, measured in pixels.
*
* Must be even for interlaced modes.
*/
# define TV_YSIZE_SHIFT 0
/**
* Enables automatic scaling calculation.
*
* If set, the rest of the registers are ignored, and the calculated values can
* be read back from the register.
*/
/**
* Disables the vertical filter.
*
* This is required on modes more than 1024 pixels wide */
/** Enables adaptive vertical filtering */
/** Selects the least adaptive vertical filtering mode */
/** Selects the moderately adaptive vertical filtering mode */
/** Selects the most adaptive vertical filtering mode */
/**
* Sets the horizontal scaling factor.
*
* This should be the fractional part of the horizontal scaling factor divided
* by the oversampling rate. TV_HSCALE should be less than 1, and set to:
*
* (src width - 1) / ((oversample * dest width) - 1)
*/
# define TV_HSCALE_FRAC_SHIFT 0
/**
* Sets the integer part of the 3.15 fixed-point vertical scaling factor.
*
* TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
*/
/**
* Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
*
* \sa TV_VSCALE_INT_MASK
*/
# define TV_VSCALE_FRAC_SHIFT 0
/**
* Sets the integer part of the 3.15 fixed-point vertical scaling factor.
*
* TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
*
* For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
*/
/**
* Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
*
* For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
*
* \sa TV_VSCALE_IP_INT_MASK
*/
# define TV_VSCALE_IP_FRAC_SHIFT 0
/**
* Specifies which field to send the CC data in.
*
* CC data is usually sent in field 0.
*/
/** Sets the horizontal position of the CC data. Usually 135. */
/** Sets the vertical position of the CC data. Usually 21 */
# define TV_CC_LINE_SHIFT 0
/** Second word of CC data to be transmitted. */
/** First word of CC data to be transmitted. */
# define TV_CC_DATA_1_SHIFT 0
/* Display Port */
/* Link training mode - select a suitable mode for each stage */
/* CPT Link training mode */
/* Signal voltages. These are mostly controlled by the other end */
/* Signal pre-emphasis levels, like voltages, the other end tells us what
* they want
*/
/* How many wires to use. I guess 3 was too hard */
/* Mystic DPCD version 1.1 special mode */
/* eDP */
/** locked once port is enabled */
/* eDP */
/** sends the clock on lane 15 of the PEG for debug */
/** limit RGB values to avoid confusing TVs */
/** Turn on the audio link */
/** vs and hs sync polarity */
/** A fantasy */
/** The aux channel provides a way to talk to the
* signal sink for DDC etc. Max packet size supported
* is 20 bytes in each direction, hence the 5 fixed
* data registers
*/
#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
/*
* Computing GMCH M and N values for the Display Port link
*
* GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
*
* ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
*
* The GMCH value is used internally
*
* bytes_per_pixel is the number of bytes coming out of the plane,
* which is after the LUTs, so we want the bytes for our color format.
* For our current usage, this is always 3, one byte for R, G and B.
*/
/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
/*
* Computing Link M and N values for the Display Port link
*
* Link M / N = pixel_clock / ls_clk
*
* (the DP spec calls pixel_clock the 'strm_clk')
*
* The Link value is transmitted in the Main Stream
* Attributes and VB-ID.
*/
/* Display & cursor control */
/* Pipe A */
#define PIPECONF_DISABLE 0
#define PIPECONF_SINGLE_WIDE 0
#define PIPECONF_PIPE_UNLOCKED 0
#define PIPECONF_PALETTE 0
/* Note that pre-gen3 does not support interlaced display directly. Panel
* fitting must be disabled on pre-ilk for interlaced. */
/* Ironlake and later have a complete new set of values for interlaced. PFIT
* means panel fitter required, PF means progressive fetch, DBL means power
* saving pixel doubling. */
#define DSPARB_BSTART_SHIFT 0
#define DSPARB_AEND_SHIFT 0
/* drain latency register values*/
/* FIFO watermark sizes etc */
#define PINEVIEW_DFT_HPLLOFF_WM 0
#define PINEVIEW_CURSOR_DFT_WM 0
/* define the Watermark register on Ironlake */
/* Memory latency timer register */
#define MLTR_WM1_SHIFT 0
/* the unit of memory self-refresh latency time is 0.5us */
/* define the fifo size on Ironlake */
/* define the WM info on Sandybridge */
/* the address where we get all kinds of latency value */
#define SSKPD_WM0_SHIFT 0
/*
* The two pipe frame counter registers are not synchronized, so
* reading a stable value is somewhat tricky. The following code
* should work:
*
* do {
* high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
* PIPE_FRAME_HIGH_SHIFT;
* low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
* PIPE_FRAME_LOW_SHIFT);
* high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
* PIPE_FRAME_HIGH_SHIFT);
* } while (high1 != high2);
* frame = (high1 << 8) | low1;
*/
#define PIPE_FRAME_HIGH_SHIFT 0
#define PIPE_PIXEL_SHIFT 0
/* GM45+ just has to be different */
/* Cursor A & B regs */
/* Old style CUR*CNTR flags (desktop 8xx) */
/* New style CUR*CNTR flags */
#define CURSOR_X_SHIFT 0
/* Display A control */
#define DISPLAY_PLANE_DISABLE 0
#define DISPPLANE_GAMMA_DISABLE 0
#define DISPPLANE_STEREO_DISABLE 0
#define DISPPLANE_SEL_PIPE_A 0
#define DISPPLANE_SRC_KEY_DISABLE 0
#define DISPPLANE_NO_LINE_DOUBLE 0
#define DISPPLANE_STEREO_POLARITY_FIRST 0
/* VBIOS flags */
/* Pipe B */
/* Display B control */
#define DISPPLANE_ALPHA_TRANS_DISABLE 0
#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
/* Sprite A control */
/* VBIOS regs */
/* Ironlake */
#define DIGITAL_PORTA_NO_DETECT (0 << 0)
/* refresh rate hardware control */
#define PIPE_DATA_M1_OFFSET 0
#define PIPE_DATA_N1_OFFSET 0
#define PIPE_DATA_M2_OFFSET 0
#define PIPE_DATA_N2_OFFSET 0
#define PIPE_LINK_M1_OFFSET 0
#define PIPE_LINK_N1_OFFSET 0
#define PIPE_LINK_M2_OFFSET 0
#define PIPE_LINK_N2_OFFSET 0
/* PIPEB timing regs are same start from 0x61000 */
/* CPU panel fitter */
/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
/* legacy palette */
#define GAMMA_MODE_MODE_8BIT (0 << 0)
/* interrupts */
/* More Ivybridge lolz */
/* Required on all Ironlake and Sandybridge according to the B-Spec. */
/* GEN7 chicken */
/* WaCatErrorRejectionIssue */
/* PCH */
/* south display engine interrupt */
/* 18 reserved */
/* 12 reserved */
/* CPT */
SDE_FDI_RXB_CPT | \
/* digital port hotplug */
#define PORTD_PULSE_DURATION_2ms (0)
#define PORTC_PULSE_DURATION_2ms (0)
#define PORTB_PULSE_DURATION_2ms (0)
#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
#define DREF_SSC4_DISABLE (0)
/* transcoder */
#define TRANS_HACTIVE_SHIFT 0
#define TRANS_HBLANK_START_SHIFT 0
#define TRANS_HSYNC_START_SHIFT 0
#define TRANS_VACTIVE_SHIFT 0
#define TRANS_VBLANK_START_SHIFT 0
#define TRANS_VSYNC_START_SHIFT 0
/* Per-transcoder DIP controls */
/* Haswell DIP controls */
/* CPU: FDI_TX */
/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
SNB has different settings. */
/* SNB A-stepping */
/* SNB B-stepping */
/* Ironlake: hardwired to 1 */
/* Ivybridge has different bits for lolz */
/* both Tx and Rx */
/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
/* train, dp width same as FDI_TX */
/* CPT */
/* FDI_RX interrupt register format */
/* vlv has 2 sets of panel control regs. */
#define PANEL_POWER_OFF (0 << 0)
#define PANEL_LIGHT_ON_DELAY_SHIFT 0
#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
/* CPT */
#define PORT_TRANS_A_SEL_CPT 0
#define TRANS_DP_VSYNC_ACTIVE_LOW 0
#define TRANS_DP_HSYNC_ACTIVE_LOW 0
/* SNB eDP training params */
/* SNB A-stepping */
/* SNB B-stepping */
/* IVB */
/* legacy values */
#define GEN6_RC0 0
/* IVYBRIDGE DPF */
/* These are the 4 32-bit write offset registers for each stream
* output buffer. It determines the offset from the
* 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
*/
/* HSW Audio */
/* Audio Digital Converter */
/* HSW Power Wells */
/* Per-pipe DDI Function Control */
/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
/* DisplayPort Transport Control */
/* DisplayPort Transport Status */
/* DDI Buffer Control */
/* DDI Buffer Translations */
/* Sideband Interface (SBI) is programmed indirectly, via
* SBI_ADDR, which contains the register offset; and SBI_DATA,
* which contains the payload */
/* SBI offsets */
/* LPT PIXCLK_GATE */
#define PIXCLK_GATE_GATE (0<<0)
/* SPLL */
/* WRPLL */
/* WRPLL divider programming */
#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
/* Port clock selection */
/* Transcoder clock selection */
/* For each transcoder, we need to select the corresponding port clock */
/* LCPLL Control */
/* Pipe WM_LINETIME - watermark line time */
#define PIPE_WM_LINETIME_TIME(x) ((x))
/* SFUSE_STRAP */
/* pipe CSC */
//For gpu top
*/
/* Special gtt memory types */
/* New caching attributes for gen6/sandybridge */
/* flag for GFDT type */
#endif /* _I915_REG_H_ */