* Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2012, 2013, Intel Corporation. All rights reserved. /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* Note: PGETBL_CTL2 has a different offset on G33. */ * The Bridge device's PCI config space has information about the * fb aperture size and the amount of pre-reserved memory. * This is all handled in the intel-gtt.ko module. i915.ko only * cares about the vga bit for the vga rbiter. #
define HPLLCC 0xc0 /* 855 only */#
define GCFGC 0xf0 /* 915+ only *//* Graphics reset regs */ #
define ILK_GDSR 0x2ca4 /* MCHBAR offset */ * Memory interface instructions used by the kernel #
define MI_END_SCENE (
1 <<
4)
/* flush binner and incr scene count *//* IVB has funny definitions for which plane to flip. */ /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw * simply ignores the register load under certain conditions. * - One can actually load arbitrary many arbitrary registers: Simply issue x * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ #
define MI_BATCH_GTT (
2<<
6)
/* aliased with (1<<7) on gen4 */ * 3D instructions used by the kernel * DPIO - a special bus for various display related registers to hide behind * Note: digital port B is DDI0, digital pot C is DDI1 * Per DDI channel DPIO regs /* control register for cpu gtt access */ * Instruction and interrupt control regs #
define RING_WAIT (
1<<
11)
/* gen3+, PRBx_CTL */#
define PRB1_CTL 0x0204c /* 915+ only */#
define INSTPS 0x02070 /* 965+ only */#
define PWRCTXA 0x2088 /* 965GM+ only *//* GM45+ chicken bits -- debug workaround bits that may be required * for various sorts of correct behavior. The top 16 bits of each are * the enables for writing to the corresponding low bit. /* Disables pipelining of read flushes past the SF-WIZ interface. * Required on all Ironlake steppings according to the B-Spec, but the * particular danger of not doing so is not specified. #
define SCPD0 0x0209c /* 915+ only */ will not assert AGPBUSY# and will only be delivered when out of C3. */ /* Make render/texture TLB fetches lower priorty than associated data * fetches. This is not turned on by default /* Isoch request wait on GTT enable (Display A/B/C streams). * Make isoch requests stall on the TLB update. May cause * display underruns (test mode only) /* Block grant count for isoch requests when block count is /* Enable render writes to complete in C2/C3/C4 power states. * If this isn't enabled, render writes are prevented in low * power states. That seems bad to me. /* This acknowledges an async flip immediately instead * of waiting for 2TLB fetches. /* Enables non-sequential data reads through arbiter /* Disable FSB snooping of cacheable write cycles from binner/render /* Arbiter time slice for non-isoch streams */ /* Low priority grace period page size */ /* Disable display A/B trickle feed */ /* Set display plane priority */ #
define BB_ADDR 0x02140 /* 8 bytes *//* On modern GEN architectures interrupt control consists of two sets * of registers. The first set pertains to the ring generating the * interrupt. The second control is for the functional block generating the * interrupt. These are PM, GT, DE, etc. * Luckily *knocks on wood* all the ring interrupt bits match up with the * GT interrupt bits, so we don't need to duplicate the defines. * These defines should cover us well from SNB->HSW with minor exceptions * it can also work on ILK. /* These are all the "old" interrupts */ * Framebuffer compression (915+ only) /* Framebuffer compression for GM45+ */ /* Framebuffer compression for Ironlake */ /* The bit 28-8 is reserved */ * Framebuffer compression for Sandybridge * The following two registers are of type GTTMMADR /* Framebuffer compression for Ivybridge */ #
define GMBUS_ENT (
1<<
29)
/* enable timeout */#
define GMBUS2 0x5108 /* status */#
define GMBUS3 0x510c /* data buffer bytes 3-0 */#
define GMBUS4 0x5110 /* interrupt mask (Pineview+) */#
define GMBUS5 0x5120 /* byte index */ * Clock control & power management * The i830 generation, in LVDS mode, defines P1 as the bit number set within * this field (only one bit may be set). /* i830, required in DVO non-gang */ * Parallel to Serial Load Pulse phase selection. * Selects the phase for the 10X DPLL clock for the PCIe * digital display port. The range is 4 to 13; 10 or more * is just a flip delay. The default is 6 * SDVO multiplier for 945G/GM. Not used on 965. * UDI pixel divider, controlling how many pixels are stuffed into a packet. * Value is pixels minus 1. Must be set to 1 pixel for SDVO. /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus * modes, the bus rate would be below the limits, so SDVO allows for stuffing * dummy bytes in the datastream at an increased clock rate, with both sides of * the link knowing how many bytes are fill. * So, for a mode with a dotclock of 65Mhz, we would want to double the clock * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be * set to 130Mhz, and the SDVO multiplier set to 2x in this register and * through an SDVO command. * This register field has values of multiplication factor minus 1, with * a maximum multiplier of 5 for SDVO. * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. * This best be set to the default value (3) or the CRT won't work. No, * I don't entirely understand what this does... * This bit must be set on the 830 to prevent hangs when turning off the /** This bit must be unset on 855,865 */ /** This bit must be set on 855,865. */ /** This bit must always be set on 965G/965GM */ /** This bit must always be set on 965G */ #
define DEUC 0x6214 /* CRL only */ * This mirrors the MCHBAR MMIO space whose location is determined by * device 0 function 0's pci config register 0x44 or 0x48 and matches it in * every way. It is not accessible from the CP register read instructions. /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ /** 915-945 and GM965 MCH register controlling DRAM channel access */ /** Pineview MCH register contains DDR3 setting */ /** 965 MCH register controlling DRAM channel configuration */ /** snb MCH registers for reading the DRAM channel configuration */ /* DIMM sizes are in multiples of 256mb. */ /** snb MCH registers for priority tuning */ /* Clocking configuration register */ /* Note, below two are guess */ #
define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */#
define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */#
define MEMSWCTL 0x11170 /* Ironlake only */#
define D3RS3EN (
1<<
28)
/* Display D3 imlies RS3 */#
define SWPROMORSX (
1<<
27)
/* RSx promotion timers ignored */#
define RCWAKERW (
1<<
26)
/* Resetwarn from PCH causes wakeup */#
define DPRSLPVREN (
1<<
25)
/* Fast voltage ramp enable */#
define GFXTGHYST (
1<<
24)
/* Hysteresis to allow trunk gating */#
define RCX_SW_EXIT (
1<<
23)
/* Leave RSx and prevent re-entry */#
define UWRCRSXE (
1<<
19)
/* wake counter limit prevents rsx */#
define RSCRP (
1<<
18)
/* rs requests control on rs1/2 reqs */#
define JRSC (
1<<
17)
/* rsx coupled to cpu c-state */#
define RS2INC0 (
1<<
16)
/* allow rs2 in cpu c0 */#
define IMPROMOEN (
1<<
10)
/* promo is immediate or delayed until next idle interval (only for timeout method above) */#
define RCENTSYNC (
1<<
9)
/* rs coupled to cpu c-state (3/6/7) */#
define STATELOCK (
1<<
7)
/* locked to rs_cstate if 0 */#
define REDSAVES (
1<<
3)
/* no context save if was idle during rs0 */#
define REDRESTORES (
1<<
2)
/* no restore if was idle during rs0 */#
define MCPPCE_EN (
1<<0)
/* enable PM_MSG from PCH->MPC *//* Haswell does have the CXT_SIZE register however it does not appear to be * valid. Now, docs explain in dwords what is in the context object. The full * size is 70720 bytes, however, the power context and execlist context will * never be saved (power context is stored elsewhere, and execlists don't work * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages. /* CPT uses bits 29:30 for pch transcoder select */ /* Hotplug control (945+ only) */ /* must use period 64 on GM45 according to docs */ * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. * Please check the detailed lore in the commit message for for experimental /* CRT/TV common between gen3+ */ /* SDVO is different across gen3/4 */ * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, * since reality corrobates that they're the same as on gen3. But keep these * bits here (and the comment!) to help any other lost wanderers back onto the /* SDVO and HDMI port control. * The same register may be used for SDVO or HDMI */ * 915G/GM SDVO pixel multiplier. * Programmed value is multiplier - 1, up to 5x. * \sa DPLL_MD_UDI_MULTIPLIER_MASK /* Bits to be preserved when writing */ /* VSYNC/HSYNC bits new with 965, default is to be set */ * Enables the LVDS port. This bit must be set before DPLLs are enabled, as * the DPLL semantics change when the LVDS is assigned to that pipe. /* Selects pipe B for LVDS data. Must be set on pre-965. */ /* LVDS dithering flag on 965/g4x platform */ /* LVDS sync polarity flags. Set to invert (i.e. negative) */ /* Enable border for unscaled (or aspect-scaled) display */ * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per * Controls the A3 data pair, which contains the additional LSBs for 24 bit * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 * setting for whether we are in dual-channel mode. The B3 pair will * additionally only be powered up when LVDS_A3_POWER_UP is set. /* Video Data Island Packet control */ /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte * of the infoframe structure specified by CEA-861. */ /* Panel power sequencing */ #
define PP_ON (
1UL <<
31)
/* OSOL_i915 */ * Indicates that all dependencies of the panel are on: * This is the most significant 15 bits of the number of backlight cycles in a * complete cycle of the modulated backlight control. * The actual value is this field multiplied by two. * This is the number of cycles out of the backlight modulation cycle for which * This field must be no greater than the number of cycles in the complete * backlight modulation cycle. /* New registers for PCH-split platforms. Safe where new bits show up, the * register layout machtes with gen4 BLC_PWM_CTL[12]. */ /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ /** Enables the TV encoder */ /** Sources the TV encoder input from pipe B instead of A. */ /** Outputs composite video (DAC A only) */ /** Outputs SVideo video (DAC B/C) */ /** Outputs Component video (DAC A/B/C) */ /** Outputs Composite and SVideo (DAC A/B/C) */ /** Enables slow sync generation (945GM only) */ /** Selects 4x oversampling for 480i and 576p */ /** Selects 2x oversampling for 720p and 1080i */ /** Selects no oversampling for 1080p */ /** Selects 8x oversampling */ /** Selects progressive mode rather than interlaced */ /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ /** Field for setting delay of Y compared to C */ /** Enables a fix for 480p/576p standard definition modes on the 915GM only */ * Enables a fix for the 915GM only. /** Bits that must be preserved by software */ #
define TV_CTL_SAVE ((
1 <<
11) | (
3 <<
9) | (
7 <<
6) |
0xf)
/** Read-only state that reports all features enabled */ /** Read-only state that reports that Macrovision is disabled in hardware*/ /** Read-only state that reports that TV-out is disabled in hardware. */ /** Encoder test pattern 1 - combo pattern */ /** Encoder test pattern 2 - full screen vertical 75% color bars */ /** Encoder test pattern 3 - full screen horizontal 75% color bars */ /** Encoder test pattern 4 - random noise */ /** Encoder test pattern 5 - linear color ramps */ * This test mode forces the DACs to 50% of full output. * This is used for load detection in combination with TVDAC_SENSE_MASK * Reports that DAC state change logic has reported change (RO). * This gets cleared when TV_DAC_STATE_EN is cleared /** Reports that DAC A voltage is above the detect threshold */ /** Reports that DAC B voltage is above the detect threshold */ /** Reports that DAC C voltage is above the detect threshold */ * Enables DAC state detection logic, for load-based TV detection. * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set * to off, for load detection to work. /** Sets the DAC A sense value to high */ /** Sets the DAC B sense value to high */ /** Sets the DAC C sense value to high */ /** Overrides the ENC_ENABLE and DAC voltage levels */ /** Sets the slew rate. Must be preserved in software */ * CSC coefficients are stored in a floating point format with 9 bits of * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with * -1 (0x3) being the only legal negative value. * Y attenuation for component video. * Stored in 1.9 fixed point. * U attenuation for component video. * Stored in 1.9 fixed point. * V attenuation for component video. * Stored in 1.9 fixed point. /** 2s-complement brightness adjustment */ /** Contrast adjustment, as a 2.6 unsigned floating point number */ /** Saturation adjustment, as a 2.6 unsigned floating point number */ /** Hue adjustment, as an integer phase angle in degrees */ /** Controls the DAC level for black */ /** Controls the DAC level for blanking */ /** Number of pixels in the hsync. */ /** Total number of pixels minus one in the line (display and blanking). */ /** Enables the colorburst (needed for non-component color) */ /** Offset of the colorburst from the start of hsync, in pixels minus one. */ /** Length of the colorburst */ /** End of hblank, measured in pixels minus one from start of hsync */ /** Start of hblank, measured in pixels minus one from start of hsync */ /** Length of vsync, in half lines */ /** Offset of the start of vsync in field 1, measured in one less than the * Offset of the start of vsync in field 2, measured in one less than the /** Enables generation of the equalization signal */ /** Length of vsync, in half lines */ /** Offset of the start of equalization in field 1, measured in one less than * the number of half lines. * Offset of the start of equalization in field 2, measured in one less than * the number of half lines. * Offset to start of vertical colorburst, measured in one less than the * number of lines from vertical start. * Offset to the end of vertical colorburst, measured in one less than the * number of lines from the start of NBR. * Offset to start of vertical colorburst, measured in one less than the * number of lines from vertical start. * Offset to the end of vertical colorburst, measured in one less than the * number of lines from the start of NBR. * Offset to start of vertical colorburst, measured in one less than the * number of lines from vertical start. * Offset to the end of vertical colorburst, measured in one less than the * number of lines from the start of NBR. * Offset to start of vertical colorburst, measured in one less than the * number of lines from vertical start. * Offset to the end of vertical colorburst, measured in one less than the * number of lines from the start of NBR. /** Turns on the first subcarrier phase generation DDA */ /** Turns on the first subcarrier phase generation DDA */ /** Turns on the first subcarrier phase generation DDA */ /** Sets the subcarrier DDA to reset frequency every other field */ /** Sets the subcarrier DDA to reset frequency every fourth field */ /** Sets the subcarrier DDA to reset frequency every eighth field */ /** Sets the subcarrier DDA to never reset the frequency */ /** Sets the peak amplitude of the colorburst.*/ /** Sets the increment of the first subcarrier phase generation DDA */ /** Sets the rollover for the second subcarrier phase generation DDA */ /** Sets the increent of the second subcarrier phase generation DDA */ /** Sets the rollover for the third subcarrier phase generation DDA */ /** Sets the increent of the third subcarrier phase generation DDA */ /** X coordinate of the display from the start of horizontal active */ /** Y coordinate of the display from the start of vertical active (NBR) */ /** Horizontal size of the display window, measured in pixels*/ * Vertical size of the display window, measured in pixels. * Must be even for interlaced modes. * Enables automatic scaling calculation. * If set, the rest of the registers are ignored, and the calculated values can * be read back from the register. * Disables the vertical filter. * This is required on modes more than 1024 pixels wide */ /** Enables adaptive vertical filtering */ /** Selects the least adaptive vertical filtering mode */ /** Selects the moderately adaptive vertical filtering mode */ /** Selects the most adaptive vertical filtering mode */ * Sets the horizontal scaling factor. * This should be the fractional part of the horizontal scaling factor divided * by the oversampling rate. TV_HSCALE should be less than 1, and set to: * (src width - 1) / ((oversample * dest width) - 1) * Sets the integer part of the 3.15 fixed-point vertical scaling factor. * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. * Sets the integer part of the 3.15 fixed-point vertical scaling factor. * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. * \sa TV_VSCALE_IP_INT_MASK * Specifies which field to send the CC data in. * CC data is usually sent in field 0. /** Sets the horizontal position of the CC data. Usually 135. */ /** Sets the vertical position of the CC data. Usually 21 */ #
define TV_CC_RDY (
1UL <<
31)
/* OSOL_i915 *//** Second word of CC data to be transmitted. */ /** First word of CC data to be transmitted. */ #
define DP_A 0x64000 /* eDP *//* Link training mode - select a suitable mode for each stage */ /* CPT Link training mode */ /* Signal voltages. These are mostly controlled by the other end */ /* Signal pre-emphasis levels, like voltages, the other end tells us what /* How many wires to use. I guess 3 was too hard */ /* Mystic DPCD version 1.1 special mode */ /** locked once port is enabled */ /** sends the clock on lane 15 of the PEG for debug */ /** limit RGB values to avoid confusing TVs */ /** Turn on the audio link */ /** vs and hs sync polarity */ /** The aux channel provides a way to talk to the * signal sink for DDC etc. Max packet size supported * is 20 bytes in each direction, hence the 5 fixed * Computing GMCH M and N values for the Display Port link * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) * The GMCH value is used internally * bytes_per_pixel is the number of bytes coming out of the plane, * which is after the LUTs, so we want the bytes for our color format. * For our current usage, this is always 3, one byte for R, G and B. /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ #
define TU_SIZE(x) (((x)-
1) <<
25)
/* default size 64 */ * Computing Link M and N values for the Display Port link * Link M / N = pixel_clock / ls_clk * (the DP spec calls pixel_clock the 'strm_clk') * The Link value is transmitted in the Main Stream /* Display & cursor control */ /* Note that pre-gen3 does not support interlaced display directly. Panel * fitting must be disabled on pre-ilk for interlaced. */ /* Ironlake and later have a complete new set of values for interlaced. PFIT * means panel fitter required, PF means progressive fetch, DBL means power * saving pixel doubling. */ /* drain latency register values*/ /* FIFO watermark sizes etc */ /* define the Watermark register on Ironlake */ /* Memory latency timer register */ /* the unit of memory self-refresh latency time is 0.5us */ /* define the fifo size on Ironlake */ /* define the WM info on Sandybridge */ /* the address where we get all kinds of latency value */ * The two pipe frame counter registers are not synchronized, so * reading a stable value is somewhat tricky. The following code * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> * PIPE_FRAME_HIGH_SHIFT); * } while (high1 != high2); * frame = (high1 << 8) | low1; /* GM45+ just has to be different */ /* Old style CUR*CNTR flags (desktop 8xx) */ /* New style CUR*CNTR flags */ /* refresh rate hardware control */ /* PIPEB timing regs are same start from 0x61000 */ /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ /* More Ivybridge lolz */ /* Required on all Ironlake and Sandybridge according to the B-Spec. */ /* WaCatErrorRejectionIssue */ /* south display engine interrupt */ /* south display engine interrupt: CPT/PPT */ /* digital port hotplug */ /* Per-transcoder DIP controls */ /* Haswell DIP controls */ /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. SNB has different settings. */ /* Ironlake: hardwired to 1 */ /* Ivybridge has different bits for lolz */ /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ /* train, dp width same as FDI_TX */ /* FDI_RX interrupt register format */ /* vlv has 2 sets of panel control regs. */ /* SNB eDP training params */ /* These are the 4 32-bit write offset registers for each stream * output buffer. It determines the offset from the * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. /* Audio Digital Converter */ /* Per-pipe DDI Function Control */ /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ /* DisplayPort Transport Control */ /* DisplayPort Transport Status */ /* DDI Buffer Translations */ /* Sideband Interface (SBI) is programmed indirectly, via * SBI_ADDR, which contains the register offset; and SBI_DATA, * which contains the payload */ /* WRPLL divider programming */ /* Port clock selection */ /* Transcoder clock selection */ /* For each transcoder, we need to select the corresponding port clock */ /* Pipe WM_LINETIME - watermark line time */ /* Special gtt memory types */ #
endif /* _I915_REG_H_ */