Searched refs:G5 (Results 1 - 17 of 17) sorted by relevance

/openjdk7/jdk/test/sun/rmi/rmic/covariantReturns/
H A DG5Impl.java26 public class G5Impl implements G5 {
H A DG5.java28 public interface G5 extends Remote { interface in inherits:Remote
/openjdk7/hotspot/src/cpu/sparc/vm/
H A DnativeInst_sparc.cpp598 a->ldsw( G5, al1.low10(), G4 ); idx++;
600 a->ldsw( G5, I3, G4 ); idx++;
601 a->ldsb( G5, al1.low10(), G4 ); idx++;
603 a->ldsb( G5, I3, G4 ); idx++;
604 a->ldsh( G5, al1.low10(), G4 ); idx++;
606 a->ldsh( G5, I3, G4 ); idx++;
607 a->lduw( G5, al1.low10(), G4 ); idx++;
609 a->lduw( G5, I3, G4 ); idx++;
610 a->ldub( G5, al1.low10(), G4 ); idx++;
612 a->ldub( G5, I
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H A DvtableStubs_sparc.cpp62 __ inc_counter(SharedRuntime::nof_megamorphic_calls_addr(), G5, G3_scratch); local
77 __ ld(G3_scratch, instanceKlass::vtable_length_offset()*wordSize, G5);
78 __ cmp_and_br_short(G5, vtable_index*vtableEntry::size(), Assembler::greaterUnsigned, Assembler::pt, L);
134 Register G5_interface = G5; // Passed in as an argument
H A Dc1_Runtime1_sparc.cpp158 if (r == G1 || r == G3 || r == G4 || r == G5) {
191 if (r == G1 || r == G3 || r == G4 || r == G5) {
211 if (r == G1 || r == G3 || r == G4 || r == G5) {
255 if (r == G1 || r == G3 || r == G4 || r == G5) {
374 Register G5_klass = G5; // Incoming
463 // G4 contains bci, G5 contains method
464 oop_maps = generate_stub_call(sasm, noreg, CAST_FROM_FN_PTR(address, counter_overflow), G4, G5);
470 Register G5_klass = G5; // Incoming
671 __ mov(O0, G5); // Save the target address.
676 __ jmp(G5,
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H A Dc1_CodeStubs_sparc.cpp76 __ delayed()->mov_or_nop(_method->as_register(), G5);
150 __ delayed()->mov_or_nop(_klass_reg->as_register(), G5);
172 __ delayed()->mov_or_nop(_klass_reg->as_register(), G5);
195 __ delayed()->mov_or_nop(_klass_reg->as_register(), G5);
218 __ delayed()->mov_or_nop(_lock_reg->as_register(), G5);
H A Dc1_FrameMap_sparc.cpp224 /* 23 */ map_register(i++, G5);
252 G5_opr = as_opr(G5);
285 G5_oop_opr = as_oop_opr(G5);
H A Dc1_MacroAssembler_sparc.cpp225 assert(klass == G5, "must be G5");
319 assert(klass == G5, "must be G5");
H A Dregister_sparc.hpp124 CONSTANT_REGISTER_DECLARATION(Register, G5 , (RegisterImpl::gbase + 5));
179 #define G5 ((Register)(G5_RegisterEnumValue)) macro
H A Dregister_definitions_sparc.cpp41 REGISTER_DEFINITION(Register, G5);
H A DstubGenerator_sparc.cpp849 __ mov(G5, L5);
863 __ mov(L5, G5);
1210 const Register right_shift = G5; // right shift bit counter
1264 const Register right_shift = G5; // right shift bit counter
1323 const Register right_shift = G5; // right shift bit counter
2608 __ mov(count, G5);
2609 gen_write_ref_array_pre_barrier(G1, G5, dest_uninitialized);
2621 gen_write_ref_array_post_barrier(G1, G5, O0);
2662 __ mov(count, G5);
2663 gen_write_ref_array_pre_barrier(G1, G5, dest_uninitialize
[all...]
H A Dassembler_sparc.cpp213 addcc( G5, G6, G7 );
263 sdiv( G4, -((1 << 12) - 1), G5 );
327 ldsh( G5, -1, G6 );
336 ldx( G3, G4, G5 );
358 ldstub( G5, G6, G7 );
566 stdcq( 4, G5, G6);
872 mov(G5_method, L1); // avoid clobbering G5
1085 set(badHeapWordVal, G5);
1195 set(badHeapWordVal, G5);
2635 mov(G5,L
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H A Dc1_LIRAssembler_sparc.cpp155 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
1603 __ set_oop(NULL, G5);
2474 op->klass()->as_register() == G5, "must be");
2502 op->klass()->as_register() == G5, "must be");
3189 // G4 is high half, G5 is low half
3191 // clear the top bits of G5, and scale up G4
3192 __ srl (src->as_register_lo(), 0, G5);
3195 __ or3(G4, G5, G4);
3204 __ mov (src->as_register_lo(), G5);
3216 __ ldx(base, disp, G5);
[all...]
H A DsharedRuntime_sparc.cpp187 __ stx(G5, SP, g5_offset+STACK_BIAS);
188 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg());
202 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next());
208 __ rdccr( G5 );
209 __ stx(G5, SP, ccr_offset+STACK_BIAS);
248 __ ldx(SP, g5_offset+STACK_BIAS, G5);
540 // G5: used in inline cache check (methodOop)
1038 // Generate a C2I adapter. On entry we know G5 holds the methodOop. The
H A Dassembler_sparc.hpp69 REGISTER_DECLARATION(Register, G5_method , G5);
88 REGISTER_DECLARATION(Register, Gtemp , G5);
91 REGISTER_DECLARATION(Register, G5_method_type , G5);
103 // G5 register will be used twice during the call. First,
105 // into G5. (This is an ordered pair of ic_klass, method.)
/openjdk7/hotspot/agent/src/share/classes/sun/jvm/hotspot/asm/sparc/
H A DSPARCRegisters.java36 public static final SPARCRegister G5; field in class:SPARCRegisters
74 G5 = new SPARCRegister(5);
107 registerNames[G5.getNumber()] = "%g5";
135 G0, G1, G2, G3, G4, G5, G6, G7, O0, O1,
/openjdk7/jdk/test/java/beans/XMLEncoder/
H A DEnumPrivate.java30 A5,B5,C5,D5,E5,F5,G5,H5,I5,J5,K5,L5,M5,N5,O5,P5,Q5,R5,S5,T5,U5,V5,W5,X5,Y5,Z5, enum constant in enum:EnumPrivate

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