0N/A/*
3158N/A * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A *
0N/A * This code is free software; you can redistribute it and/or modify it
0N/A * under the terms of the GNU General Public License version 2 only, as
0N/A * published by the Free Software Foundation.
0N/A *
0N/A * This code is distributed in the hope that it will be useful, but WITHOUT
0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A * version 2 for more details (a copy is included in the LICENSE file that
0N/A * accompanied this code).
0N/A *
0N/A * You should have received a copy of the GNU General Public License version
0N/A * 2 along with this work; if not, write to the Free Software Foundation,
0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0N/A *
1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1472N/A * or visit www.oracle.com if you need additional information or have any
1472N/A * questions.
0N/A *
0N/A */
0N/A
1879N/A#ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
1879N/A#define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
1879N/A
0N/Aclass BiasedLockingCounters;
0N/A
0N/A// <sys/trap.h> promises that the system will not use traps 16-31
0N/A#define ST_RESERVED_FOR_USER_0 0x10
0N/A
0N/A/* Written: David Ungar 4/19/97 */
0N/A
0N/A// Contains all the definitions needed for sparc assembly code generation.
0N/A
0N/A// Register aliases for parts of the system:
0N/A
0N/A// 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe
0N/A// across context switches in V8+ ABI. Of course, there are no 64 bit regs
0N/A// in V8 ABI. All 64 bits are preserved in V9 ABI for all registers.
0N/A
0N/A// g2-g4 are scratch registers called "application globals". Their
0N/A// meaning is reserved to the "compilation system"--which means us!
0N/A// They are are not supposed to be touched by ordinary C code, although
0N/A// highly-optimized C code might steal them for temps. They are safe
0N/A// across thread switches, and the ABI requires that they be safe
0N/A// across function calls.
0N/A//
0N/A// g1 and g3 are touched by more modules. V8 allows g1 to be clobbered
0N/A// across func calls, and V8+ also allows g5 to be clobbered across
0N/A// func calls. Also, g1 and g5 can get touched while doing shared
0N/A// library loading.
0N/A//
0N/A// We must not touch g7 (it is the thread-self register) and g6 is
0N/A// reserved for certain tools. g0, of course, is always zero.
0N/A//
0N/A// (Sources: SunSoft Compilers Group, thread library engineers.)
0N/A
0N/A// %%%% The interpreter should be revisited to reduce global scratch regs.
0N/A
0N/A// This global always holds the current JavaThread pointer:
0N/A
0N/AREGISTER_DECLARATION(Register, G2_thread , G2);
113N/AREGISTER_DECLARATION(Register, G6_heapbase , G6);
0N/A
0N/A// The following globals are part of the Java calling convention:
0N/A
0N/AREGISTER_DECLARATION(Register, G5_method , G5);
0N/AREGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
0N/AREGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method);
0N/A
0N/A// The following globals are used for the new C1 & interpreter calling convention:
0N/AREGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument
0N/A
0N/A// This local is used to preserve G2_thread in the interpreter and in stubs:
0N/AREGISTER_DECLARATION(Register, L7_thread_cache , L7);
0N/A
0N/A// These globals are used as scratch registers in the interpreter:
0N/A
0N/AREGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch
0N/AREGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME
0N/AREGISTER_DECLARATION(Register, G3_scratch , G3);
0N/AREGISTER_DECLARATION(Register, G4_scratch , G4);
0N/A
0N/A// These globals are used as short-lived scratch registers in the compiler:
0N/A
0N/AREGISTER_DECLARATION(Register, Gtemp , G5);
0N/A
710N/A// JSR 292 fixed register usages:
710N/AREGISTER_DECLARATION(Register, G5_method_type , G5);
710N/AREGISTER_DECLARATION(Register, G3_method_handle , G3);
1484N/AREGISTER_DECLARATION(Register, L7_mh_SP_save , L7);
710N/A
0N/A// The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,
0N/A// because a single patchable "set" instruction (NativeMovConstReg,
0N/A// or NativeMovConstPatching for compiler1) instruction
0N/A// serves to set up either quantity, depending on whether the compiled
0N/A// call site is an inline cache or is megamorphic. See the function
0N/A// CompiledIC::set_to_megamorphic.
0N/A//
710N/A// If a inline cache targets an interpreted method, then the
710N/A// G5 register will be used twice during the call. First,
710N/A// the call site will be patched to load a compiledICHolder
710N/A// into G5. (This is an ordered pair of ic_klass, method.)
710N/A// The c2i adapter will first check the ic_klass, then load
710N/A// G5_method with the method part of the pair just before
710N/A// jumping into the interpreter.
0N/A//
0N/A// Note that G5_method is only the method-self for the interpreter,
0N/A// and is logically unrelated to G5_megamorphic_method.
0N/A//
0N/A// Invariants on G2_thread (the JavaThread pointer):
0N/A// - it should not be used for any other purpose anywhere
0N/A// - it must be re-initialized by StubRoutines::call_stub()
0N/A// - it must be preserved around every use of call_VM
0N/A
0N/A// We can consider using g2/g3/g4 to cache more values than the
0N/A// JavaThread, such as the card-marking base or perhaps pointers into
0N/A// Eden. It's something of a waste to use them as scratch temporaries,
0N/A// since they are not supposed to be volatile. (Of course, if we find
0N/A// that Java doesn't benefit from application globals, then we can just
0N/A// use them as ordinary temporaries.)
0N/A//
0N/A// Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
0N/A// it makes sense to use them routinely for procedure linkage,
0N/A// whenever the On registers are not applicable. Examples: G5_method,
0N/A// G5_inline_cache_klass, and a double handful of miscellaneous compiler
0N/A// stubs. This means that compiler stubs, etc., should be kept to a
0N/A// maximum of two or three G-register arguments.
0N/A
0N/A
0N/A// stub frames
0N/A
0N/AREGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself
0N/A
0N/A// Interpreter frames
0N/A
0N/A#ifdef CC_INTERP
0N/AREGISTER_DECLARATION(Register, Lstate , L0); // interpreter state object pointer
0N/AREGISTER_DECLARATION(Register, L1_scratch , L1); // scratch
0N/AREGISTER_DECLARATION(Register, Lmirror , L1); // mirror (for native methods only)
0N/AREGISTER_DECLARATION(Register, L2_scratch , L2);
0N/AREGISTER_DECLARATION(Register, L3_scratch , L3);
0N/AREGISTER_DECLARATION(Register, L4_scratch , L4);
0N/AREGISTER_DECLARATION(Register, Lscratch , L5); // C1 uses
0N/AREGISTER_DECLARATION(Register, Lscratch2 , L6); // C1 uses
0N/AREGISTER_DECLARATION(Register, L7_scratch , L7); // constant pool cache
0N/AREGISTER_DECLARATION(Register, O5_savedSP , O5);
0N/AREGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
0N/A // a copy SP, so in 64-bit it's a biased value. The bias
0N/A // is added and removed as needed in the frame code.
0N/A// Interface to signature handler
0N/AREGISTER_DECLARATION(Register, Llocals , L7); // pointer to locals for signature handler
0N/AREGISTER_DECLARATION(Register, Lmethod , L6); // methodOop when calling signature handler
0N/A
0N/A#else
0N/AREGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer
0N/AREGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode
0N/AREGISTER_DECLARATION(Register, Lmethod , L2);
0N/AREGISTER_DECLARATION(Register, Llocals , L3);
0N/AREGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler
0N/A // must match Llocals in asm interpreter
0N/AREGISTER_DECLARATION(Register, Lmonitors , L4);
0N/AREGISTER_DECLARATION(Register, Lbyte_code , L5);
0N/A// When calling out from the interpreter we record SP so that we can remove any extra stack
0N/A// space allocated during adapter transitions. This register is only live from the point
0N/A// of the call until we return.
0N/AREGISTER_DECLARATION(Register, Llast_SP , L5);
0N/AREGISTER_DECLARATION(Register, Lscratch , L5);
0N/AREGISTER_DECLARATION(Register, Lscratch2 , L6);
0N/AREGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache
0N/A
0N/AREGISTER_DECLARATION(Register, O5_savedSP , O5);
0N/AREGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
0N/A // a copy SP, so in 64-bit it's a biased value. The bias
0N/A // is added and removed as needed in the frame code.
0N/AREGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables
0N/AREGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
0N/AREGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data
0N/A#endif /* CC_INTERP */
0N/A
0N/A// NOTE: Lscratch2 and LcpoolCache point to the same registers in
0N/A// the interpreter code. If Lscratch2 needs to be used for some
0N/A// purpose than LcpoolCache should be restore after that for
0N/A// the interpreter to work right
0N/A// (These assignments must be compatible with L7_thread_cache; see above.)
0N/A
0N/A// Since Lbcp points into the middle of the method object,
0N/A// it is temporarily converted into a "bcx" during GC.
0N/A
0N/A// Exception processing
0N/A// These registers are passed into exception handlers.
0N/A// All exception handlers require the exception object being thrown.
0N/A// In addition, an nmethod's exception handler must be passed
0N/A// the address of the call site within the nmethod, to allow
0N/A// proper selection of the applicable catch block.
0N/A// (Interpreter frames use their own bcp() for this purpose.)
0N/A//
0N/A// The Oissuing_pc value is not always needed. When jumping to a
0N/A// handler that is known to be interpreted, the Oissuing_pc value can be
0N/A// omitted. An actual catch block in compiled code receives (from its
0N/A// nmethod's exception handler) the thrown exception in the Oexception,
0N/A// but it doesn't need the Oissuing_pc.
0N/A//
0N/A// If an exception handler (either interpreted or compiled)
0N/A// discovers there is no applicable catch block, it updates
0N/A// the Oissuing_pc to the continuation PC of its own caller,
0N/A// pops back to that caller's stack frame, and executes that
0N/A// caller's exception handler. Obviously, this process will
0N/A// iterate until the control stack is popped back to a method
0N/A// containing an applicable catch block. A key invariant is
0N/A// that the Oissuing_pc value is always a value local to
0N/A// the method whose exception handler is currently executing.
0N/A//
0N/A// Note: The issuing PC value is __not__ a raw return address (I7 value).
0N/A// It is a "return pc", the address __following__ the call.
0N/A// Raw return addresses are converted to issuing PCs by frame::pc(),
0N/A// or by stubs. Issuing PCs can be used directly with PC range tables.
0N/A//
0N/AREGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown
0N/AREGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
0N/A
0N/A
0N/A// These must occur after the declarations above
0N/A#ifndef DONT_USE_REGISTER_DEFINES
0N/A
0N/A#define Gthread AS_REGISTER(Register, Gthread)
0N/A#define Gmethod AS_REGISTER(Register, Gmethod)
0N/A#define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)
0N/A#define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg)
0N/A#define Gargs AS_REGISTER(Register, Gargs)
0N/A#define Lthread_cache AS_REGISTER(Register, Lthread_cache)
0N/A#define Gframe_size AS_REGISTER(Register, Gframe_size)
0N/A#define Gtemp AS_REGISTER(Register, Gtemp)
0N/A
0N/A#ifdef CC_INTERP
0N/A#define Lstate AS_REGISTER(Register, Lstate)
0N/A#define Lesp AS_REGISTER(Register, Lesp)
0N/A#define L1_scratch AS_REGISTER(Register, L1_scratch)
0N/A#define Lmirror AS_REGISTER(Register, Lmirror)
0N/A#define L2_scratch AS_REGISTER(Register, L2_scratch)
0N/A#define L3_scratch AS_REGISTER(Register, L3_scratch)
0N/A#define L4_scratch AS_REGISTER(Register, L4_scratch)
0N/A#define Lscratch AS_REGISTER(Register, Lscratch)
0N/A#define Lscratch2 AS_REGISTER(Register, Lscratch2)
0N/A#define L7_scratch AS_REGISTER(Register, L7_scratch)
0N/A#define Ostate AS_REGISTER(Register, Ostate)
0N/A#else
0N/A#define Lesp AS_REGISTER(Register, Lesp)
0N/A#define Lbcp AS_REGISTER(Register, Lbcp)
0N/A#define Lmethod AS_REGISTER(Register, Lmethod)
0N/A#define Llocals AS_REGISTER(Register, Llocals)
0N/A#define Lmonitors AS_REGISTER(Register, Lmonitors)
0N/A#define Lbyte_code AS_REGISTER(Register, Lbyte_code)
0N/A#define Lscratch AS_REGISTER(Register, Lscratch)
0N/A#define Lscratch2 AS_REGISTER(Register, Lscratch2)
0N/A#define LcpoolCache AS_REGISTER(Register, LcpoolCache)
0N/A#endif /* ! CC_INTERP */
0N/A
0N/A#define Lentry_args AS_REGISTER(Register, Lentry_args)
0N/A#define I5_savedSP AS_REGISTER(Register, I5_savedSP)
0N/A#define O5_savedSP AS_REGISTER(Register, O5_savedSP)
0N/A#define IdispatchAddress AS_REGISTER(Register, IdispatchAddress)
0N/A#define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr)
0N/A#define IdispatchTables AS_REGISTER(Register, IdispatchTables)
0N/A
0N/A#define Oexception AS_REGISTER(Register, Oexception)
0N/A#define Oissuing_pc AS_REGISTER(Register, Oissuing_pc)
0N/A
0N/A
0N/A#endif
0N/A
0N/A// Address is an abstraction used to represent a memory location.
0N/A//
0N/A// Note: A register location is represented via a Register, not
0N/A// via an address for efficiency & simplicity reasons.
0N/A
0N/Aclass Address VALUE_OBJ_CLASS_SPEC {
0N/A private:
727N/A Register _base; // Base register.
727N/A RegisterOrConstant _index_or_disp; // Index register or constant displacement.
727N/A RelocationHolder _rspec;
727N/A
727N/A public:
727N/A Address() : _base(noreg), _index_or_disp(noreg) {}
727N/A
727N/A Address(Register base, RegisterOrConstant index_or_disp)
727N/A : _base(base),
727N/A _index_or_disp(index_or_disp) {
727N/A }
727N/A
727N/A Address(Register base, Register index)
727N/A : _base(base),
727N/A _index_or_disp(index) {
727N/A }
727N/A
727N/A Address(Register base, int disp)
727N/A : _base(base),
727N/A _index_or_disp(disp) {
727N/A }
727N/A
Error!

 

There was an error!

null

java.lang.NullPointerException