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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
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#ifndef CPU_SPARC_VM_REGISTER_SPARC_HPP
#define CPU_SPARC_VM_REGISTER_SPARC_HPP
#include "asm/register.hpp"
#include "vm_version_sparc.hpp"
// forward declaration
class Address;
class VMRegImpl;
// Use Register as shortcut
class RegisterImpl;
}
// The implementation of integer registers for the SPARC architecture
public:
enum {
};
// set specific construction
// accessors
const char* name() const;
// testers
// derived registers, offsets, and addresses
int input_number() const {
}
}
}
int sp_offset_in_saved_window() const {
}
};
// set specific construction
// The integer registers of the SPARC architecture
//
// Because sparc has so many registers, #define'ing values for the is
// beneficial in code size and the cost of some of the dangers of
// defines. We don't use them on Intel because win32 uses asm
// directives which use the same names for registers as Hotspot does,
// so #defines would screw up the inline assembly. If a particular
// file has a problem with these defines then it's possible to turn
// them off in that file by defining DONT_USE_REGISTER_DEFINES.
// register_definition_sparc.cpp does that so that it's able to
// provide real definitions of these registers for use in debuggers
// and such.
//
#ifndef DONT_USE_REGISTER_DEFINES
#endif // DONT_USE_REGISTER_DEFINES
// Use FloatRegister as shortcut
class FloatRegisterImpl;
// construction
}
// The implementation of float registers for the SPARC architecture
public:
enum {
};
enum Width {
S = 1, D = 2, Q = 3
};
// construction
// accessors
public:
const int c = encoding();
switch (w) {
case S:
return c;
case D:
return (c & 0x1e) | ((c & 0x20) >> 5);
case Q:
return (c & 0x1c) | ((c & 0x20) >> 5);
}
return -1;
}
const char* name() const;
};
// The float registers of the SPARC architecture
#ifndef DONT_USE_REGISTER_DEFINES
#endif // DONT_USE_REGISTER_DEFINES
// Maximum number of incoming arguments that can be passed in i registers.
const int SPARC_ARGS_IN_REGS_NUM = 6;
class ConcreteRegisterImpl : public AbstractRegisterImpl {
public:
enum {
// This number must be large enough to cover REG_COUNT (defined by c2) registers.
// There is no requirement that any ordering here matches any ordering c2 gives
// it's optoregs.
1 + // ccr
4 // fcc
};
static const int max_gpr;
static const int max_fpr;
};
// Single, Double and Quad fp reg classes. These exist to map the ADLC
// encoding for a floating point register, to the FloatRegister number
// desired by the macroassembler. A FloatRegister is a number between
// 0 and 63 passed around as a pointer. For ADLC, an fp register encoding
// is the actual bit encoding used by the sparc hardware. When ADLC used
// the macroassembler to generate an instruction that references, e.g., a
// double fp reg, it passed the bit encoding to the macroassembler via
// as_FloatRegister, which, for double regs > 30, returns an illegal
// register number.
//
// Therefore we provide the following classes for use by ADLC. Their
// sole purpose is to convert from sparc register encodings to FloatRegisters.
// At some future time, we might replace FloatRegister with these classes,
// hence the definitions of as_xxxFloatRegister as class methods rather
// than as external inline routines.
class SingleFloatRegisterImpl;
typedef SingleFloatRegisterImpl *SingleFloatRegister;
class SingleFloatRegisterImpl {
public:
return as_FloatRegister(encoding);
}
};
class DoubleFloatRegisterImpl;
typedef DoubleFloatRegisterImpl *DoubleFloatRegister;
class DoubleFloatRegisterImpl {
public:
}
};
class QuadFloatRegisterImpl;
typedef QuadFloatRegisterImpl *QuadFloatRegister;
class QuadFloatRegisterImpl {
public:
}
};
#endif // CPU_SPARC_VM_REGISTER_SPARC_HPP