0N/A

1879N/A#include "precompiled.hpp"

1879N/A#include "c1/c1_Compilation.hpp"

1879N/A#include "c1/c1_LIRAssembler.hpp"

1879N/A#include "c1/c1_MacroAssembler.hpp"

1879N/A#include "c1/c1_Runtime1.hpp"

1879N/A#include "c1/c1_ValueStack.hpp"

1879N/A#include "ci/ciArrayKlass.hpp"

1879N/A#include "ci/ciInstance.hpp"

1879N/A#include "gc_interface/collectedHeap.hpp"

1879N/A#include "memory/barrierSet.hpp"

1879N/A#include "memory/cardTableModRefBS.hpp"

1879N/A#include "nativeInst_sparc.hpp"

1879N/A#include "oops/objArrayKlass.hpp"

1879N/A#include "runtime/sharedRuntime.hpp"

0N/A

0N/A#define __ _masm->

0N/A

0N/A

0N/A

0N/A

0N/Abool LIR_Assembler::is_small_constant(LIR_Opr opr) {

0N/A if (opr->is_constant()) {

0N/A LIR_Const* constant = opr->as_constant_ptr();

0N/A switch (constant->type()) {

0N/A case T_INT: {

0N/A jint value = constant->as_jint();

0N/A return Assembler::is_simm13(value);

0N/A }

0N/A

0N/A default:

0N/A return false;

0N/A }

0N/A }

0N/A return false;

0N/A}

0N/A

0N/A

0N/Abool LIR_Assembler::is_single_instruction(LIR_Op* op) {

0N/A switch (op->code()) {

0N/A case lir_null_check:

0N/A return true;

0N/A

0N/A

0N/A case lir_add:

0N/A case lir_ushr:

0N/A case lir_shr:

0N/A case lir_shl:

0N/A // integer shifts and adds are always one instruction

0N/A return op->result_opr()->is_single_cpu();

0N/A

0N/A

0N/A case lir_move: {

0N/A LIR_Op1* op1 = op->as_Op1();

0N/A LIR_Opr src = op1->in_opr();

0N/A LIR_Opr dst = op1->result_opr();

0N/A

0N/A if (src == dst) {

0N/A NEEDS_CLEANUP;

0N/A // this works around a problem where moves with the same src and dst

0N/A // end up in the delay slot and then the assembler swallows the mov

0N/A // since it has no effect and then it complains because the delay slot

0N/A // is empty. returning false stops the optimizer from putting this in

0N/A // the delay slot

0N/A return false;

0N/A }

0N/A

0N/A // don't put moves involving oops into the delay slot since the VerifyOops code

0N/A // will make it much larger than a single instruction.

0N/A if (VerifyOops) {

0N/A return false;

0N/A }

0N/A

0N/A if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||

0N/A ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {

0N/A return false;

0N/A }

0N/A

1909N/A if (UseCompressedOops) {

1909N/A if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false;

1909N/A if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;

1909N/A }

1909N/A

0N/A if (dst->is_register()) {

0N/A if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {

0N/A return !PatchALot;

0N/A } else if (src->is_single_stack()) {

0N/A return true;

0N/A }

0N/A }

0N/A

0N/A if (src->is_register()) {

0N/A if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {

0N/A return !PatchALot;

0N/A } else if (dst->is_single_stack()) {

0N/A return true;

0N/A }

0N/A }

0N/A

0N/A if (dst->is_register() &&

0N/A ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||

0N/A (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {

0N/A return true;

0N/A }

0N/A

0N/A return false;

0N/A }

0N/A

0N/A default:

0N/A return false;

0N/A }

0N/A ShouldNotReachHere();

0N/A}

0N/A

0N/A

0N/ALIR_Opr LIR_Assembler::receiverOpr() {

0N/A return FrameMap::O0_oop_opr;

0N/A}

0N/A

0N/A

0N/ALIR_Opr LIR_Assembler::osrBufferPointer() {

0N/A return FrameMap::I0_opr;

0N/A}

0N/A

0N/A

0N/Aint LIR_Assembler::initial_frame_size_in_bytes() {

0N/A return in_bytes(frame_map()->framesize_in_bytes());

0N/A}

0N/A

0N/A

0N/Aint LIR_Assembler::check_icache() {

0N/A int offset = __ offset();

0N/A __ inline_cache_check(O0, G5_inline_cache_reg);

0N/A return offset;

0N/A}

0N/A

0N/A

0N/Avoid LIR_Assembler::osr_entry() {

0N/A // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):

0N/A //

0N/A // 1. Create a new compiled activation.

0N/A // 2. Initialize local variables in the compiled activation. The expression stack must be empty

0N/A // at the osr_bci; it is not initialized.

0N/A // 3. Jump to the continuation address in compiled code to resume execution.

0N/A

0N/A // OSR entry point

0N/A offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());

0N/A BlockBegin* osr_entry = compilation()->hir()->osr_entry();

0N/A ValueStack* entry_state = osr_entry->end()->state();

0N/A int number_of_locks = entry_state->locks_size();

0N/A

0N/A // Create a frame for the compiled activation.

0N/A __ build_frame(initial_frame_size_in_bytes());

0N/A

0N/A // OSR buffer is

0N/A //

0N/A // locals[nlocals-1..0]

0N/A // monitors[number_of_locks-1..0]

0N/A //

0N/A // locals is a direct copy of the interpreter frame so in the osr buffer

0N/A // so first slot in the local array is the last local from the interpreter

0N/A // and last slot is local[0] (receiver) from the interpreter

0N/A //

0N/A // Similarly with locks. The first lock slot in the osr buffer is the nth lock

0N/A // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock

0N/A // in the interpreter frame (the method lock if a sync method)

0N/A

0N/A // Initialize monitors in the compiled activation.

0N/A // I0: pointer to osr buffer

0N/A //

0N/A // All other registers are dead at this point and the locals will be

0N/A // copied into place by code emitted in the IR.

0N/A

0N/A Register OSR_buf = osrBufferPointer()->as_register();

0N/A { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");

0N/A int monitor_offset = BytesPerWord * method()->max_locals() +

1060N/A (2 * BytesPerWord) * (number_of_locks - 1);

1060N/A // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in

1060N/A // the OSR buffer using 2 word entries: first the lock and then

1060N/A // the oop.

0N/A for (int i = 0; i < number_of_locks; i++) {

1060N/A int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);

0N/A#ifdef ASSERT

0N/A // verify the interpreter's monitor has a non-null object

0N/A {

0N/A Label L;

1060N/A __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);

2664N/A __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L);

0N/A __ stop("locked object is NULL");

0N/A __ bind(L);

0N/A }

0N/A#endif // ASSERT

0N/A // Copy the lock field into the compiled activation.

1060N/A __ ld_ptr(OSR_buf, slot_offset + 0, O7);

0N/A __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));

1060N/A __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);

0N/A __ st_ptr(O7, frame_map()->address_for_monitor_object(i));

0N/A }

0N/A }

0N/A}

0N/A

0N/A

0N/Avoid LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) {

0N/A Register str0 = left->as_register();

0N/A Register str1 = right->as_register();

0N/A

0N/A Label Ldone;

0N/A

0N/A Register result = dst->as_register();

0N/A {

3726N/A // Get a pointer to the first character of string0 in tmp0

3726N/A // and get string0.length() in str0

3726N/A // Get a pointer to the first character of string1 in tmp1

3726N/A // and get string1.length() in str1

3726N/A // Also, get string0.length()-string1.length() in

3726N/A // o7 and get the condition code set

0N/A // Note: some instructions have been hoisted for better instruction scheduling

0N/A

0N/A Register tmp0 = L0;

0N/A Register tmp1 = L1;

0N/A Register tmp2 = L2;

0N/A

0N/A int value_offset = java_lang_String:: value_offset_in_bytes(); // char array

3726N/A if (java_lang_String::has_offset_field()) {

3726N/A int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position

3726N/A int count_offset = java_lang_String:: count_offset_in_bytes();

3726N/A __ load_heap_oop(str0, value_offset, tmp0);

3726N/A __ ld(str0, offset_offset, tmp2);

3726N/A __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);

3726N/A __ ld(str0, count_offset, str0);

3726N/A __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);

3726N/A } else {

3726N/A __ load_heap_oop(str0, value_offset, tmp1);

3726N/A __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);

3726N/A __ ld(tmp1, arrayOopDesc::length_offset_in_bytes(), str0);

3726N/A }

0N/A

0N/A // str1 may be null

0N/A add_debug_info_for_null_check_here(info);

0N/A

3726N/A if (java_lang_String::has_offset_field()) {

3726N/A int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position

3726N/A int count_offset = java_lang_String:: count_offset_in_bytes();

3726N/A __ load_heap_oop(str1, value_offset, tmp1);

3726N/A __ add(tmp0, tmp2, tmp0);

3726N/A

3726N/A __ ld(str1, offset_offset, tmp2);

3726N/A __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);

3726N/A __ ld(str1, count_offset, str1);

3726N/A __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);

3726N/A __ add(tmp1, tmp2, tmp1);

3726N/A } else {

3726N/A __ load_heap_oop(str1, value_offset, tmp2);

3726N/A __ add(tmp2, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);

3726N/A __ ld(tmp2, arrayOopDesc::length_offset_in_bytes(), str1);

3726N/A }

0N/A __ subcc(str0, str1, O7);

0N/A }

0N/A

0N/A {

0N/A // Compute the minimum of the string lengths, scale it and store it in limit

0N/A Register count0 = I0;

0N/A Register count1 = I1;

0N/A Register limit = L3;

0N/A

0N/A Label Lskip;

0N/A __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter

0N/A __ br(Assembler::greater, true, Assembler::pt, Lskip);

0N/A __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter

0N/A __ bind(Lskip);

0N/A

0N/A // If either string is empty (or both of them) the result is the difference in lengths

0N/A __ cmp(limit, 0);

0N/A __ br(Assembler::equal, true, Assembler::pn, Ldone);

0N/A __ delayed()->mov(O7, result); // result is difference in lengths

0N/A }

0N/A

0N/A {

0N/A // Neither string is empty

0N/A Label Lloop;

0N/A

0N/A Register base0 = L0;

0N/A Register base1 = L1;

0N/A Register chr0 = I0;

0N/A Register chr1 = I1;

0N/A Register limit = L3;

0N/A

0N/A // Shift base0 and base1 to the end of the arrays, negate limit

0N/A __ add(base0, limit, base0);

0N/A __ add(base1, limit, base1);

3726N/A __ neg(limit); // limit = -min{string0.length(), string1.length()}

0N/A

0N/A __ lduh(base0, limit, chr0);

0N/A __ bind(Lloop);

0N/A __ lduh(base1, limit, chr1);

0N/A __ subcc(chr0, chr1, chr0);

0N/A __ br(Assembler::notZero, false, Assembler::pn, Ldone);

0N/A assert(chr0 == result, "result must be pre-placed");

0N/A __ delayed()->inccc(limit, sizeof(jchar));

0N/A __ br(Assembler::notZero, true, Assembler::pt, Lloop);

0N/A __ delayed()->lduh(base0, limit, chr0);

0N/A }

0N/A

0N/A // If strings are equal up to min length, return the length difference.

0N/A __ mov(O7, result);

0N/A

0N/A // Otherwise, return the difference between the first mismatched chars.

0N/A __ bind(Ldone);

0N/A}

0N/A

0N/A

0N/A

0N/Avoid LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {

0N/A if (!GenerateSynchronizationCode) return;

0N/A

0N/A Register obj_reg = obj_opr->as_register();

0N/A Register lock_reg = lock_opr->as_register();

0N/A

0N/A Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);

0N/A Register reg = mon_addr.base();

0N/A int offset = mon_addr.disp();

0N/A // compute pointer to BasicLock

0N/A if (mon_addr.is_simm13()) {

0N/A __ add(reg, offset, lock_reg);

0N/A }

0N/A else {

0N/A __ set(offset, lock_reg);

0N/A __ add(reg, lock_reg, lock_reg);

0N/A }

0N/A // unlock object

0N/A MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);

0N/A // _slow_case_stubs->append(slow_case);

0N/A // temporary fix: must be created after exceptionhandler, therefore as call stub

0N/A _slow_case_stubs->append(slow_case);

0N/A if (UseFastLocking) {

0N/A // try inlined fast unlocking first, revert to slow locking if it fails

0N/A // note: lock_reg points to the displaced header since the displaced header offset is 0!

0N/A assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");

0N/A __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());

0N/A } else {

0N/A // always do slow unlocking

0N/A // note: the slow unlocking code could be inlined here, however if we use

0N/A // slow unlocking, speed doesn't matter anyway and this solution is

0N/A // simpler and requires less duplicated code - additionally, the

0N/A // slow unlocking code is the same in either case which simplifies

0N/A // debugging

0N/A __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());

0N/A __ delayed()->nop();

0N/A }

0N/A // done

0N/A __ bind(*slow_case->continuation());

0N/A}

0N/A

0N/A

1204N/Aint LIR_Assembler::emit_exception_handler() {

0N/A // if the last instruction is a call (typically to do a throw which

0N/A // is coming at the end after block reordering) the return address

0N/A // must still point into the code area in order to avoid assertion

0N/A // failures when searching for the corresponding bci => add a nop

0N/A // (was bug 5/14/1999 - gri)

0N/A __ nop();

0N/A

0N/A // generate code for exception handler

0N/A ciMethod* method = compilation()->method();

0N/A

0N/A address handler_base = __ start_a_stub(exception_handler_size);

0N/A

0N/A if (handler_base == NULL) {

0N/A // not enough space left for the handler

0N/A bailout("exception handler overflow");

1204N/A return -1;

0N/A }

1204N/A

0N/A int offset = code_offset();

0N/A

2168N/A __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);

0N/A __ delayed()->nop();

2168N/A __ should_not_reach_here();

3089N/A guarantee(code_offset() - offset <= exception_handler_size, "overflow");

0N/A __ end_a_stub();

1204N/A

1204N/A return offset;

0N/A}

0N/A

1204N/A

1378N/Aint LIR_Assembler::emit_unwind_handler() {

1378N/A#ifndef PRODUCT

1378N/A if (CommentedAssembly) {

1378N/A _masm->block_comment("Unwind handler");

1378N/A }

1378N/A#endif

1378N/A

1378N/A int offset = code_offset();

1378N/A

1378N/A // Fetch the exception from TLS and clear out exception related thread state

1378N/A __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0);

1378N/A __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));

1378N/A __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));

1378N/A

1378N/A __ bind(_unwind_handler_entry);

1378N/A __ verify_not_null_oop(O0);

1378N/A if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {

1378N/A __ mov(O0, I0); // Preserve the exception

1378N/A }

1378N/A

1378N/A // Preform needed unlocking

1378N/A MonitorExitStub* stub = NULL;

1378N/A if (method()->is_synchronized()) {

1378N/A monitor_address(0, FrameMap::I1_opr);

1378N/A stub = new MonitorExitStub(FrameMap::I1_opr, true, 0);

1378N/A __ unlock_object(I3, I2, I1, *stub->entry());

1378N/A __ bind(*stub->continuation());

1378N/A }

1378N/A

1378N/A if (compilation()->env()->dtrace_method_probes()) {

1750N/A __ mov(G2_thread, O0);

1750N/A jobject2reg(method()->constant_encoding(), O1);

1378N/A __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type);

1378N/A __ delayed()->nop();

1378N/A }

1378N/A

1378N/A if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {

1378N/A __ mov(I0, O0); // Restore the exception

1378N/A }

1378N/A

1378N/A // dispatch to the unwind logic

1378N/A __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);

1378N/A __ delayed()->nop();

1378N/A

1378N/A // Emit the slow path assembly

1378N/A if (stub != NULL) {

1378N/A stub->emit_code(this);

1378N/A }

1378N/A

1378N/A return offset;

1378N/A}

1378N/A

1378N/A

1204N/Aint LIR_Assembler::emit_deopt_handler() {

0N/A // if the last instruction is a call (typically to do a throw which

0N/A // is coming at the end after block reordering) the return address

0N/A // must still point into the code area in order to avoid assertion

0N/A // failures when searching for the corresponding bci => add a nop

0N/A // (was bug 5/14/1999 - gri)

0N/A __ nop();

0N/A

0N/A // generate code for deopt handler

0N/A ciMethod* method = compilation()->method();

0N/A address handler_base = __ start_a_stub(deopt_handler_size);

0N/A if (handler_base == NULL) {

0N/A // not enough space left for the handler

0N/A bailout("deopt handler overflow");

1204N/A return -1;

0N/A }

1204N/A

0N/A int offset = code_offset();

727N/A AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());

727N/A __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp

0N/A __ delayed()->nop();

3089N/A guarantee(code_offset() - offset <= deopt_handler_size, "overflow");

0N/A __ end_a_stub();

1204N/A

1204N/A return offset;

0N/A}

0N/A

0N/A

0N/Avoid LIR_Assembler::jobject2reg(jobject o, Register reg) {

0N/A if (o == NULL) {

0N/A __ set(NULL_WORD, reg);

0N/A } else {

0N/A int oop_index = __ oop_recorder()->find_index(o);

0N/A RelocationHolder rspec = oop_Relocation::spec(oop_index);

0N/A __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created

0N/A }

0N/A}

0N/A

0N/A

0N/Avoid LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {

0N/A // Allocate a new index in oop table to hold the oop once it's been patched

0N/A int oop_index = __ oop_recorder()->allocate_index((jobject)NULL);

0N/A PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index);

0N/A

727N/A AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));

727N/A assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");

0N/A // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the

0N/A // NULL will be dynamically patched later and the patched value may be large. We must

0N/A // therefore generate the sethi/add as a placeholders

727N/A __ patchable_set(addrlit, reg);

0N/A

0N/A patching_epilog(patch, lir_patch_normal, reg, info);

0N/A}

0N/A

0N/A

0N/Avoid LIR_Assembler::emit_op3(LIR_Op3* op) {

0N/A Register Rdividend = op->in_opr1()->as_register();

0N/A Register Rdivisor = noreg;

0N/A Register Rscratch = op->in_opr3()->as_register();

0N/A Register Rresult = op->result_opr()->as_register();

0N/A int divisor = -1;

0N/A

0N/A if (op->in_opr2()->is_register()) {

0N/A Rdivisor = op->in_opr2()->as_register();

0N/A } else {

0N/A divisor = op->in_opr2()->as_constant_ptr()->as_jint();

0N/A assert(Assembler::is_simm13(divisor), "can only handle simm13");

0N/A }

0N/A

0N/A assert(Rdividend != Rscratch, "");

0N/A assert(Rdivisor != Rscratch, "");

0N/A assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");

0N/A

0N/A if (Rdivisor == noreg && is_power_of_2(divisor)) {

0N/A // convert division by a power of two into some shifts and logical operations

0N/A if (op->code() == lir_idiv) {

0N/A if (divisor == 2) {

0N/A __ srl(Rdividend, 31, Rscratch);

0N/A } else {

0N/A __ sra(Rdividend, 31, Rscratch);

0N/A __ and3(Rscratch, divisor - 1, Rscratch);

0N/A }

0N/A __ add(Rdividend, Rscratch, Rscratch);

0N/A __ sra(Rscratch, log2_intptr(divisor), Rresult);

0N/A return;

0N/A } else {

0N/A if (divisor == 2) {

0N/A __ srl(Rdividend, 31, Rscratch);

0N/A } else {

0N/A __ sra(Rdividend, 31, Rscratch);

0N/A __ and3(Rscratch, divisor - 1,Rscratch);

0N/A }

0N/A __ add(Rdividend, Rscratch, Rscratch);

0N/A __ andn(Rscratch, divisor - 1,Rscratch);

0N/A __ sub(Rdividend, Rscratch, Rresult);

0N/A return;

0N/A }

0N/A }

0N/A

0N/A __ sra(Rdividend, 31, Rscratch);

0N/A __ wry(Rscratch);

0N/A if (!VM_Version::v9_instructions_work()) {

0N/A // v9 doesn't require these nops

0N/A __ nop();

0N/A __ nop();

0N/A __ nop();

0N/A __ nop();

0N/A }

0N/A

0N/A add_debug_info_for_div0_here(op->info());

0N/A

0N/A if (Rdivisor != noreg) {

0N/A __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));

0N/A } else {

0N/A assert(Assembler::is_simm13(divisor), "can only handle simm13");

0N/A __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));

0N/A }

0N/A

0N/A Label skip;

0N/A __ br(Assembler::overflowSet, true, Assembler::pn, skip);

0N/A __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));

0N/A __ bind(skip);

0N/A

0N/A if (op->code() == lir_irem) {

0N/A if (Rdivisor != noreg) {

0N/A __ smul(Rscratch, Rdivisor, Rscratch);

0N/A } else {

0N/A __ smul(Rscratch, divisor, Rscratch);

0N/A }

0N/A __ sub(Rdividend, Rscratch, Rresult);

0N/A }

0N/A}

0N/A

0N/A

0N/Avoid LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {

0N/A#ifdef ASSERT

0N/A assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");

0N/A if (op->block() != NULL) _branch_target_blocks.append(op->block());

0N/A if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());

0N/A#endif

0N/A assert(op->info() == NULL, "shouldn't have CodeEmitInfo");

0N/A

0N/A if (op->cond() == lir_cond_always) {

0N/A __ br(Assembler::always, false, Assembler::pt, *(op->label()));

0N/A } else if (op->code() == lir_cond_float_branch) {

0N/A assert(op->ublock() != NULL, "must have unordered successor");

0N/A bool is_unordered = (op->ublock() == op->block());

0N/A Assembler::Condition acond;

0N/A switch (op->cond()) {

0N/A case lir_cond_equal: acond = Assembler::f_equal; break;

0N/A case lir_cond_notEqual: acond = Assembler::f_notEqual; break;

0N/A case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;

0N/A case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;

0N/A case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;

0N/A case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;

0N/A default : ShouldNotReachHere();

0N/A };

0N/A

0N/A if (!VM_Version::v9_instructions_work()) {

0N/A __ nop();

0N/A }

0N/A __ fb( acond, false, Assembler::pn, *(op->label()));

0N/A } else {

0N/A assert (op->code() == lir_branch, "just checking");

0N/A

0N/A Assembler::Condition acond;

0N/A switch (op->cond()) {

0N/A case lir_cond_equal: acond = Assembler::equal; break;

0N/A case lir_cond_notEqual: acond = Assembler::notEqual; break;

0N/A case lir_cond_less: acond = Assembler::less; break;

0N/A case lir_cond_lessEqual: acond = Assembler::lessEqual; break;

0N/A case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;

0N/A case lir_cond_greater: acond = Assembler::greater; break;

0N/A case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;

0N/A case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;

0N/A default: ShouldNotReachHere();

0N/A };

0N/A

0N/A // sparc has different condition codes for testing 32-bit

0N/A // vs. 64-bit values. We could always test xcc is we could

0N/A // guarantee that 32-bit loads always sign extended but that isn't

0N/A // true and since sign extension isn't free, it would impose a

0N/A // slight cost.

0N/A#ifdef _LP64

0N/A if (op->type() == T_INT) {

0N/A __ br(acond, false, Assembler::pn, *(op->label()));

0N/A } else

0N/A#endif

0N/A __ brx(acond, false, Assembler::pn, *(op->label()));

0N/A }

0N/A // The peephole pass fills the delay slot

0N/A}

0N/A

0N/A

0N/Avoid LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {

0N/A Bytecodes::Code code = op->bytecode();

0N/A LIR_Opr dst = op->result_opr();

0N/A

0N/A switch(code) {

0N/A case Bytecodes::_i2l: {

0N/A Register rlo = dst->as_register_lo();

0N/A Register rhi = dst->as_register_hi();

0N/A Register rval = op->in_opr()->as_register();

0N/A#ifdef _LP64

0N/A __ sra(rval, 0, rlo);

0N/A#else

0N/A __ mov(rval, rlo);

0N/A __ sra(rval, BitsPerInt-1, rhi);

0N/A#endif

0N/A break;

0N/A }

0N/A case Bytecodes::_i2d:

0N/A case Bytecodes::_i2f: {

0N/A bool is_double = (code == Bytecodes::_i2d);

0N/A FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();

0N/A FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;

0N/A FloatRegister rsrc = op->in_opr()->as_float_reg();

0N/A if (rsrc != rdst) {

0N/A __ fmov(FloatRegisterImpl::S, rsrc, rdst);

0N/A }

0N/A __ fitof(w, rdst, rdst);

0N/A break;

0N/A }

0N/A case Bytecodes::_f2i:{

0N/A FloatRegister rsrc = op->in_opr()->as_float_reg();

0N/A Address addr = frame_map()->address_for_slot(dst->single_stack_ix());

0N/A Label L;

0N/A // result must be 0 if value is NaN; test by comparing value to itself

0N/A __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);

0N/A if (!VM_Version::v9_instructions_work()) {

0N/A __ nop();

0N/A }

0N/A __ fb(Assembler::f_unordered, true, Assembler::pn, L);

0N/A __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN

0N/A __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);

0N/A // move integer result from float register to int register

0N/A __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());

0N/A __ bind (L);

0N/A break;

0N/A }

0N/A case Bytecodes::_l2i: {

0N/A Register rlo = op->in_opr()->as_register_lo();

0N/A Register rhi = op->in_opr()->as_register_hi();

0N/A Register rdst = dst->as_register();

0N/A#ifdef _LP64

0N/A __ sra(rlo, 0, rdst);

0N/A#else

0N/A __ mov(rlo, rdst);

0N/A#endif

0N/A break;

0N/A }

0N/A case Bytecodes::_d2f:

0N/A case Bytecodes::_f2d: {

0N/A bool is_double = (code == Bytecodes::_f2d);

0N/A assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");

0N/A LIR_Opr val = op->in_opr();

0N/A FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();

0N/A FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();

0N/A FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;

0N/A FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;

0N/A __ ftof(vw, dw, rval, rdst);

0N/A break;

0N/A }

0N/A case Bytecodes::_i2s:

0N/A case Bytecodes::_i2b: {

0N/A Register rval = op->in_opr()->as_register();

0N/A Register rdst = dst->as_register();

0N/A int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);

0N/A __ sll (rval, shift, rdst);

0N/A __ sra (rdst, shift, rdst);

0N/A break;

0N/A }

0N/A case Bytecodes::_i2c: {

0N/A Register rval = op->in_opr()->as_register();

0N/A Register rdst = dst->as_register();

0N/A int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;

0N/A __ sll (rval, shift, rdst);

0N/A __ srl (rdst, shift, rdst);

0N/A break;

0N/A }

0N/A

0N/A default: ShouldNotReachHere();

0N/A }

0N/A}

0N/A

0N/A

0N/Avoid LIR_Assembler::align_call(LIR_Code) {

0N/A // do nothing since all instructions are word aligned on sparc

0N/A}

0N/A

0N/A

1295N/Avoid LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {

1295N/A __ call(op->addr(), rtype);

1484N/A // The peephole pass fills the delay slot, add_call_info is done in

1484N/A // LIR_Assembler::emit_delay.

0N/A}

0N/A

0N/A

1295N/Avoid LIR_Assembler::ic_call(LIR_OpJavaCall* op) {

0N/A RelocationHolder rspec = virtual_call_Relocation::spec(pc());

0N/A __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);

0N/A __ relocate(rspec);

1295N/A __ call(op->addr(), relocInfo::none);

1484N/A // The peephole pass fills the delay slot, add_call_info is done in

1484N/A // LIR_Assembler::emit_delay.

0N/A}

0N/A

0N/A

1295N/Avoid LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {

1295N/A add_debug_info_for_null_check_here(op->info());

1909N/A __ load_klass(O0, G3_scratch);

2957N/A if (Assembler::is_simm13(op->vtable_offset())) {

1295N/A __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);

0N/A } else {

0N/A // This will generate 2 instructions

1295N/A __ set(op->vtable_offset(), G5_method);

0N/A // ld_ptr, set_hi, set

0N/A __ ld_ptr(G3_scratch, G5_method, G5_method);

0N/A }

727N/A __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);

0N/A __ callr(G3_scratch, G0);

0N/A // the peephole pass fills the delay slot

0N/A}

0N/A

1909N/Aint LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {

0N/A int store_offset;

0N/A if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {

0N/A assert(!unaligned, "can't handle this");

0N/A // for offsets larger than a simm13 we setup the offset in O7

727N/A __ set(offset, O7);

1909N/A store_offset = store(from_reg, base, O7, type, wide);

0N/A } else {

1909N/A if (type == T_ARRAY || type == T_OBJECT) {

1909N/A __ verify_oop(from_reg->as_register());

1909N/A }

0N/A store_offset = code_offset();

0N/A switch (type) {

0N/A case T_BOOLEAN: // fall through

0N/A case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;

0N/A case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;

0N/A case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;

0N/A case T_INT : __ stw(from_reg->as_register(), base, offset); break;

0N/A case T_LONG :

0N/A#ifdef _LP64

0N/A if (unaligned || PatchALot) {

0N/A __ srax(from_reg->as_register_lo(), 32, O7);

0N/A __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);

0N/A __ stw(O7, base, offset + hi_word_offset_in_bytes);

0N/A } else {

0N/A __ stx(from_reg->as_register_lo(), base, offset);

0N/A }

0N/A#else

0N/A assert(Assembler::is_simm13(offset + 4), "must be");

0N/A __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);

0N/A __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);

0N/A#endif

0N/A break;

1909N/A case T_ADDRESS:

1909N/A __ st_ptr(from_reg->as_register(), base, offset);

1909N/A break;

0N/A case T_ARRAY : // fall through

1909N/A case T_OBJECT:

1909N/A {

1909N/A if (UseCompressedOops && !wide) {

1909N/A __ encode_heap_oop(from_reg->as_register(), G3_scratch);

1909N/A store_offset = code_offset();

1909N/A __ stw(G3_scratch, base, offset);

1909N/A } else {

1909N/A __ st_ptr(from_reg->as_register(), base, offset);

1909N/A }

1909N/A break;

1909N/A }

1909N/A

0N/A case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;

0N/A case T_DOUBLE:

0N/A {

0N/A FloatRegister reg = from_reg->as_double_reg();

0N/A // split unaligned stores

0N/A if (unaligned || PatchALot) {

0N/A assert(Assembler::is_simm13(offset + 4), "must be");

0N/A __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);

0N/A __ stf(FloatRegisterImpl::S, reg, base, offset);

0N/A } else {

0N/A __ stf(FloatRegisterImpl::D, reg, base, offset);

0N/A }

0N/A break;

0N/A }

0N/A default : ShouldNotReachHere();

0N/A }

0N/A }

0N/A return store_offset;

0N/A}

0N/A

0N/A

1909N/Aint LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {

1909N/A if (type == T_ARRAY || type == T_OBJECT) {

1909N/A __ verify_oop(from_reg->as_register());

1909N/A }

0N/A int store_offset = code_offset();

0N/A switch (type) {

0N/A case T_BOOLEAN: // fall through

0N/A case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;

0N/A case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;

0N/A case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;

0N/A case T_INT : __ stw(from_reg->as_register(), base, disp); break;

0N/A case T_LONG :

0N/A#ifdef _LP64

0N/A __ stx(from_reg->as_register_lo(), base, disp);

0N/A#else

0N/A assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");

0N/A __ std(from_reg->as_register_hi(), base, disp);

0N/A#endif

0N/A break;

1909N/A case T_ADDRESS:

1909N/A __ st_ptr(from_reg->as_register(), base, disp);

1909N/A break;

0N/A case T_ARRAY : // fall through

1909N/A case T_OBJECT:

1909N/A {

1909N/A if (UseCompressedOops && !wide) {

1909N/A __ encode_heap_oop(from_reg->as_register(), G3_scratch);

1909N/A store_offset = code_offset();

1909N/A __ stw(G3_scratch, base, disp);

1909N/A } else {

1909N/A __ st_ptr(from_reg->as_register(), base, disp);

1909N/A }

1909N/A break;

1909N/A }

0N/A case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;

0N/A case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;

0N/A default : ShouldNotReachHere();

0N/A }

0N/A return store_offset;

0N/A}

0N/A

0N/A

1909N/Aint LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {

0N/A int load_offset;

0N/A if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {

0N/A assert(base != O7, "destroying register");

0N/A assert(!unaligned, "can't handle this");

0N/A // for offsets larger than a simm13 we setup the offset in O7

727N/A __ set(offset, O7);

1909N/A load_offset = load(base, O7, to_reg, type, wide);

0N/A } else {

0N/A load_offset = code_offset();

0N/A switch(type) {

0N/A case T_BOOLEAN: // fall through

0N/A case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;

0N/A case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;

0N/A case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;

0N/A case T_INT : __ ld(base, offset, to_reg->as_register()); break;

0N/A case T_LONG :

0N/A if (!unaligned) {

0N/A#ifdef _LP64

0N/A __ ldx(base, offset, to_reg->as_register_lo());

0N/A#else

0N/A assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),

0N/A "must be sequential");

0N/A __ ldd(base, offset, to_reg->as_register_hi());

0N/A#endif

0N/A } else {

0N/A#ifdef _LP64

0N/A assert(base != to_reg->as_register_lo(), "can't handle this");

1060N/A assert(O7 != to_reg->as_register_lo(), "can't handle this");

0N/A __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());

1060N/A __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last

0N/A __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());

1060N/A __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());

0N/A#else

0N/A if (base == to_reg->as_register_lo()) {

0N/A __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());

0N/A __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());

0N/A } else {

0N/A __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());

0N/A __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());

0N/A }

0N/A#endif

0N/A }

0N/A break;

1909N/A case T_ADDRESS: __ ld_ptr(base, offset, to_reg->as_register()); break;

0N/A case T_ARRAY : // fall through

1909N/A case T_OBJECT:

1909N/A {

1909N/A if (UseCompressedOops && !wide) {

1909N/A __ lduw(base, offset, to_reg->as_register());

1909N/A __ decode_heap_oop(to_reg->as_register());

1909N/A } else {

1909N/A __ ld_ptr(base, offset, to_reg->as_register());

1909N/A }

1909N/A break;

1909N/A }

0N/A case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;

0N/A case T_DOUBLE:

0N/A {

0N/A FloatRegister reg = to_reg->as_double_reg();

0N/A // split unaligned loads

0N/A if (unaligned || PatchALot) {

1060N/A __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());

1060N/A __ ldf(FloatRegisterImpl::S, base, offset, reg);

0N/A } else {

0N/A __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());

0N/A }

0N/A break;

0N/A }

0N/A default : ShouldNotReachHere();

0N/A }

1909N/A if (type == T_ARRAY || type == T_OBJECT) {

1909N/A __ verify_oop(to_reg->as_register());

1909N/A }

0N/A }

0N/A return load_offset;

0N/A}

0N/A

0N/A

1909N/Aint LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {

0N/A int load_offset = code_offset();

0N/A switch(type) {

0N/A case T_BOOLEAN: // fall through

1909N/A case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;

1909N/A case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;

1909N/A case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;

1909N/A case T_INT : __ ld(base, disp, to_reg->as_register()); break;

1909N/A case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;

0N/A case T_ARRAY : // fall through

1909N/A case T_OBJECT:

1909N/A {

1909N/A if (UseCompressedOops && !wide) {

1909N/A __ lduw(base, disp, to_reg->as_register());

1909N/A __ decode_heap_oop(to_reg->as_register());

1909N/A } else {

1909N/A __ ld_ptr(base, disp, to_reg->as_register());

1909N/A }

1909N/A break;

1909N/A }

0N/A case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;

0N/A case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;

0N/A case T_LONG :

0N/A#ifdef _LP64

0N/A __ ldx(base, disp, to_reg->as_register_lo());

0N/A#else

0N/A assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),

0N/A "must be sequential");

0N/A __ ldd(base, disp, to_reg->as_register_hi());

0N/A#endif

0N/A break;

0N/A default : ShouldNotReachHere();

0N/A }

1909N/A if (type == T_ARRAY || type == T_OBJECT) {

1909N/A __ verify_oop(to_reg->as_register());

1909N/A }

0N/A return load_offset;

0N/A}

0N/A

0N/Avoid LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {

0N/A LIR_Const* c = src->as_constant_ptr();

0N/A switch (c->type()) {

0N/A case T_INT:

1909N/A case T_FLOAT: {

1909N/A Register src_reg = O7;

1909N/A int value = c->as_jint_bits();

1909N/A if (value == 0) {

1909N/A src_reg = G0;

1909N/A } else {

1909N/A __ set(value, O7);

1909N/A }

1909N/A Address addr = frame_map()->address_for_slot(dest->single_stack_ix());

1909N/A __ stw(src_reg, addr.base(), addr.disp());

1909N/A break;

1909N/A }

1297N/A case T_ADDRESS: {

0N/A Register src_reg = O7;

0N/A int value = c->as_jint_bits();

0N/A if (value == 0) {

0N/A src_reg = G0;

0N/A } else {

0N/A __ set(value, O7);

0N/A }

0N/A Address addr = frame_map()->address_for_slot(dest->single_stack_ix());

1909N/A __ st_ptr(src_reg, addr.base(), addr.disp());

0N/A break;

0N/A }

0N/A case T_OBJECT: {

0N/A Register src_reg = O7;

0N/A jobject2reg(c->as_jobject(), src_reg);

0N/A Address addr = frame_map()->address_for_slot(dest->single_stack_ix());

0N/A __ st_ptr(src_reg, addr.base(), addr.disp());

0N/A break;

0N/A }

0N/A case T_LONG:

0N/A case T_DOUBLE: {

0N/A Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());

0N/A

0N/A Register tmp = O7;

0N/A int value_lo = c->as_jint_lo_bits();

0N/A if (value_lo == 0) {

0N/A tmp = G0;

0N/A } else {

0N/A __ set(value_lo, O7);

0N/A }

0N/A __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);

0N/A int value_hi = c->as_jint_hi_bits();

0N/A if (value_hi == 0) {

0N/A tmp = G0;

0N/A } else {

0N/A __ set(value_hi, O7);

0N/A }

0N/A __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);

0N/A break;

0N/A }

0N/A default:

0N/A Unimplemented();

0N/A }

0N/A}

0N/A

0N/A

1909N/Avoid LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {

0N/A LIR_Const* c = src->as_constant_ptr();

0N/A LIR_Address* addr = dest->as_address_ptr();

0N/A Register base = addr->base()->as_pointer_register();

1909N/A int offset = -1;

1909N/A

0N/A switch (c->type()) {

0N/A case T_INT:

1297N/A case T_FLOAT:

1297N/A case T_ADDRESS: {

0N/A LIR_Opr tmp = FrameMap::O7_opr;

0N/A int value = c->as_jint_bits();

0N/A if (value == 0) {

0N/A tmp = FrameMap::G0_opr;

0N/A } else if (Assembler::is_simm13(value)) {

0N/A __ set(value, O7);

0N/A }

0N/A if (addr->index()->is_valid()) {

0N/A assert(addr->disp() == 0, "must be zero");

1909N/A offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);

0N/A } else {

0N/A assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");

1909N/A offset = store(tmp, base, addr->disp(), type, wide, false);

0N/A }

0N/A break;

0N/A }

0N/A case T_LONG:

0N/A case T_DOUBLE: {

0N/A assert(!addr->index()->is_valid(), "can't handle reg reg address here");

0N/A assert(Assembler::is_simm13(addr->disp()) &&

0N/A Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");

0N/A

1909N/A LIR_Opr tmp = FrameMap::O7_opr;

0N/A int value_lo = c->as_jint_lo_bits();

0N/A if (value_lo == 0) {

1909N/A tmp = FrameMap::G0_opr;

0N/A } else {

0N/A __ set(value_lo, O7);

0N/A }

1909N/A offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false);

0N/A int value_hi = c->as_jint_hi_bits();

0N/A if (value_hi == 0) {

1909N/A tmp = FrameMap::G0_opr;

0N/A } else {

0N/A __ set(value_hi, O7);

0N/A }

2890N/A store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false);

0N/A break;